From: Marc Zyngier <maz@kernel.org>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Cc: <kvmarm@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
<will@kernel.org>, <catalin.marinas@arm.com>,
<oliver.upton@linux.dev>, <james.morse@arm.com>,
<suzuki.poulose@arm.com>, <yuzenghui@huawei.com>,
<wangzhou1@hisilicon.com>, <linuxarm@huawei.com>
Subject: Re: [PATCH] KVM: arm64: Make the exposed feature bits in AA64DFR0_EL1 writable from userspace
Date: Tue, 13 Aug 2024 19:20:55 +0100 [thread overview]
Message-ID: <86v804z3lk.wl-maz@kernel.org> (raw)
In-Reply-To: <20240813142835.77180-1-shameerali.kolothum.thodi@huawei.com>
On Tue, 13 Aug 2024 15:28:35 +0100,
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> wrote:
>
> KVM exposes the OS double lock feature bit to Guests but returns
> RAZ/WI on Guest OSDLR_EL1 access. This breaks Guest migration between
> systems where this feature support differ. Add support to make this
> feature writable from userspace by setting the mask bit. While at it,
> set the mask bits for other exposed features in the AA64DFR0_EL1
> register as well.
>
> Also update the selftest to cover these fields.
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
> This is based on the discussion here(Thanks to Oliver),
> https://lore.kernel.org/all/ZrVSlbVwnaMDShah@linux.dev/
> ---
> arch/arm64/kvm/sys_regs.c | 6 +++++-
> tools/testing/selftests/kvm/aarch64/set_id_regs.c | 4 ++++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index c90324060436..adb49d681052 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -2376,7 +2376,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> .get_user = get_id_reg,
> .set_user = set_id_aa64dfr0_el1,
> .reset = read_sanitised_id_aa64dfr0_el1,
> - .val = ID_AA64DFR0_EL1_PMUVer_MASK |
> + .val = ID_AA64DFR0_EL1_DoubleLock_MASK |
> + ID_AA64DFR0_EL1_CTX_CMPs_MASK |
> + ID_AA64DFR0_EL1_WRPs_MASK |
> + ID_AA64DFR0_EL1_BRPs_MASK |
I think this is going to cause some troubles.
The issue is that context-aware breakpoints are the highest-numbered
breakpoints, right after the normal breakpoints (D2.8.3 "Breakpoint
types and linking of breakpoints"). So if you reduce the number of
normal breakpoints, you shift the context-aware ones down, and
everything breaks.
I really don't see how you can safely do that without completely
changing the way we handle the debug registers.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2024-08-13 18:20 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-13 14:28 [PATCH] KVM: arm64: Make the exposed feature bits in AA64DFR0_EL1 writable from userspace Shameer Kolothum
2024-08-13 18:20 ` Marc Zyngier [this message]
2024-08-14 9:17 ` Shameerali Kolothum Thodi
2024-08-15 8:32 ` Marc Zyngier
2024-11-26 17:00 ` Sebastian Ott
2024-11-26 19:29 ` Marc Zyngier
2024-11-27 17:53 ` Sebastian Ott
2024-11-28 9:31 ` Eric Auger
2024-12-01 12:21 ` Marc Zyngier
2024-12-02 8:03 ` Eric Auger
2024-12-02 9:11 ` Marc Zyngier
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