From: Marc Zyngier <maz@kernel.org>
To: Zaid Alali <zaidal@os.amperecomputing.com>
Cc: catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org,
broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com,
ruanjinjie@huawei.com, oliver.upton@linux.dev, robh@kernel.org,
anshuman.khandual@arm.com, james.morse@arm.com,
shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com,
scott@os.amperecomputing.com, joey.gouly@arm.com,
ardb@kernel.org, yangyicong@hisilicon.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative
Date: Wed, 05 Feb 2025 14:14:30 +0000 [thread overview]
Message-ID: <86wme4tr5l.wl-maz@kernel.org> (raw)
In-Reply-To: <Z6KKnpB2IwO9GAYA@zaid-VirtualBox>
On Tue, 04 Feb 2025 21:46:06 +0000,
Zaid Alali <zaidal@os.amperecomputing.com> wrote:
>
> On Tue, Jan 28, 2025 at 08:34:47AM +0000, Marc Zyngier wrote:
> > On Mon, 27 Jan 2025 20:18:29 +0000,
> > Zaid Alali <zaidal@os.amperecomputing.com> wrote:
> > >
> > > Add an alternative code sequence to work around Ampere erratum
> > > AC03_CPU_50 on AmpereOne and Ampere1A.
> > >
> > > Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a
> > > direct read of the register will return a value of 0xf8. An incorrect
> > > value from a direct read can only happen with the value 0xf0.
> >
> > Under which precise conditions? Does it equally apply to virtual
> > interrupts or SCR_EL3.FIQ==0, for which there is no non-secure shift
> > (which I can only assume is the source of the erratum)? Does it
> > equally affect G0 and G1 interrupts?
> >
>
> Hi Marc,
>
> This only occurs when:
> When SCR_EL3.FIQ==1 and PE is NOT in EL3/Secure State,
> and ICC_PMR_EL1.Priority==LowestPriorityImplemented==0xf8 (highest priority is 0x00).
>
> Does it equally apply to virtual interrupts or SCR_EL3.FIQ==0?
>
> Based on this Defect (AArch-21735) and our implementation, it only
> affected ICC_PMR_EL1, therefore does not apply to virtual interrupts.
Are you saying that this is erratum is *strictly* AARCH-21735?
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2025-02-05 14:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-27 20:18 [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative Zaid Alali
2025-01-28 8:34 ` Marc Zyngier
2025-01-28 20:54 ` Oliver Upton
2025-02-04 21:54 ` Zaid Alali
2025-02-04 21:46 ` Zaid Alali
2025-02-05 14:14 ` Marc Zyngier [this message]
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