Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative

[Zaid Alali <zaidal@os.amperecomputing.com>]

On Tue, Jan 28, 2025 at 12:54:26PM -0800, Oliver Upton wrote:
> On Tue, Jan 28, 2025 at 08:34:47AM +0000, Marc Zyngier wrote:
> > > +config AMPERE_ERRATUM_AC03_CPU_50
> > > +	bool "AmpereOne: AC03_CPU_50: Certain checks for ICC_PMR_EL1 that expects the value 0xf0 may read 0xf8 instead"
> > > +	default y
> > > +	help
> > > +	  This option adds an alternative code sequence to work around Ampere
> > > +	  erratum AC03_CPU_50 on AmpereOne and Ampere1A.
> > > +
> > > +	  Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a
> > > +	  direct read of the register will return a value of 0xf8. An incorrect
> > > +	  value from a direct read can only happen with the value 0xf0.
> > > +
> > > +	  The workaround for the erratum will do logical AND 0xf0 to the
> > > +	  value read from ICC_PMR_EL1 register before returning the value.
> > > +
> > > +	  If unsure, say Y.
> > > +
> > 
> > An alternative for this would simply to prevent the enabling of pNMI
> > on this platform.
> 
> There's also AC03_CPU_36, where the CPU goes into the weeds if you take
> an asynchronous exception while fiddling with HCR_EL2. We don't have a
> mitigation for it, and it can be pretty easily reproduced by using pNMIs
> while running VMs.
> 
> So I agree, disabling pNMIs might be the easier way out.
> 
> [*] https://amperecomputing.com/assets/AmpereOne_Developer_ER_v0_80_20240823_28945022f4.pdf
>

We prefer to keep pNMIs enabled if possible since it is useful, and we will send another
patch for AC03_CPU_36 to fix that. If this is not feasible we can send another patch
to disable it in both AC03_CPU_36 and AC03_CPU_50. 
> -- 
> Thanks,
> Oliver