Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
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Cc: Randolph <randolph@andestech.com>
Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
Date: Fri, 23 Feb 2024 10:06:44 +0100	[thread overview]
Message-ID: <871q93eehn.ffs@tglx> (raw)
In-Reply-To: <874jdzef1j.ffs@tglx>

On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote:
> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>>> Palmer, feel free to take this through the riscv tree. I have no other
>>> changes pending against that driver.
>>
>> Aargh. Spoken too early. This conflicts with Anups AIA series.
>>
>>   https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
>>
>> So I rather take the pile through my tree and deal with the conflicts
>> localy than inflicting it on next.
>
>> Palmer?
>
> Nah. I just apply the two intc patches localy and give you a tag to pull
> from so we carry both the same commits. Then I can deal with the
> conflicts on my side trivially.

Here you go:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24

Contains:

  f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
  96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")

on top of v6.8-rc1

Thanks,

        tglx