From: Alistair Popple <apopple@nvidia.com>
To: Peter Xu <peterx@redhat.com>
Cc: "Sierra Guiza, Alejandro \(Alex\)" <alex.sierra@amd.com>,
Ralph Campbell <rcampbell@nvidia.com>,
Lyude Paul <lyude@redhat.com>, Karol Herbst <kherbst@redhat.com>,
David Hildenbrand <david@redhat.com>,
John Hubbard <jhubbard@nvidia.com>,
Felix Kuehling <Felix.Kuehling@amd.com>,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Matthew Wilcox <willy@infradead.org>,
linux-mm@kvack.org, Logan Gunthorpe <logang@deltatee.com>,
Ben Skeggs <bskeggs@redhat.com>, Jason Gunthorpe <jgg@nvidia.com>,
Huang Ying <ying.huang@intel.com>,
stable@vger.kernel.org, akpm@linux-foundation.org,
huang ying <huang.ying.caritas@gmail.com>
Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page
Date: Wed, 17 Aug 2022 11:49:03 +1000 [thread overview]
Message-ID: <871qtfvdlw.fsf@nvdebian.thelocal> (raw)
In-Reply-To: <Yvv/eGfi3LW8WxPZ@xz-m1.local>
Peter Xu <peterx@redhat.com> writes:
> On Tue, Aug 16, 2022 at 04:10:29PM +0800, huang ying wrote:
>> > @@ -193,11 +194,10 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
>> > bool anon_exclusive;
>> > pte_t swp_pte;
>> >
>> > + flush_cache_page(vma, addr, pte_pfn(*ptep));
>> > + pte = ptep_clear_flush(vma, addr, ptep);
>>
>> Although I think it's possible to batch the TLB flushing just before
>> unlocking PTL. The current code looks correct.
>
> If we're with unconditionally ptep_clear_flush(), does it mean we should
> probably drop the "unmapped" and the last flush_tlb_range() already since
> they'll be redundant?
This patch does that, unless I missed something?
> If that'll need to be dropped, it looks indeed better to still keep the
> batch to me but just move it earlier (before unlock iiuc then it'll be
> safe), then we can keep using ptep_get_and_clear() afaiu but keep "pte"
> updated.
I think we would also need to check should_defer_flush(). Looking at
try_to_unmap_one() there is this comment:
if (should_defer_flush(mm, flags) && !anon_exclusive) {
/*
* We clear the PTE but do not flush so potentially
* a remote CPU could still be writing to the folio.
* If the entry was previously clean then the
* architecture must guarantee that a clear->dirty
* transition on a cached TLB entry is written through
* and traps if the PTE is unmapped.
*/
And as I understand it we'd need the same guarantee here. Given
try_to_migrate_one() doesn't do batched TLB flushes either I'd rather
keep the code as consistent as possible between
migrate_vma_collect_pmd() and try_to_migrate_one(). I could look at
introducing TLB flushing for both in some future patch series.
- Alistair
> Thanks,
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Popple <apopple@nvidia.com>
To: Peter Xu <peterx@redhat.com>
Cc: huang ying <huang.ying.caritas@gmail.com>,
linux-mm@kvack.org, akpm@linux-foundation.org,
linux-kernel@vger.kernel.org, "Sierra Guiza,
Alejandro (Alex)" <alex.sierra@amd.com>,
Felix Kuehling <Felix.Kuehling@amd.com>,
Jason Gunthorpe <jgg@nvidia.com>,
John Hubbard <jhubbard@nvidia.com>,
David Hildenbrand <david@redhat.com>,
Ralph Campbell <rcampbell@nvidia.com>,
Matthew Wilcox <willy@infradead.org>,
Karol Herbst <kherbst@redhat.com>, Lyude Paul <lyude@redhat.com>,
Ben Skeggs <bskeggs@redhat.com>,
Logan Gunthorpe <logang@deltatee.com>,
paulus@ozlabs.org, linuxppc-dev@lists.ozlabs.org,
Huang Ying <ying.huang@intel.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page
Date: Wed, 17 Aug 2022 11:49:03 +1000 [thread overview]
Message-ID: <871qtfvdlw.fsf@nvdebian.thelocal> (raw)
In-Reply-To: <Yvv/eGfi3LW8WxPZ@xz-m1.local>
Peter Xu <peterx@redhat.com> writes:
> On Tue, Aug 16, 2022 at 04:10:29PM +0800, huang ying wrote:
>> > @@ -193,11 +194,10 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
>> > bool anon_exclusive;
>> > pte_t swp_pte;
>> >
>> > + flush_cache_page(vma, addr, pte_pfn(*ptep));
>> > + pte = ptep_clear_flush(vma, addr, ptep);
>>
>> Although I think it's possible to batch the TLB flushing just before
>> unlocking PTL. The current code looks correct.
>
> If we're with unconditionally ptep_clear_flush(), does it mean we should
> probably drop the "unmapped" and the last flush_tlb_range() already since
> they'll be redundant?
This patch does that, unless I missed something?
> If that'll need to be dropped, it looks indeed better to still keep the
> batch to me but just move it earlier (before unlock iiuc then it'll be
> safe), then we can keep using ptep_get_and_clear() afaiu but keep "pte"
> updated.
I think we would also need to check should_defer_flush(). Looking at
try_to_unmap_one() there is this comment:
if (should_defer_flush(mm, flags) && !anon_exclusive) {
/*
* We clear the PTE but do not flush so potentially
* a remote CPU could still be writing to the folio.
* If the entry was previously clean then the
* architecture must guarantee that a clear->dirty
* transition on a cached TLB entry is written through
* and traps if the PTE is unmapped.
*/
And as I understand it we'd need the same guarantee here. Given
try_to_migrate_one() doesn't do batched TLB flushes either I'd rather
keep the code as consistent as possible between
migrate_vma_collect_pmd() and try_to_migrate_one(). I could look at
introducing TLB flushing for both in some future patch series.
- Alistair
> Thanks,
next prev parent reply other threads:[~2022-08-17 1:55 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-16 7:39 [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page Alistair Popple
2022-08-16 7:39 ` Alistair Popple
2022-08-16 7:39 ` [PATCH v2 2/2] selftests/hmm-tests: Add test for dirty bits Alistair Popple
2022-08-16 7:39 ` Alistair Popple
2022-08-16 8:10 ` [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page huang ying
2022-08-16 8:10 ` huang ying
2022-08-16 20:35 ` Peter Xu
2022-08-16 20:35 ` Peter Xu
2022-08-17 1:49 ` Alistair Popple [this message]
2022-08-17 1:49 ` Alistair Popple
2022-08-17 2:45 ` Peter Xu
2022-08-17 2:45 ` Peter Xu
2022-08-17 5:41 ` Alistair Popple
2022-08-17 5:41 ` Alistair Popple
2022-08-17 7:17 ` Huang, Ying
2022-08-17 7:17 ` Huang, Ying
2022-08-17 9:41 ` Nadav Amit
2022-08-17 9:41 ` Nadav Amit
2022-08-17 19:27 ` Peter Xu
2022-08-17 19:27 ` Peter Xu
2022-08-18 6:34 ` Huang, Ying
2022-08-18 6:34 ` Huang, Ying
2022-08-18 14:44 ` Peter Xu
2022-08-18 14:44 ` Peter Xu
2022-08-19 2:51 ` Huang, Ying
2022-08-19 2:51 ` Huang, Ying
2022-08-24 1:56 ` Alistair Popple
2022-08-24 1:56 ` Alistair Popple
2022-08-24 20:25 ` Peter Xu
2022-08-24 20:25 ` Peter Xu
2022-08-24 20:48 ` Peter Xu
2022-08-24 20:48 ` Peter Xu
2022-08-25 0:42 ` Alistair Popple
2022-08-25 0:42 ` Alistair Popple
2022-08-25 1:24 ` Alistair Popple
2022-08-25 1:24 ` Alistair Popple
2022-08-25 15:04 ` Peter Xu
2022-08-25 15:04 ` Peter Xu
2022-08-25 22:09 ` Alistair Popple
2022-08-25 22:09 ` Alistair Popple
2022-08-25 23:36 ` Peter Xu
2022-08-25 23:36 ` Peter Xu
2022-08-25 14:40 ` Peter Xu
2022-08-25 14:40 ` Peter Xu
2022-08-18 5:59 ` Huang, Ying
2022-08-18 5:59 ` Huang, Ying
2022-08-17 19:07 ` Peter Xu
2022-08-17 19:07 ` Peter Xu
2022-08-17 1:38 ` Alistair Popple
2022-08-17 1:38 ` Alistair Popple
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