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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more
Date: Wed, 09 Mar 2022 11:30:56 +0200	[thread overview]
Message-ID: <871qzb1nhr.fsf@intel.com> (raw)
In-Reply-To: <20220307233940.4161-8-ville.syrjala@linux.intel.com>

On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
> and the max to 594 MHz (HDMI max). The supported DP frequencies
> (162MHz-540MHz) fit within the same range.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index f4e5290b86a4..7377f1f009ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -285,8 +285,7 @@ static const struct intel_limit intel_limits_chv = {
>  };
>  
>  static const struct intel_limit intel_limits_bxt = {
> -	/* FIXME: find real dot limits */
> -	.dot = { .min = 0, .max = INT_MAX },
> +	.dot = { .min = 25000, .max = 594000 },
>  	.vco = { .min = 4800000, .max = 6700000 },
>  	.n = { .min = 1, .max = 1 },
>  	.m1 = { .min = 2, .max = 2 },

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-03-09  9:31 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
2022-03-09  9:53   ` Jani Nikula
2022-03-09 21:43   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Ville Syrjala
2022-03-09  9:50   ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
2022-03-09  9:22   ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
2022-03-09  9:27   ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
2022-03-09  9:46   ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
2022-03-09  9:30   ` Jani Nikula [this message]
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
2022-03-09  9:34   ` Jani Nikula
2022-03-07 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3) Patchwork
2022-03-08 13:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09  2:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4) Patchwork
2022-03-09  3:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 18:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5) Patchwork
2022-03-09 18:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6) Patchwork
2022-03-09 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10  7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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