From: Marc Zyngier <maz@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Chen-Yu Tsai <wenst@chromium.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
Date: Thu, 12 Aug 2021 14:09:20 +0100 [thread overview]
Message-ID: <871r6yajy7.wl-maz@kernel.org> (raw)
In-Reply-To: <79eabae1-e4a3-7a12-7aa0-3680569584e5@arm.com>
On Thu, 12 Aug 2021 12:51:34 +0100,
Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>
> Hi,
>
> After re-familiarizing myself with the spec, it starting to look to
> me like indeed there's something not quite right (read as: totally
> broken) with my patch.
>
> Arm IHI 0069F, the pseudocode for reading ICC_RPR_EL1 (page 11-797),
> says that the priority returned is unchanged if SCTLR_EL3.FIQ ==
> 0.
Sure, but look at what ICC_RPR_EL1 does for FIQ==1:
<quote>
if HaveEL(EL3) && !IsSecure() && SCR_EL3.FIQ == '1' then
// A Non-secure GIC access and Group 0 inaccessible to Non-secure.
if pPriority<7> == '0' then
// Priority is in Secure half and not visible to Non-secure
Priority = Zeros();
elsif !IsOnes(pPriority) then
// Non-secure access and not idle, so physical priority must be shifted
pPriority<7:0> = (pPriority AND PRIMask())<6:0>:'0';
return ZeroExtend(pPriority);
</quote>
See how the the priority is shifted *left* (bits [6:0] end up in
[7:1])?
> This means that the ICC_RPR_EL1 read will return the secure view
> (the value as it is stored by the GIC) of the priority, so for
> pseudo-nmis it will return (GICD_INT_NMI_PRI >> 1) | 0x80, which
> definitely != GICD_INT_NMI_PRI.
That's not my reading of the pseudocode.
> This is further confirmed by this statement on page 4-67:
>
> "When GICD_CTLR.DS == 0, [..] For Non-secure access to ICC_PMR_EL1
> and ICC_RPR_EL1 when SCR_EL3.FIQ == 0: The Secure, unshifted view
> applies."
>
> I don't know how I missed that during testing.
>
> Did a quick test on the model with PMU NMIs (GICD_CTRL.DS = 0,
> SCTLR_EL2.FIQ = 0), gic_handle_nmi() was not being called at all,
0? Really????
> but when I changed the comparison to gic_read_rpr() ==
> ((GICD_INT_NMI_PRI >> 1) | 0x80), NMIs were being correctly handled
> again.
You have completely lost me. This contradicts what you have written
above.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Chen-Yu Tsai <wenst@chromium.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
Date: Thu, 12 Aug 2021 14:09:20 +0100 [thread overview]
Message-ID: <871r6yajy7.wl-maz@kernel.org> (raw)
In-Reply-To: <79eabae1-e4a3-7a12-7aa0-3680569584e5@arm.com>
On Thu, 12 Aug 2021 12:51:34 +0100,
Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>
> Hi,
>
> After re-familiarizing myself with the spec, it starting to look to
> me like indeed there's something not quite right (read as: totally
> broken) with my patch.
>
> Arm IHI 0069F, the pseudocode for reading ICC_RPR_EL1 (page 11-797),
> says that the priority returned is unchanged if SCTLR_EL3.FIQ ==
> 0.
Sure, but look at what ICC_RPR_EL1 does for FIQ==1:
<quote>
if HaveEL(EL3) && !IsSecure() && SCR_EL3.FIQ == '1' then
// A Non-secure GIC access and Group 0 inaccessible to Non-secure.
if pPriority<7> == '0' then
// Priority is in Secure half and not visible to Non-secure
Priority = Zeros();
elsif !IsOnes(pPriority) then
// Non-secure access and not idle, so physical priority must be shifted
pPriority<7:0> = (pPriority AND PRIMask())<6:0>:'0';
return ZeroExtend(pPriority);
</quote>
See how the the priority is shifted *left* (bits [6:0] end up in
[7:1])?
> This means that the ICC_RPR_EL1 read will return the secure view
> (the value as it is stored by the GIC) of the priority, so for
> pseudo-nmis it will return (GICD_INT_NMI_PRI >> 1) | 0x80, which
> definitely != GICD_INT_NMI_PRI.
That's not my reading of the pseudocode.
> This is further confirmed by this statement on page 4-67:
>
> "When GICD_CTLR.DS == 0, [..] For Non-secure access to ICC_PMR_EL1
> and ICC_RPR_EL1 when SCR_EL3.FIQ == 0: The Secure, unshifted view
> applies."
>
> I don't know how I missed that during testing.
>
> Did a quick test on the model with PMU NMIs (GICD_CTRL.DS = 0,
> SCTLR_EL2.FIQ = 0), gic_handle_nmi() was not being called at all,
0? Really????
> but when I changed the comparison to gic_read_rpr() ==
> ((GICD_INT_NMI_PRI >> 1) | 0x80), NMIs were being correctly handled
> again.
You have completely lost me. This contradicts what you have written
above.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-08-12 13:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-11 17:15 [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used Chen-Yu Tsai
2021-08-11 17:15 ` Chen-Yu Tsai
2021-08-11 18:31 ` Marc Zyngier
2021-08-11 18:31 ` Marc Zyngier
2021-08-12 11:51 ` Alexandru Elisei
2021-08-12 11:51 ` Alexandru Elisei
2021-08-12 13:09 ` Marc Zyngier [this message]
2021-08-12 13:09 ` Marc Zyngier
2021-08-12 14:24 ` Alexandru Elisei
2021-08-12 14:24 ` Alexandru Elisei
2021-08-20 12:58 ` Marc Zyngier
2021-08-20 12:58 ` Marc Zyngier
2021-08-16 15:11 ` Chen-Yu Tsai
2021-08-16 15:11 ` Chen-Yu Tsai
2021-08-20 13:31 ` Alexandru Elisei
2021-08-20 13:31 ` Alexandru Elisei
2021-08-20 13:55 ` Marc Zyngier
2021-08-20 13:55 ` Marc Zyngier
2021-08-20 13:34 ` [irqchip: irq/irqchip-next] " irqchip-bot for Chen-Yu Tsai
2021-08-20 14:05 ` irqchip-bot for Chen-Yu Tsai
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