All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915/cnl: Fix the formulae for register offsets
@ 2018-11-23 19:56 Radhakrishna Sripada
  2018-11-23 20:12 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Radhakrishna Sripada @ 2018-11-23 19:56 UTC (permalink / raw)
  To: intel-gfx

For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..352024756e91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8662,18 +8662,21 @@ enum {
 #define   CHV_EU311_PG_ENABLE		(1 << 1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
-#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
-					      ((slice) % 3) * 0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x34 : 0x2C) \
+					      + ((slice) % 3) * 0x4)
 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
-#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
-					      ((slice) % 3) * 0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
+					      + ((slice) % 3) * 0x8)
 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
-#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
-					      ((slice) % 3) * 0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
+					      + ((slice) % 3) * 0x8)
 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
-- 
2.9.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cnl: Fix the formulae for register offsets
  2018-11-23 19:56 [PATCH] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
@ 2018-11-23 20:12 ` Patchwork
  2018-11-23 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-11-23 20:12 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/cnl: Fix the formulae for register offsets
URL   : https://patchwork.freedesktop.org/series/52960/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f3f5633bd407 drm/i915/cnl: Fix the formulae for register offsets
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6: 
For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices.

-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:8665:
+#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x34 : 0x2C) \
+					      + ((slice) % 3) * 0x4)

-:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects?
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:8673:
+#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
+					      + ((slice) % 3) * 0x8)

-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:8677:
+#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * \
+					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
+					      + ((slice) % 3) * 0x8)

total: 0 errors, 1 warnings, 3 checks, 27 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets
  2018-11-23 19:56 [PATCH] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
  2018-11-23 20:12 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-11-23 20:30 ` Patchwork
  2018-11-23 23:48 ` ✓ Fi.CI.IGT: " Patchwork
  2018-11-26  9:10 ` [PATCH] " Jani Nikula
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-11-23 20:30 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/cnl: Fix the formulae for register offsets
URL   : https://patchwork.freedesktop.org/series/52960/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5196 -> Patchwork_10900 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/52960/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10900 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ctx_create@basic-files:
      {fi-icl-u3}:        PASS -> DMESG-WARN (fdo#107724)

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u2:          NOTRUN -> DMESG-WARN (fdo#107724)

    igt@kms_chamelium@common-hpd-after-suspend:
      fi-icl-u2:          NOTRUN -> DMESG-FAIL (fdo#107732, fdo#103375, fdo#108070)

    {igt@runner@aborted}:
      fi-icl-u2:          NOTRUN -> FAIL (fdo#108070)

    
    ==== Possible fixes ====

    igt@i915_selftest@live_hangcheck:
      fi-bwr-2160:        DMESG-FAIL (fdo#108735) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      {fi-icl-u3}:        FAIL (fdo#103167) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#107732 https://bugs.freedesktop.org/show_bug.cgi?id=107732
  fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
  fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735


== Participating hosts (47 -> 42) ==

  Additional (1): fi-icl-u2 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_5196 -> Patchwork_10900

  CI_DRM_5196: 6faf34996697818131ce4448a696e586b31a574e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4726: f48bebb15d3d2c1e6382e1f11b0aeac06fae6082 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10900: f3f5633bd407af130fc9a569ee54a4ca3aad7c00 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f3f5633bd407 drm/i915/cnl: Fix the formulae for register offsets

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10900/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix the formulae for register offsets
  2018-11-23 19:56 [PATCH] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
  2018-11-23 20:12 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
  2018-11-23 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-11-23 23:48 ` Patchwork
  2018-11-26  9:10 ` [PATCH] " Jani Nikula
  3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-11-23 23:48 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/cnl: Fix the formulae for register offsets
URL   : https://patchwork.freedesktop.org/series/52960/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5196_full -> Patchwork_10900_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10900_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10900_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10900_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@pm_rpm@universal-planes:
      {shard-iclb}:       PASS -> INCOMPLETE

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10900_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_busy@extended-modeset-hang-newfb-render-b:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
      {shard-iclb}:       NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
      shard-kbl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_chv_cursor_fail@pipe-c-64x64-left-edge:
      shard-skl:          PASS -> FAIL (fdo#104671)

    igt@kms_cursor_crc@cursor-128x42-offscreen:
      shard-apl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +6

    igt@kms_cursor_crc@cursor-256x85-sliding:
      shard-skl:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +1

    igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
      shard-skl:          PASS -> FAIL (fdo#103184)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-glk:          PASS -> FAIL (fdo#103167) +2

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          PASS -> FAIL (fdo#105682, fdo#103167)

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
      shard-skl:          PASS -> FAIL (fdo#105682) +1

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
      {shard-iclb}:       PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
      shard-skl:          PASS -> FAIL (fdo#105682, fdo#103167)

    igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
      shard-skl:          PASS -> FAIL (fdo#103167) +5

    igt@kms_plane@pixel-format-pipe-c-planes:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#103166)

    igt@kms_plane@plane-position-covered-pipe-c-planes:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
      shard-skl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
      shard-skl:          PASS -> FAIL (fdo#108145, fdo#107815)

    igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
      shard-skl:          PASS -> FAIL (fdo#107815)

    igt@perf@oa-exponents:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@perf_pmu@rc6-runtime-pm-long:
      {shard-iclb}:       PASS -> FAIL (fdo#105010)
      shard-skl:          PASS -> FAIL (fdo#105010)

    igt@pm_rpm@basic-rte:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@gem_fence_thrash@bo-copy:
      shard-apl:          INCOMPLETE (fdo#103927) -> PASS

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) -> PASS

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      {shard-iclb}:       DMESG-WARN (fdo#107956) -> PASS

    igt@kms_color@pipe-b-ctm-max:
      shard-apl:          FAIL (fdo#108147) -> PASS

    igt@kms_color@pipe-b-legacy-gamma:
      shard-apl:          FAIL (fdo#104782) -> PASS

    igt@kms_color@pipe-c-ctm-max:
      shard-skl:          FAIL (fdo#108147) -> PASS

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-glk:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
      shard-glk:          DMESG-WARN (fdo#105763, fdo#106538) -> PASS +1

    igt@kms_draw_crc@draw-method-xrgb2101010-blt-xtiled:
      shard-skl:          FAIL (fdo#103184) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip@dpms-vs-vblank-race:
      shard-kbl:          DMESG-WARN (fdo#103313, fdo#105345) -> PASS

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-skl:          FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
      {shard-iclb}:       FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
      shard-glk:          DMESG-FAIL (fdo#105763, fdo#106538) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    igt@kms_vblank@pipe-a-ts-continuation-suspend:
      shard-hsw:          FAIL (fdo#104894) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#104894 https://bugs.freedesktop.org/show_bug.cgi?id=104894
  fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
  fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (7 -> 7) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5196 -> Patchwork_10900

  CI_DRM_5196: 6faf34996697818131ce4448a696e586b31a574e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4726: f48bebb15d3d2c1e6382e1f11b0aeac06fae6082 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10900: f3f5633bd407af130fc9a569ee54a4ca3aad7c00 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10900/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix the formulae for register offsets
  2018-11-23 19:56 [PATCH] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
                   ` (2 preceding siblings ...)
  2018-11-23 23:48 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-11-26  9:10 ` Jani Nikula
  3 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2018-11-26  9:10 UTC (permalink / raw)
  To: Radhakrishna Sripada, intel-gfx

On Fri, 23 Nov 2018, Radhakrishna Sripada <radhakrishna.sripada@intel.com> wrote:
> For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices.

Maybe it's time to realize using calculations like this isn't viable
anymore. For a seemingly simple change like this, I think it just takes
too long to review. It just underlines my point that the original was
wrong already.

There macros aren't widely used. Despite the large number of slices, I'd
go for explicitly defining the per-slice registers and using _PICK() to
choose.

BR,
Jani.



>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe8f71..352024756e91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8662,18 +8662,21 @@ enum {
>  #define   CHV_EU311_PG_ENABLE		(1 << 1)
>  
>  #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
> -#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
> -					      ((slice) % 3) * 0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x34 : 0x2C) \
> +					      + ((slice) % 3) * 0x4)
>  #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>  #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
>  #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>  
>  #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
> -#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
> -					      ((slice) % 3) * 0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
> +					      + ((slice) % 3) * 0x8)
>  #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
> -#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> -					      ((slice) % 3) * 0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
> +					      + ((slice) % 3) * 0x8)
>  #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
>  #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
>  #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-11-26  9:10 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-11-23 19:56 [PATCH] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
2018-11-23 20:12 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-11-23 20:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-23 23:48 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-26  9:10 ` [PATCH] " Jani Nikula

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.