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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: "Vivekanandan,
	Balasubramani" <balasubramani.vivekanandan@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Subject: Re: [PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround
Date: Tue, 3 Nov 2026 11:20:24 -0300	[thread overview]
Message-ID: <8733tiq9nb.fsf@intel.com> (raw)
In-Reply-To: <auiH9H2NZGsRZCht@bvivekan-mobl1>

"Vivekanandan, Balasubramani" <balasubramani.vivekanandan@intel.com>
writes:

> On 30.10.2026 19:57, Gustavo Sousa wrote:
>> Re-organize adjust_idledly() so that we return and avoid touching the
>> hardware if no applicable workaround was found.
>> 
>> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
>>  1 file changed, 19 insertions(+), 13 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 01a7baf061eb..32d33c70e7f4 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  	u64 idledly_ps, idledly_hw_ps;
>>  	u64 min_idledly_ps = 0;
>>  	u64 max_idledly_ps = -1;
>> -	bool inhibit_switch = false;
>> +	bool clear_inhibit_switch = false;
>>  	bool wa_applied = false;
>>  
>>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>> @@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  		if (!idledly_units_ps)
>>  			return;
>>  
>> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>> -		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> -		idledly_ps = idledly * idledly_units_ps;
>> -		idledly_hw_ps = idledly_ps;
>> -
>>  		if (XE_GT_WA(gt, 14025941587))
>>  			min_idledly_ps = max(min_idledly_ps, 5000000);
>>  
>> @@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  					       max_idledly_ps,
>>  					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>>  
>> -			/* Clear the inhibit switch without disturbing a valid delay. */
>> -			if (inhibit_switch) {
>> -				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -				wa_applied = true;
>> -			}
>> +			clear_inhibit_switch = true;
>>  		}
>>  
>> +		/* No applicable workaround found. */
>> +		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
>> +			return;
>
> We can skip the check for "max_idledly_ps == -1".

You say that because of the "!clear_inhibit_switch" check?

If so, I would prefer that we keep the check so that we do not tie the
maximum idle delay with the clear_inhibit_switch flag.  It is true that
today the only workaround that defines a maximum idle delay also sets
clear_inhibit_switch, but I think we should make the logic treat those
two things orthogonally, like it is already being done below.

>
> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Thanks! :-)

Let me know if I can go ahead with you r-b on the patch as-is; or if you
prefer to further discuss this.

--
Gustavo Sousa

>
> Regards,
> Bala
>
>> +
>> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>> +
>> +		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
>> +			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> +			wa_applied = true;
>> +		}
>> +
>> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> +		idledly_ps = idledly * idledly_units_ps;
>> +		idledly_hw_ps = idledly_ps;
>> +
>>  		/*
>>  		 * min_idledly_ps is applied before max_idledly_ps, which takes
>>  		 * priority if the two ever conflict (not expected in practice).
>> @@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  
>>  			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
>>  				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
>> -				  !!inhibit_switch, gt->info.timestamp_base);
>> +				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
>> +				  gt->info.timestamp_base);
>>  			xe_mmio_write32(&gt->mmio,
>>  					RING_IDLEDLY(hwe->mmio_base),
>>  					idledly_reg_val);
>> 
>> -- 
>> 2.56.0
>> 

  reply	other threads:[~2026-11-03 14:20 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-30 22:57 [PATCH v2 00/10] drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 01/10] drm/xe: Bail from adjust_idledly() if in VF mode Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 02/10] drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 03/10] drm/xe: Use picosecond as common unit in adjust_idledly() Gustavo Sousa
2026-11-02 18:54   ` Matt Atwood
2026-10-30 22:57 ` [PATCH v2 04/10] drm/xe: Factor out {min,max}_idledly_ps " Gustavo Sousa
2026-11-02 12:42   ` Vivekanandan, Balasubramani
2026-11-03 14:07     ` Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround Gustavo Sousa
2026-11-02 12:54   ` Vivekanandan, Balasubramani
2026-11-03 14:20     ` Gustavo Sousa [this message]
2026-11-04 17:06       ` Matt Atwood
2026-10-30 22:57 ` [PATCH v2 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly() Gustavo Sousa
2026-11-02 12:58   ` Vivekanandan, Balasubramani
2026-10-30 22:57 ` [PATCH v2 07/10] drm/xe: Replace MAXCNT comment with a comment on adjust_idledly() Gustavo Sousa
2026-11-02 18:48   ` Matt Atwood
2026-10-30 22:57 ` [PATCH v2 08/10] drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 09/10] drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds Gustavo Sousa
2026-10-30 22:57 ` [PATCH v2 10/10] drm/xe: Implement Wa_16031259911 Gustavo Sousa
2026-10-30 23:15 ` ✗ CI.checkpatch: warning for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2) Patchwork
2026-10-30 23:17 ` ✓ CI.KUnit: success " Patchwork
2026-10-30 23:53 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-31 19:00 ` ✓ Xe.CI.FULL: " Patchwork

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