[PATCH v2 00/10] drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[PATCH v2 00/10] drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Gustavo Sousa]

There is a new workaround, namely Wa_16031259911, to be added to the
xe driver that applies to graphics IP versions 35.10 and 35.11.  The
workaround is similar to existing ones that apply adjustments to
RING_IDLEDLY.

The current implementation can be improved though: adjust_idledly()
can be cleaned up and refactored to make the code easier to follow
sequentially as well as to add new workarounds (such as
Wa_16031259911); the GuC ADS regset accounting has a subtle issue
where the addition of RING_IDLEDLY is not accounted for.

This series addresses those issues first and then adds the
implementation of Wa_16031259911 as the final step.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v2:
- Change idledly_units_ps and maxcnt_units_ps to u64 in adjust_idledly()
  to avoid 32-bit multiplication overflow. (Sashiko, Matt)
- Replace the call-site comment for adjust_idledly() with a comment at
  the function definition instead of just dropping it. (Matt)
- Link to v1: https://patch.msgid.link/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com

---
Gustavo Sousa (10):
      drm/xe: Bail from adjust_idledly() if in VF mode
      drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule
      drm/xe: Use picosecond as common unit in adjust_idledly()
      drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()
      drm/xe: Bail from adjust_idledly() if no applicable workaround
      drm/xe: Drop early and redundant workaround checks in adjust_idledly()
      drm/xe: Replace MAXCNT comment with a comment on adjust_idledly()
      drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop
      drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds
      drm/xe: Implement Wa_16031259911

 drivers/gpu/drm/xe/xe_guc_ads.c    |  16 ++--
 drivers/gpu/drm/xe/xe_hw_engine.c  | 158 ++++++++++++++++++-------------------
 drivers/gpu/drm/xe/xe_wa.c         |   5 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules |   6 +-
 4 files changed, 93 insertions(+), 92 deletions(-)
---
base-commit: 238c1e3e984e2b7f948cb24165314b8d719a23d6
change-id: 20261021-wa_16031259911-3a83c69d8570

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH v2 01/10] drm/xe: Bail from adjust_idledly() if in VF mode

[Gustavo Sousa]

Both Wa_14025941587 and Wa_16023105232 apply adjustments to
RING_IDLEDLY and take different approaches to avoid SRIOV VF mode.

Let's converge them into a consistent approach.  Since
adjust_idledly() should avoid SRIOV VF irrespective of what
workarounds are enabled, choose to add an early return in that
function instead of having each related workaround add
FUNC(xe_rtp_match_not_sriov_vf) to their rules.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c  | 6 ++++--
 drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 55ee0c892c1e..50e8c5103bdc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -611,8 +611,10 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	bool wa_applied = false;
 	bool clamped_below_maxcnt = false;
 
-	if ((!IS_SRIOV_VF(gt_to_xe(gt)) && XE_GT_WA(gt, 16023105232)) ||
-	    XE_GT_WA(gt, 14025941587)) {
+	if (IS_SRIOV_VF(gt_to_xe(gt)))
+		return;
+
+	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
 		u32 mincnt_idledly_ns = 5000;
 
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 96132c6e3340..0774f6d5a81f 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -74,6 +74,6 @@
 		GRAPHICS_VERSION(3510)
 14026539277	GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)
 14027054324	GRAPHICS_VERSION(3511)
-14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
-		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
+14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
+		MEDIA_VERSION_RANGE(1301, 3503)
 16030224309	GRAPHICS_VERSION_RANGE(3510, 3511)

-- 
2.56.0

[PATCH v2 02/10] drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule

[Gustavo Sousa]

Wa_16023105232 was extended in xe_wa_oob.rules to match extra IP
releases while the respective entry in xe_was[] was overlooked.
Update the latter to be in sync with the former.

Also add comments in the code so that we don't forget to update both
places if new IP versions are added.

Fixes: c96e0df4e9f5 ("drm/xe/xe3: Add support for media IP version 30.02")
Fixes: 4fde66699f1c ("drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05")
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c         | 5 +++--
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c94fe7753f9a..bbe1696a57bc 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -581,8 +581,9 @@ static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
 	},
 	{ XE_RTP_NAME("16023105232"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
-		       GRAPHICS_VERSION_RANGE(2001, 3001)),
+	  /* IP versions need to be in sync with the respective entry in xe_wa_oob.rules. */
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3002), OR,
+		       GRAPHICS_VERSION_RANGE(2001, 3005)),
 	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 0774f6d5a81f..7f8f6cb9b0a1 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -44,6 +44,7 @@
 18013179988	GRAPHICS_VERSION(1255)
 		GRAPHICS_VERSION_RANGE(1270, 1274)
 1508761755	GRAPHICS_VERSION(1255)
+# IP versions need to be in sync with the respective entry in xe_wa.c.
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3005)
 		MEDIA_VERSION_RANGE(1301, 3002)
 16026508708	GRAPHICS_VERSION_RANGE(1200, 3005)

-- 
2.56.0

[PATCH v2 03/10] drm/xe: Use picosecond as common unit in adjust_idledly()

[Gustavo Sousa]

Because gt->info.timestamp_base is given in picoseconds, we lose
precision when calculating the current idle delay in nanoseconds.
Let's avoid that by using picosecond as the common unit of time in
adjust_idledly().

A good side effect of this is that we avoid issuing some integer
divisions.

v2:
  - Change idledly_units_ps and maxcnt_units_ps to u64 to avoid 32-bit
    multiplication overflow. (Sashiko, Matt)

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 55 +++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 50e8c5103bdc..eb99284af3cc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -596,17 +596,19 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	xe_reg_whitelist_process_engine(hwe);
 }
 
-static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps)
+static u32 idledly_floor_ticks(u64 idledly_ps, u64 idledly_units_ps)
 {
-	return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps);
+	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
 }
 
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly, idledly_hw, idledly_reg_val, maxcnt;
-	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
-	u32 maxcnt_units_ns = 640;
+	u32 idledly_reg_val, maxcnt_reg_val;
+	u64 idledly_units_ps = 8 * gt->info.timestamp_base;
+	u64 maxcnt_units_ps = 640000;
+	u64 idledly_ps, idledly_hw_ps;
+	u64 maxcnt_ps;
 	bool inhibit_switch = false;
 	bool wa_applied = false;
 	bool clamped_below_maxcnt = false;
@@ -615,29 +617,27 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 		return;
 
 	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		u32 mincnt_idledly_ns = 5000;
+		u32 mincnt_idledly_ps = 5000000;
 
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps)
 			return;
 
 		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
-		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
-
 		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
-		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
-		idledly_hw = idledly;
-		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
-		maxcnt *= maxcnt_units_ns;
+		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
+		idledly_hw_ps = idledly_ps;
+
+		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
 
 		/*
 		 * Wa_14025941587 is applied before Wa_16023105232, which takes
 		 * priority if the two ever conflict (not expected in practice).
 		 */
 		if (XE_GT_WA(gt, 14025941587) &&
-		    idledly < mincnt_idledly_ns) {
-			idledly = mincnt_idledly_ns;
+		    idledly_ps < mincnt_idledly_ps) {
+			idledly_ps = mincnt_idledly_ps;
 			wa_applied = true;
 		}
 
@@ -649,11 +649,11 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			}
 
 			/* Warn only on the value read from hardware. */
-			xe_gt_WARN_ON(gt, idledly_hw >= maxcnt);
+			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
 
-			if (idledly >= maxcnt) {
+			if (idledly_ps >= maxcnt_ps) {
 				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
-				idledly = maxcnt ? maxcnt - 1 : 0;
+				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
 				clamped_below_maxcnt = true;
 				wa_applied = true;
 			}
@@ -668,10 +668,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			 * Wa_14025941587 minimum survives tick quantization.
 			 */
 			if (clamped_below_maxcnt)
-				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
+				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
 			else
-				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
-								 idledly_units_ps);
+				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
 
 			/*
 			 * Tick quantization can still push the rounded-up value
@@ -679,17 +678,17 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			 * priority even in that case.
 			 */
 			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
-			    (u64)idledly_ticks * idledly_units_ps >= (u64)maxcnt * 1000) {
-				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%u, so flooring\n",
-					  hwe->name, idledly_ticks, maxcnt);
-				idledly = maxcnt ? maxcnt - 1 : 0;
-				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
+			    idledly_ticks * idledly_units_ps >= maxcnt_ps) {
+				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
+					  hwe->name, idledly_ticks, maxcnt_ps);
+				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
+				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
 			}
 
 			idledly_reg_val &= ~IDLE_DELAY;
 			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
-			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
-				  hwe->name, idledly, maxcnt,
+			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
+				  hwe->name, idledly_ps, maxcnt_ps,
 				  !!inhibit_switch, gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),

-- 
2.56.0

[PATCH v2 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[Gustavo Sousa]

The function adjust_idledly() currently does the following adjustments
to the IDLEDLY register:

- Wa_14025941587 defines a minimum value for the idle delay.

- Wa_16023105232 defines a maximum value for the idle delay and also
  unsets INHIBIT_SWITCH_UNTIL_PREEMPTED.

We have an upcoming workaround that will also define a minimum idle
delay.

Let's reorganize the logic in adjust_idledly() in a way to make it
easier to reason about and also easier to extend.

Do that by having the workaround-specific logic only responsible for
defining min_idledly_ps or max_idledly_ps, and then keeping the logic of
how to apply them to the register field (with the right rounding up or
down) separate.

This separation drops the helper function idledly_floor_ticks(), the
clamped_below_maxcnt variable, and the extra quantization check,
arguably making the code easier to follow.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 100 ++++++++++++++++----------------------
 1 file changed, 41 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index eb99284af3cc..01a7baf061eb 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -596,99 +596,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	xe_reg_whitelist_process_engine(hwe);
 }
 
-static u32 idledly_floor_ticks(u64 idledly_ps, u64 idledly_units_ps)
-{
-	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
-}
-
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly_reg_val, maxcnt_reg_val;
+	u32 idledly_reg_val;
+	u32 idledly;
 	u64 idledly_units_ps = 8 * gt->info.timestamp_base;
-	u64 maxcnt_units_ps = 640000;
 	u64 idledly_ps, idledly_hw_ps;
-	u64 maxcnt_ps;
+	u64 min_idledly_ps = 0;
+	u64 max_idledly_ps = -1;
 	bool inhibit_switch = false;
 	bool wa_applied = false;
-	bool clamped_below_maxcnt = false;
 
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
 		return;
 
 	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		u32 mincnt_idledly_ps = 5000000;
-
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps)
 			return;
 
 		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+		idledly_ps = idledly * idledly_units_ps;
 		idledly_hw_ps = idledly_ps;
 
-		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
-		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
-
-		/*
-		 * Wa_14025941587 is applied before Wa_16023105232, which takes
-		 * priority if the two ever conflict (not expected in practice).
-		 */
-		if (XE_GT_WA(gt, 14025941587) &&
-		    idledly_ps < mincnt_idledly_ps) {
-			idledly_ps = mincnt_idledly_ps;
-			wa_applied = true;
-		}
+		if (XE_GT_WA(gt, 14025941587))
+			min_idledly_ps = max(min_idledly_ps, 5000000);
 
 		if (XE_GT_WA(gt, 16023105232)) {
+			u64 maxcnt_units_ps = 640000;
+			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+
+			max_idledly_ps = min_t(u64,
+					       max_idledly_ps,
+					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
+
 			/* Clear the inhibit switch without disturbing a valid delay. */
 			if (inhibit_switch) {
 				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
 				wa_applied = true;
 			}
+		}
 
-			/* Warn only on the value read from hardware. */
-			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
+		/*
+		 * min_idledly_ps is applied before max_idledly_ps, which takes
+		 * priority if the two ever conflict (not expected in practice).
+		 */
+		if (idledly_ps < min_idledly_ps) {
+			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
+			idledly_ps = idledly * idledly_units_ps;
+			wa_applied = true;
+		}
 
-			if (idledly_ps >= maxcnt_ps) {
-				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
-				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
-				clamped_below_maxcnt = true;
-				wa_applied = true;
+		if (idledly_ps >= max_idledly_ps) {
+			if (max_idledly_ps) {
+				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
+				idledly_ps = idledly * idledly_units_ps;
+			} else {
+				idledly = 0;
+				idledly_ps = 0;
 			}
+
+			wa_applied = true;
 		}
 
-		if (wa_applied) {
-			u32 idledly_ticks;
-
-			/*
-			 * Wa_16023105232 requires idledly < maxcnt, so floor
-			 * that clamp; otherwise round up to guarantee the
-			 * Wa_14025941587 minimum survives tick quantization.
-			 */
-			if (clamped_below_maxcnt)
-				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
-			else
-				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
-
-			/*
-			 * Tick quantization can still push the rounded-up value
-			 * to/above maxcnt; re-floor here so Wa_16023105232 keeps
-			 * priority even in that case.
-			 */
-			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
-			    idledly_ticks * idledly_units_ps >= maxcnt_ps) {
-				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
-					  hwe->name, idledly_ticks, maxcnt_ps);
-				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
-				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
-			}
+		/* Warn only if the value read from *hardware* exceeds the maximum. */
+		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
 
+		if (wa_applied) {
 			idledly_reg_val &= ~IDLE_DELAY;
-			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
-			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
-				  hwe->name, idledly_ps, maxcnt_ps,
+			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
+
+			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
+				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
 				  !!inhibit_switch, gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),

-- 
2.56.0

[PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Gustavo Sousa]

Re-organize adjust_idledly() so that we return and avoid touching the
hardware if no applicable workaround was found.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 01a7baf061eb..32d33c70e7f4 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	u64 idledly_ps, idledly_hw_ps;
 	u64 min_idledly_ps = 0;
 	u64 max_idledly_ps = -1;
-	bool inhibit_switch = false;
+	bool clear_inhibit_switch = false;
 	bool wa_applied = false;
 
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
@@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 		if (!idledly_units_ps)
 			return;
 
-		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
-		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
-		idledly_ps = idledly * idledly_units_ps;
-		idledly_hw_ps = idledly_ps;
-
 		if (XE_GT_WA(gt, 14025941587))
 			min_idledly_ps = max(min_idledly_ps, 5000000);
 
@@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 					       max_idledly_ps,
 					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
 
-			/* Clear the inhibit switch without disturbing a valid delay. */
-			if (inhibit_switch) {
-				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
-				wa_applied = true;
-			}
+			clear_inhibit_switch = true;
 		}
 
+		/* No applicable workaround found. */
+		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
+			return;
+
+		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+
+		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
+			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+			wa_applied = true;
+		}
+
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+		idledly_ps = idledly * idledly_units_ps;
+		idledly_hw_ps = idledly_ps;
+
 		/*
 		 * min_idledly_ps is applied before max_idledly_ps, which takes
 		 * priority if the two ever conflict (not expected in practice).
@@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 
 			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
 				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
-				  !!inhibit_switch, gt->info.timestamp_base);
+				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
+				  gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),
 					idledly_reg_val);

-- 
2.56.0

[PATCH v2 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly()

[Gustavo Sousa]

With the latest change, adjust_idledly() now only touches hardware
when necessary and has workaround-specific logic well scoped into
individual "if" statements.  The early workaround checks are now
redundant and can be dropped.  Do that.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 108 +++++++++++++++++++-------------------
 1 file changed, 53 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 32d33c70e7f4..08bd8754ad09 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -611,77 +611,75 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
 		return;
 
-	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
-		if (!idledly_units_ps)
-			return;
+	/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
+	if (!idledly_units_ps)
+		return;
 
-		if (XE_GT_WA(gt, 14025941587))
-			min_idledly_ps = max(min_idledly_ps, 5000000);
+	if (XE_GT_WA(gt, 14025941587))
+		min_idledly_ps = max(min_idledly_ps, 5000000);
 
-		if (XE_GT_WA(gt, 16023105232)) {
-			u64 maxcnt_units_ps = 640000;
-			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+	if (XE_GT_WA(gt, 16023105232)) {
+		u64 maxcnt_units_ps = 640000;
+		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
-			max_idledly_ps = min_t(u64,
-					       max_idledly_ps,
-					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
+		max_idledly_ps = min_t(u64,
+				       max_idledly_ps,
+				       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
 
-			clear_inhibit_switch = true;
-		}
+		clear_inhibit_switch = true;
+	}
 
-		/* No applicable workaround found. */
-		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
-			return;
+	/* No applicable workaround found. */
+	if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
+		return;
 
-		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+	idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 
-		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
-			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
-			wa_applied = true;
-		}
+	if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
+		idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		wa_applied = true;
+	}
+
+	idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+	idledly_ps = idledly * idledly_units_ps;
+	idledly_hw_ps = idledly_ps;
 
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+	/*
+	 * min_idledly_ps is applied before max_idledly_ps, which takes
+	 * priority if the two ever conflict (not expected in practice).
+	 */
+	if (idledly_ps < min_idledly_ps) {
+		idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
 		idledly_ps = idledly * idledly_units_ps;
-		idledly_hw_ps = idledly_ps;
+		wa_applied = true;
+	}
 
-		/*
-		 * min_idledly_ps is applied before max_idledly_ps, which takes
-		 * priority if the two ever conflict (not expected in practice).
-		 */
-		if (idledly_ps < min_idledly_ps) {
-			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
+	if (idledly_ps >= max_idledly_ps) {
+		if (max_idledly_ps) {
+			idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
 			idledly_ps = idledly * idledly_units_ps;
-			wa_applied = true;
+		} else {
+			idledly = 0;
+			idledly_ps = 0;
 		}
 
-		if (idledly_ps >= max_idledly_ps) {
-			if (max_idledly_ps) {
-				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
-				idledly_ps = idledly * idledly_units_ps;
-			} else {
-				idledly = 0;
-				idledly_ps = 0;
-			}
-
-			wa_applied = true;
-		}
+		wa_applied = true;
+	}
 
-		/* Warn only if the value read from *hardware* exceeds the maximum. */
-		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
+	/* Warn only if the value read from *hardware* exceeds the maximum. */
+	xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
 
-		if (wa_applied) {
-			idledly_reg_val &= ~IDLE_DELAY;
-			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
+	if (wa_applied) {
+		idledly_reg_val &= ~IDLE_DELAY;
+		idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
 
-			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
-				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
-				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
-				  gt->info.timestamp_base);
-			xe_mmio_write32(&gt->mmio,
-					RING_IDLEDLY(hwe->mmio_base),
-					idledly_reg_val);
-		}
+		xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
+			  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
+			  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
+			  gt->info.timestamp_base);
+		xe_mmio_write32(&gt->mmio,
+				RING_IDLEDLY(hwe->mmio_base),
+				idledly_reg_val);
 	}
 }
 

-- 
2.56.0

[PATCH v2 07/10] drm/xe: Replace MAXCNT comment with a comment on adjust_idledly()

[Gustavo Sousa]

The adjust_idledly() function does more than what the comment on the
call site says.  Drop that outdated comment and document
adjust_idledly() at its definition instead.

v2:
  - Add a comment above adjust_idledly() instead of just dropping the
    call-site comment. (Matt)

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 08bd8754ad09..7950e118ee1d 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -596,6 +596,9 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	xe_reg_whitelist_process_engine(hwe);
 }
 
+/*
+ * Apply workarounds that require adjustments to RING_IDLEDLY.
+ */
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
@@ -719,7 +722,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
 			xe_hw_engine_enable_ring(hwe);
 	}
 
-	/* Ensure IDLEDLY is lower than MAXCNT */
 	adjust_idledly(hwe);
 
 	return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);

-- 
2.56.0

[PATCH v2 08/10] drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop

[Gustavo Sousa]

The regset size increment for Wa_1607983814 is correct with today's
hardware, because the maximum number RCS per GT is one.  That said, it
is arguably more accurate to make that calculation inside the
for_each_hw_engine() loop, where we can mimic the same conditions used
by guc_mmio_regset_write().

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 43a2951a66d6..a67d3405b10f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -220,14 +220,15 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 	enum xe_hw_engine_id id;
 	unsigned int count = 0;
 
-	for_each_hw_engine(hwe, gt, id)
+	for_each_hw_engine(hwe, gt, id) {
 		xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
 			count++;
 
-	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
+		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
+			count += LNCFCMOCS_REG_COUNT;
+	}
 
-	if (XE_GT_WA(gt, 1607983814))
-		count += LNCFCMOCS_REG_COUNT;
+	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
 
 	return count * sizeof(struct guc_mmio_reg);
 }

-- 
2.56.0

[PATCH v2 09/10] drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds

[Gustavo Sousa]

We need to keep calculate_regset_size() in sync with
guc_mmio_regset_write(). They became out of sync when RING_IDLEDLY was
added.

This likely went unnoticed because ADS_REGSET_EXTRA_MAX - being
greater than the current size of extra_regs - inadvertently provided
some extra room in the regset, which ended up being used for
RING_IDLEDLY.

However, we should not rely on that. We should make
ADS_REGSET_EXTRA_MAX strictly about extra_regs, and explicitly account
for the RING_IDLEDLY register.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index a67d3405b10f..2e738d205738 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -226,6 +226,9 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 
 		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
 			count += LNCFCMOCS_REG_COUNT;
+
+		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+			count++; /* RING_IDLEDLY */
 	}
 
 	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;

-- 
2.56.0

[PATCH v2 10/10] drm/xe: Implement Wa_16031259911

[Gustavo Sousa]

Implement Wa_16031259911, which applies to graphics version 35.10 and
35.11.  The workaround definition instructs us to set the minimum idle
delay value to 2 times the memory read delay, and tells that using 1
unit of the IDLE_DELAY field covers that minimum.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    | 6 ++++--
 drivers/gpu/drm/xe/xe_hw_engine.c  | 3 +++
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 2e738d205738..7f830122ae16 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -227,7 +227,8 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
 			count += LNCFCMOCS_REG_COUNT;
 
-		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
+		    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
 			count++; /* RING_IDLEDLY */
 	}
 
@@ -875,7 +876,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
 		}
 	}
 
-	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
+	    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
 		guc_mmio_regset_write_one(ads, regset_map,
 					  RING_IDLEDLY(hwe->mmio_base),
 					  count++);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 7950e118ee1d..7f304b9fe0e1 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -621,6 +621,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	if (XE_GT_WA(gt, 14025941587))
 		min_idledly_ps = max(min_idledly_ps, 5000000);
 
+	if (XE_GT_WA(gt, 16031259911) && xe_gt_supports_multi_queue(gt, hwe->class))
+		min_idledly_ps = max(min_idledly_ps, idledly_units_ps);
+
 	if (XE_GT_WA(gt, 16023105232)) {
 		u64 maxcnt_units_ps = 640000;
 		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 7f8f6cb9b0a1..e7df4f52184c 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -78,3 +78,4 @@
 14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
 		MEDIA_VERSION_RANGE(1301, 3503)
 16030224309	GRAPHICS_VERSION_RANGE(3510, 3511)
+16031259911	GRAPHICS_VERSION_RANGE(3510, 3511)

-- 
2.56.0

✗ CI.checkpatch: warning for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)
URL   : https://patchwork.freedesktop.org/series/176761/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2a3913f545e210e724330d92b7fc4def5471a744
Author: Gustavo Sousa <gustavo.sousa@intel.com>
Date:   Fri Oct 30 19:57:49 2026 -0300

    drm/xe: Implement Wa_16031259911
    
    Implement Wa_16031259911, which applies to graphics version 35.10 and
    35.11.  The workaround definition instructs us to set the minimum idle
    delay value to 2 times the memory read delay, and tells that using 1
    unit of the IDLE_DELAY field covers that minimum.
    
    Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
    Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+ /mt/dim checkpatch 238c1e3e984e2b7f948cb24165314b8d719a23d6 drm-intel
9f4851f1760f drm/xe: Bail from adjust_idledly() if in VF mode
298307497b07 drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule
98069b800ef1 drm/xe: Use picosecond as common unit in adjust_idledly()
a679429b29d4 drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()
-:98: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#98: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:634:
+					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);

total: 0 errors, 1 warnings, 0 checks, 140 lines checked
b686e8d38785 drm/xe: Bail from adjust_idledly() if no applicable workaround
7359ea9f9a90 drm/xe: Drop early and redundant workaround checks in adjust_idledly()
69703bc6dce8 drm/xe: Replace MAXCNT comment with a comment on adjust_idledly()
2ed88bebc11b drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop
e26d7ee8f14b drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds
2a3913f545e2 drm/xe: Implement Wa_16031259911
-:24: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#24: FILE: drivers/gpu/drm/xe/xe_guc_ads.c:231:
+		    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))

total: 0 errors, 1 warnings, 0 checks, 31 lines checked

✓ CI.KUnit: success for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)
URL   : https://patchwork.freedesktop.org/series/176761/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[23:15:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:15:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:15:43] Starting KUnit Kernel (1/1)...
[23:15:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:15:43] ================= gpu_buddy (14 subtests) ==================
[23:15:43] [PASSED] gpu_test_buddy_alloc_limit
[23:15:43] [PASSED] gpu_test_buddy_alloc_optimistic
[23:15:43] [PASSED] gpu_test_buddy_alloc_pessimistic
[23:15:43] [PASSED] gpu_test_buddy_alloc_pathological
[23:15:43] [PASSED] gpu_test_buddy_alloc_contiguous
[23:15:43] [PASSED] gpu_test_buddy_alloc_clear
[23:15:43] [PASSED] gpu_test_buddy_alloc_range
[23:15:43] [PASSED] gpu_test_buddy_alloc_range_bias
[23:15:44] [PASSED] gpu_test_buddy_fragmentation_performance
[23:15:45] [PASSED] gpu_test_buddy_dirty_tracker_performance
[23:15:45] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[23:15:45] [PASSED] gpu_test_buddy_offset_aligned_allocation
[23:15:45] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[23:15:45] [PASSED] gpu_test_buddy_addr_to_block
[23:15:45] ==================== [PASSED] gpu_buddy ====================
[23:15:45] ============================================================
[23:15:45] Testing complete. Ran 14 tests: passed: 14
[23:15:45] Elapsed time: 26.669s total, 4.448s configuring, 20.353s building, 1.814s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:15:45] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:15:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:16:26] Starting KUnit Kernel (1/1)...
[23:16:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:16:26] ================== guc_buf (11 subtests) ===================
[23:16:26] [PASSED] test_smallest
[23:16:26] [PASSED] test_largest
[23:16:26] [PASSED] test_granular
[23:16:26] [PASSED] test_unique
[23:16:26] [PASSED] test_overlap
[23:16:26] [PASSED] test_reusable
[23:16:26] [PASSED] test_too_big
[23:16:26] [PASSED] test_flush
[23:16:26] [PASSED] test_lookup
[23:16:26] [PASSED] test_data
[23:16:26] [PASSED] test_class
[23:16:26] ===================== [PASSED] guc_buf =====================
[23:16:26] =================== guc_dbm (7 subtests) ===================
[23:16:26] [PASSED] test_empty
[23:16:26] [PASSED] test_default
[23:16:26] ======================== test_size  ========================
[23:16:26] [PASSED] 4
[23:16:26] [PASSED] 8
[23:16:26] [PASSED] 32
[23:16:26] [PASSED] 256
[23:16:26] ==================== [PASSED] test_size ====================
[23:16:26] ======================= test_reuse  ========================
[23:16:26] [PASSED] 4
[23:16:26] [PASSED] 8
[23:16:26] [PASSED] 32
[23:16:26] [PASSED] 256
[23:16:26] =================== [PASSED] test_reuse ====================
[23:16:26] =================== test_range_overlap  ====================
[23:16:26] [PASSED] 4
[23:16:26] [PASSED] 8
[23:16:26] [PASSED] 32
[23:16:26] [PASSED] 256
[23:16:26] =============== [PASSED] test_range_overlap ================
[23:16:26] =================== test_range_compact  ====================
[23:16:26] [PASSED] 4
[23:16:26] [PASSED] 8
[23:16:26] [PASSED] 32
[23:16:26] [PASSED] 256
[23:16:26] =============== [PASSED] test_range_compact ================
[23:16:26] ==================== test_range_spare  =====================
[23:16:26] [PASSED] 4
[23:16:26] [PASSED] 8
[23:16:26] [PASSED] 32
[23:16:26] [PASSED] 256
[23:16:26] ================ [PASSED] test_range_spare =================
[23:16:26] ===================== [PASSED] guc_dbm =====================
[23:16:26] ================== guc_idm (22 subtests) ===================
[23:16:26] [PASSED] bad_init
[23:16:26] [PASSED] no_init
[23:16:26] [PASSED] init_fini
[23:16:26] [PASSED] check_init_small
[23:16:26] [PASSED] check_init_shared
[23:16:26] [PASSED] check_used
[23:16:26] [PASSED] check_quota
[23:16:26] [PASSED] check_all
[23:16:26] [PASSED] check_limits
[23:16:26] [PASSED] check_overlap
[23:16:26] [PASSED] check_overlap_alloc
[23:16:26] [PASSED] check_overlap_release
[23:16:26] [PASSED] check_overlap_partial_init
[23:16:26] [PASSED] check_overlap_partial_shared_range_blocking
[23:16:26] [PASSED] check_used_usable
[23:16:26] [PASSED] check_used_shareable
[23:16:26] [PASSED] check_used_mixed
[23:16:26] [PASSED] check_release_usable_range
[23:16:26] [PASSED] check_release_shareable_range
[23:16:26] [PASSED] check_split_boundaries
[23:16:26] [PASSED] check_shareable_spare
[23:16:26] [PASSED] check_shareable_spare_fragmented_tail
[23:16:26] ===================== [PASSED] guc_idm =====================
[23:16:26] ============== guc_klv_helpers (13 subtests) ===============
[23:16:26] [PASSED] test_count
[23:16:26] [PASSED] test_encode_u32
[23:16:26] [PASSED] test_encode_u64
[23:16:26] [PASSED] test_encode_string
[23:16:26] [PASSED] test_encode_object_raw
[23:16:26] [PASSED] test_encode_object_klv
[23:16:26] [PASSED] test_encode_object_nested
[23:16:26] [PASSED] test_encode_object_basic
[23:16:26] ===================== test_decode_u16  =====================
[23:16:26] [PASSED] empty
[23:16:26] [PASSED] valid
[23:16:26] [PASSED] max
[23:16:26] [PASSED] big
[23:16:26] [PASSED] long
[23:16:26] ================= [PASSED] test_decode_u16 =================
[23:16:26] ===================== test_decode_u32  =====================
[23:16:26] [PASSED] empty
[23:16:26] [PASSED] valid
[23:16:26] [PASSED] max
[23:16:26] [PASSED] long
[23:16:26] ================= [PASSED] test_decode_u32 =================
[23:16:26] ===================== test_decode_u64  =====================
[23:16:26] [PASSED] empty
[23:16:26] [PASSED] short
[23:16:26] [PASSED] valid
[23:16:26] [PASSED] max
[23:16:26] [PASSED] long
[23:16:26] ================= [PASSED] test_decode_u64 =================
[23:16:26] ===================== test_decode_str  =====================
[23:16:26] [PASSED] empty
[23:16:26] [PASSED] one
[23:16:26] [PASSED] one_trash
[23:16:26] [PASSED] two
[23:16:26] [PASSED] two_trash
[23:16:26] [PASSED] three
[23:16:26] [PASSED] dword
[23:16:26] [PASSED] four
[23:16:26] [PASSED] five
[23:16:26] [PASSED] six
[23:16:26] [PASSED] seven
[23:16:26] [PASSED] qword
[23:16:26] ================= [PASSED] test_decode_str =================
[23:16:26] [PASSED] test_print
[23:16:26] ================= [PASSED] guc_klv_helpers =================
[23:16:26] =================== xe_log (4 subtests) ====================
[23:16:26] [PASSED] demo_cper
[23:16:26] [PASSED] demo_dmesg
[23:16:26] ======================= test_dmesg  ========================
[23:16:26] [PASSED] test_fatal
[23:16:26] [PASSED] test_fatal_tile
[23:16:26] [PASSED] test_fatal_gt
[23:16:26] [PASSED] test_fatal_comp
[23:16:26] [PASSED] test_fatal_comp_tile
[23:16:26] [PASSED] test_fatal_comp_gt
[23:16:26] [PASSED] test_fatal_all
[23:16:26] [PASSED] test_recoverable
[23:16:26] [PASSED] test_recoverable_tile
[23:16:26] [PASSED] test_recoverable_gt
[23:16:26] [PASSED] test_recoverable_comp
[23:16:26] [PASSED] test_recoverable_comp_tile
[23:16:26] [PASSED] test_recoverable_comp_gt
[23:16:26] [PASSED] test_recoverable_all
[23:16:26] [PASSED] test_info
[23:16:26] [PASSED] test_info_tile
[23:16:26] [PASSED] test_info_gt
[23:16:26] [PASSED] test_info_err
[23:16:26] [PASSED] test_info_comp
[23:16:26] [PASSED] test_info_comp_tile
[23:16:26] [PASSED] test_info_comp_gt
[23:16:26] [PASSED] test_info_all
[23:16:26] [PASSED] test_hw_fatal
[23:16:26] [PASSED] test_hw_recoverable
[23:16:26] [PASSED] test_hw_corrected
[23:16:26] [PASSED] test_hw_informational
[23:16:26] =================== [PASSED] test_dmesg ====================
[23:16:26] ====================== test_invalid  =======================
[23:16:26] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[23:16:26] ================== [SKIPPED] test_invalid ==================
[23:16:26] ===================== [PASSED] xe_log ======================
[23:16:26] ================== no_relay (3 subtests) ===================
[23:16:26] [PASSED] xe_drops_guc2pf_if_not_ready
[23:16:26] [PASSED] xe_drops_guc2vf_if_not_ready
[23:16:26] [PASSED] xe_rejects_send_if_not_ready
[23:16:26] ==================== [PASSED] no_relay =====================
[23:16:26] ================== pf_relay (14 subtests) ==================
[23:16:26] [PASSED] pf_rejects_guc2pf_too_short
[23:16:26] [PASSED] pf_rejects_guc2pf_too_long
[23:16:26] [PASSED] pf_rejects_guc2pf_no_payload
[23:16:26] [PASSED] pf_fails_no_payload
[23:16:26] [PASSED] pf_fails_bad_origin
[23:16:26] [PASSED] pf_fails_bad_type
[23:16:26] [PASSED] pf_txn_reports_error
[23:16:26] [PASSED] pf_txn_sends_pf2guc
[23:16:26] [PASSED] pf_sends_pf2guc
[23:16:26] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:16:26] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:16:26] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:16:26] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:16:26] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:16:26] ==================== [PASSED] pf_relay =====================
[23:16:26] ================== vf_relay (3 subtests) ===================
[23:16:26] [PASSED] vf_rejects_guc2vf_too_short
[23:16:26] [PASSED] vf_rejects_guc2vf_too_long
[23:16:26] [PASSED] vf_rejects_guc2vf_no_payload
[23:16:26] ==================== [PASSED] vf_relay =====================
[23:16:26] ================ pf_gt_config (9 subtests) =================
[23:16:26] [PASSED] fair_contexts_1vf
[23:16:26] [PASSED] fair_doorbells_1vf
[23:16:26] [PASSED] fair_ggtt_1vf
[23:16:26] ====================== fair_vram_1vf  ======================
[23:16:26] [PASSED] 3.50 GiB
[23:16:26] [PASSED] 11.5 GiB
[23:16:26] [PASSED] 15.5 GiB
[23:16:26] [PASSED] 31.5 GiB
[23:16:26] [PASSED] 63.5 GiB
[23:16:26] [PASSED] 1.91 GiB
[23:16:26] ================== [PASSED] fair_vram_1vf ==================
[23:16:26] ================ fair_vram_1vf_admin_only  =================
[23:16:26] [PASSED] 3.50 GiB
[23:16:26] [PASSED] 11.5 GiB
[23:16:26] [PASSED] 15.5 GiB
[23:16:26] [PASSED] 31.5 GiB
[23:16:26] [PASSED] 63.5 GiB
[23:16:26] [PASSED] 1.91 GiB
[23:16:26] ============ [PASSED] fair_vram_1vf_admin_only =============
[23:16:26] ====================== fair_contexts  ======================
[23:16:26] [PASSED] 1 VF
[23:16:26] [PASSED] 2 VFs
[23:16:26] [PASSED] 3 VFs
[23:16:26] [PASSED] 4 VFs
[23:16:26] [PASSED] 5 VFs
[23:16:26] [PASSED] 6 VFs
[23:16:26] [PASSED] 7 VFs
[23:16:26] [PASSED] 8 VFs
[23:16:26] [PASSED] 9 VFs
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[23:16:26] [PASSED] 37 VFs
[23:16:26] [PASSED] 38 VFs
[23:16:26] [PASSED] 39 VFs
[23:16:26] [PASSED] 40 VFs
[23:16:26] [PASSED] 41 VFs
[23:16:26] [PASSED] 42 VFs
[23:16:26] [PASSED] 43 VFs
[23:16:26] [PASSED] 44 VFs
[23:16:26] [PASSED] 45 VFs
[23:16:26] [PASSED] 46 VFs
[23:16:26] [PASSED] 47 VFs
[23:16:26] [PASSED] 48 VFs
[23:16:26] [PASSED] 49 VFs
[23:16:26] [PASSED] 50 VFs
[23:16:26] [PASSED] 51 VFs
[23:16:26] [PASSED] 52 VFs
[23:16:26] [PASSED] 53 VFs
[23:16:26] [PASSED] 54 VFs
[23:16:26] [PASSED] 55 VFs
[23:16:26] [PASSED] 56 VFs
[23:16:26] [PASSED] 57 VFs
[23:16:26] [PASSED] 58 VFs
[23:16:26] [PASSED] 59 VFs
[23:16:26] [PASSED] 60 VFs
[23:16:26] [PASSED] 61 VFs
[23:16:26] [PASSED] 62 VFs
[23:16:26] [PASSED] 63 VFs
[23:16:26] ================== [PASSED] fair_contexts ==================
[23:16:26] ===================== fair_doorbells  ======================
[23:16:26] [PASSED] 1 VF
[23:16:26] [PASSED] 2 VFs
[23:16:26] [PASSED] 3 VFs
[23:16:26] [PASSED] 4 VFs
[23:16:26] [PASSED] 5 VFs
[23:16:26] [PASSED] 6 VFs
[23:16:26] [PASSED] 7 VFs
[23:16:26] [PASSED] 8 VFs
[23:16:26] [PASSED] 9 VFs
[23:16:26] [PASSED] 10 VFs
[23:16:26] [PASSED] 11 VFs
[23:16:26] [PASSED] 12 VFs
[23:16:26] [PASSED] 13 VFs
[23:16:26] [PASSED] 14 VFs
[23:16:26] [PASSED] 15 VFs
[23:16:26] [PASSED] 16 VFs
[23:16:26] [PASSED] 17 VFs
[23:16:26] [PASSED] 18 VFs
[23:16:26] [PASSED] 19 VFs
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[23:16:26] [PASSED] 21 VFs
[23:16:26] [PASSED] 22 VFs
[23:16:26] [PASSED] 23 VFs
[23:16:26] [PASSED] 24 VFs
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[23:16:26] [PASSED] 28 VFs
[23:16:26] [PASSED] 29 VFs
[23:16:26] [PASSED] 30 VFs
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[23:16:26] [PASSED] 32 VFs
[23:16:26] [PASSED] 33 VFs
[23:16:26] [PASSED] 34 VFs
[23:16:26] [PASSED] 35 VFs
[23:16:26] [PASSED] 36 VFs
[23:16:26] [PASSED] 37 VFs
[23:16:26] [PASSED] 38 VFs
[23:16:26] [PASSED] 39 VFs
[23:16:26] [PASSED] 40 VFs
[23:16:26] [PASSED] 41 VFs
[23:16:26] [PASSED] 42 VFs
[23:16:26] [PASSED] 43 VFs
[23:16:26] [PASSED] 44 VFs
[23:16:26] [PASSED] 45 VFs
[23:16:26] [PASSED] 46 VFs
[23:16:26] [PASSED] 47 VFs
[23:16:26] [PASSED] 48 VFs
[23:16:26] [PASSED] 49 VFs
[23:16:26] [PASSED] 50 VFs
[23:16:26] [PASSED] 51 VFs
[23:16:26] [PASSED] 52 VFs
[23:16:26] [PASSED] 53 VFs
[23:16:26] [PASSED] 54 VFs
[23:16:26] [PASSED] 55 VFs
[23:16:26] [PASSED] 56 VFs
[23:16:26] [PASSED] 57 VFs
[23:16:26] [PASSED] 58 VFs
[23:16:26] [PASSED] 59 VFs
[23:16:26] [PASSED] 60 VFs
[23:16:26] [PASSED] 61 VFs
[23:16:26] [PASSED] 62 VFs
[23:16:26] [PASSED] 63 VFs
[23:16:26] ================= [PASSED] fair_doorbells ==================
[23:16:26] ======================== fair_ggtt  ========================
[23:16:26] [PASSED] 1 VF
[23:16:26] [PASSED] 2 VFs
[23:16:26] [PASSED] 3 VFs
[23:16:26] [PASSED] 4 VFs
[23:16:26] [PASSED] 5 VFs
[23:16:26] [PASSED] 6 VFs
[23:16:26] [PASSED] 7 VFs
[23:16:26] [PASSED] 8 VFs
[23:16:26] [PASSED] 9 VFs
[23:16:26] [PASSED] 10 VFs
[23:16:26] [PASSED] 11 VFs
[23:16:26] [PASSED] 12 VFs
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[23:16:26] [PASSED] 44 VFs
[23:16:26] [PASSED] 45 VFs
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[23:16:26] [PASSED] 48 VFs
[23:16:26] [PASSED] 49 VFs
[23:16:26] [PASSED] 50 VFs
[23:16:26] [PASSED] 51 VFs
[23:16:26] [PASSED] 52 VFs
[23:16:26] [PASSED] 53 VFs
[23:16:27] [PASSED] 54 VFs
[23:16:27] [PASSED] 55 VFs
[23:16:27] [PASSED] 56 VFs
[23:16:27] [PASSED] 57 VFs
[23:16:27] [PASSED] 58 VFs
[23:16:27] [PASSED] 59 VFs
[23:16:27] [PASSED] 60 VFs
[23:16:27] [PASSED] 61 VFs
[23:16:27] [PASSED] 62 VFs
[23:16:27] [PASSED] 63 VFs
[23:16:27] ==================== [PASSED] fair_ggtt ====================
[23:16:27] ======================== fair_vram  ========================
[23:16:27] [PASSED] 1 VF
[23:16:27] [PASSED] 2 VFs
[23:16:27] [PASSED] 3 VFs
[23:16:27] [PASSED] 4 VFs
[23:16:27] [PASSED] 5 VFs
[23:16:27] [PASSED] 6 VFs
[23:16:27] [PASSED] 7 VFs
[23:16:27] [PASSED] 8 VFs
[23:16:27] [PASSED] 9 VFs
[23:16:27] [PASSED] 10 VFs
[23:16:27] [PASSED] 11 VFs
[23:16:27] [PASSED] 12 VFs
[23:16:27] [PASSED] 13 VFs
[23:16:27] [PASSED] 14 VFs
[23:16:27] [PASSED] 15 VFs
[23:16:27] [PASSED] 16 VFs
[23:16:27] [PASSED] 17 VFs
[23:16:27] [PASSED] 18 VFs
[23:16:27] [PASSED] 19 VFs
[23:16:27] [PASSED] 20 VFs
[23:16:27] [PASSED] 21 VFs
[23:16:27] [PASSED] 22 VFs
[23:16:27] [PASSED] 23 VFs
[23:16:27] [PASSED] 24 VFs
[23:16:27] [PASSED] 25 VFs
[23:16:27] [PASSED] 26 VFs
[23:16:27] [PASSED] 27 VFs
[23:16:27] [PASSED] 28 VFs
[23:16:27] [PASSED] 29 VFs
[23:16:27] [PASSED] 30 VFs
[23:16:27] [PASSED] 31 VFs
[23:16:27] [PASSED] 32 VFs
[23:16:27] [PASSED] 33 VFs
[23:16:27] [PASSED] 34 VFs
[23:16:27] [PASSED] 35 VFs
[23:16:27] [PASSED] 36 VFs
[23:16:27] [PASSED] 37 VFs
[23:16:27] [PASSED] 38 VFs
[23:16:27] [PASSED] 39 VFs
[23:16:27] [PASSED] 40 VFs
[23:16:27] [PASSED] 41 VFs
[23:16:27] [PASSED] 42 VFs
[23:16:27] [PASSED] 43 VFs
[23:16:27] [PASSED] 44 VFs
[23:16:27] [PASSED] 45 VFs
[23:16:27] [PASSED] 46 VFs
[23:16:27] [PASSED] 47 VFs
[23:16:27] [PASSED] 48 VFs
[23:16:27] [PASSED] 49 VFs
[23:16:27] [PASSED] 50 VFs
[23:16:27] [PASSED] 51 VFs
[23:16:27] [PASSED] 52 VFs
[23:16:27] [PASSED] 53 VFs
[23:16:27] [PASSED] 54 VFs
[23:16:27] [PASSED] 55 VFs
[23:16:27] [PASSED] 56 VFs
[23:16:27] [PASSED] 57 VFs
[23:16:27] [PASSED] 58 VFs
[23:16:27] [PASSED] 59 VFs
[23:16:27] [PASSED] 60 VFs
[23:16:27] [PASSED] 61 VFs
[23:16:27] [PASSED] 62 VFs
[23:16:27] [PASSED] 63 VFs
[23:16:27] ==================== [PASSED] fair_vram ====================
[23:16:27] ================== [PASSED] pf_gt_config ===================
[23:16:27] ===================== lmtt (1 subtest) =====================
[23:16:27] ======================== test_ops  =========================
[23:16:27] [PASSED] 2-level
[23:16:27] [PASSED] multi-level
[23:16:27] ==================== [PASSED] test_ops =====================
[23:16:27] ====================== [PASSED] lmtt =======================
[23:16:27] ================= sriov_packet (1 subtest) =================
[23:16:27] [PASSED] test_descriptor_init
[23:16:27] ================== [PASSED] sriov_packet ===================
[23:16:27] ================= pf_service (11 subtests) =================
[23:16:27] [PASSED] pf_negotiate_any
[23:16:27] [PASSED] pf_negotiate_base_match
[23:16:27] [PASSED] pf_negotiate_base_newer
[23:16:27] [PASSED] pf_negotiate_base_next
[23:16:27] [SKIPPED] pf_negotiate_base_older (no older minor)
[23:16:27] [PASSED] pf_negotiate_base_prev
[23:16:27] [PASSED] pf_negotiate_latest_match
[23:16:27] [PASSED] pf_negotiate_latest_newer
[23:16:27] [PASSED] pf_negotiate_latest_next
[23:16:27] [SKIPPED] pf_negotiate_latest_older (no older minor)
[23:16:27] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[23:16:27] =================== [PASSED] pf_service ====================
[23:16:27] ================= xe_guc_g2g (2 subtests) ==================
[23:16:27] ============== xe_live_guc_g2g_kunit_default  ==============
[23:16:27] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:16:27] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:16:27] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:16:27] =================== [SKIPPED] xe_guc_g2g ===================
[23:16:27] =================== xe_mocs (2 subtests) ===================
[23:16:27] ================ xe_live_mocs_kernel_kunit  ================
[23:16:27] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:16:27] ================ xe_live_mocs_reset_kunit  =================
[23:16:27] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:16:27] ==================== [SKIPPED] xe_mocs =====================
[23:16:27] ================= xe_migrate (3 subtests) ==================
[23:16:27] ================= xe_migrate_sanity_kunit  =================
[23:16:27] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:16:27] ================== xe_validate_ccs_kunit  ==================
[23:16:27] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:16:27] ============= xe_migrate_access_memory_kunit  ==============
[23:16:27] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[23:16:27] =================== [SKIPPED] xe_migrate ===================
[23:16:27] ================== xe_dma_buf (1 subtest) ==================
[23:16:27] ==================== xe_dma_buf_kunit  =====================
[23:16:27] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:16:27] =================== [SKIPPED] xe_dma_buf ===================
[23:16:27] ================= xe_bo_shrink (1 subtest) =================
[23:16:27] =================== xe_bo_shrink_kunit  ====================
[23:16:27] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:16:27] ================== [SKIPPED] xe_bo_shrink ==================
[23:16:27] ==================== xe_bo (2 subtests) ====================
[23:16:27] ================== xe_ccs_migrate_kunit  ===================
[23:16:27] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:16:27] ==================== xe_bo_evict_kunit  ====================
[23:16:27] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:16:27] ===================== [SKIPPED] xe_bo ======================
[23:16:27] =================== xe_any (9 subtests) ====================
[23:16:27] [PASSED] test_to_xe
[23:16:27] [PASSED] test_to_dev
[23:16:27] [PASSED] test_to_pdev
[23:16:27] [PASSED] test_to_drm
[23:16:27] [PASSED] test_if_pdev
[23:16:27] [PASSED] test_if_xe
[23:16:27] [PASSED] test_if_tile
[23:16:27] [PASSED] test_if_gt
[23:16:27] [PASSED] test_to_id
[23:16:27] ===================== [PASSED] xe_any ======================
[23:16:27] ==================== args (13 subtests) ====================
[23:16:27] [PASSED] count_args_test
[23:16:27] [PASSED] call_args_example
[23:16:27] [PASSED] call_args_test
[23:16:27] [PASSED] drop_first_arg_example
[23:16:27] [PASSED] drop_first_arg_test
[23:16:27] [PASSED] first_arg_example
[23:16:27] [PASSED] first_arg_test
[23:16:27] [PASSED] last_arg_example
[23:16:27] [PASSED] last_arg_test
[23:16:27] [PASSED] pick_arg_example
[23:16:27] [PASSED] if_args_example
[23:16:27] [PASSED] if_args_test
[23:16:27] [PASSED] sep_comma_example
[23:16:27] ====================== [PASSED] args =======================
[23:16:27] =================== xe_pci (3 subtests) ====================
[23:16:27] ==================== check_graphics_ip  ====================
[23:16:27] [PASSED] 12.00 Xe_LP
[23:16:27] [PASSED] 12.10 Xe_LP+
[23:16:27] [PASSED] 12.55 Xe_HPG
[23:16:27] [PASSED] 12.60 Xe_HPC
[23:16:27] [PASSED] 12.70 Xe_LPG
[23:16:27] [PASSED] 12.71 Xe_LPG
[23:16:27] [PASSED] 12.74 Xe_LPG+
[23:16:27] [PASSED] 20.01 Xe2_HPG
[23:16:27] [PASSED] 20.02 Xe2_HPG
[23:16:27] [PASSED] 20.04 Xe2_LPG
[23:16:27] [PASSED] 30.00 Xe3_LPG
[23:16:27] [PASSED] 30.01 Xe3_LPG
[23:16:27] [PASSED] 30.03 Xe3_LPG
[23:16:27] [PASSED] 30.04 Xe3_LPG
[23:16:27] [PASSED] 30.05 Xe3_LPG
[23:16:27] [PASSED] 35.10 Xe3p_LPG
[23:16:27] [PASSED] 35.11 Xe3p_XPC
[23:16:27] ================ [PASSED] check_graphics_ip ================
[23:16:27] ===================== check_media_ip  ======================
[23:16:27] [PASSED] 12.00 Xe_M
[23:16:27] [PASSED] 12.55 Xe_HPM
[23:16:27] [PASSED] 13.00 Xe_LPM+
[23:16:27] [PASSED] 13.01 Xe2_HPM
[23:16:27] [PASSED] 20.00 Xe2_LPM
[23:16:27] [PASSED] 30.00 Xe3_LPM
[23:16:27] [PASSED] 30.02 Xe3_LPM
[23:16:27] [PASSED] 35.00 Xe3p_LPM
[23:16:27] [PASSED] 35.03 Xe3p_HPM
[23:16:27] ================= [PASSED] check_media_ip ==================
[23:16:27] =================== check_platform_desc  ===================
[23:16:27] [PASSED] 0x9A60 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A68 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A70 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A40 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A49 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A59 (TIGERLAKE)
[23:16:27] [PASSED] 0x9A78 (TIGERLAKE)
[23:16:27] [PASSED] 0x9AC0 (TIGERLAKE)
[23:16:27] [PASSED] 0x9AC9 (TIGERLAKE)
[23:16:27] [PASSED] 0x9AD9 (TIGERLAKE)
[23:16:27] [PASSED] 0x9AF8 (TIGERLAKE)
[23:16:27] [PASSED] 0x4C80 (ROCKETLAKE)
[23:16:27] [PASSED] 0x4C8A (ROCKETLAKE)
[23:16:27] [PASSED] 0x4C8B (ROCKETLAKE)
[23:16:27] [PASSED] 0x4C8C (ROCKETLAKE)
[23:16:27] [PASSED] 0x4C90 (ROCKETLAKE)
[23:16:27] [PASSED] 0x4C9A (ROCKETLAKE)
[23:16:27] [PASSED] 0x4680 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4682 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4688 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x468A (ALDERLAKE_S)
[23:16:27] [PASSED] 0x468B (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4690 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4692 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4693 (ALDERLAKE_S)
[23:16:27] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46AA (ALDERLAKE_P)
[23:16:27] [PASSED] 0x462A (ALDERLAKE_P)
[23:16:27] [PASSED] 0x4626 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x4628 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:16:27] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:16:27] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:16:27] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:16:27] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:16:27] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:16:27] [PASSED] 0xA721 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA720 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:16:27] [PASSED] 0xA780 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA781 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA782 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA783 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA788 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA789 (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA78A (ALDERLAKE_S)
[23:16:27] [PASSED] 0xA78B (ALDERLAKE_S)
[23:16:27] [PASSED] 0x4905 (DG1)
[23:16:27] [PASSED] 0x4906 (DG1)
[23:16:27] [PASSED] 0x4907 (DG1)
[23:16:27] [PASSED] 0x4908 (DG1)
[23:16:27] [PASSED] 0x4909 (DG1)
[23:16:27] [PASSED] 0x56C0 (DG2)
[23:16:27] [PASSED] 0x56C2 (DG2)
[23:16:27] [PASSED] 0x56C1 (DG2)
[23:16:27] [PASSED] 0x7D51 (METEORLAKE)
[23:16:27] [PASSED] 0x7DD1 (METEORLAKE)
[23:16:27] [PASSED] 0x7D41 (METEORLAKE)
[23:16:27] [PASSED] 0x7D67 (METEORLAKE)
[23:16:27] [PASSED] 0xB640 (METEORLAKE)
[23:16:27] [PASSED] 0x56A0 (DG2)
[23:16:27] [PASSED] 0x56A1 (DG2)
[23:16:27] [PASSED] 0x56A2 (DG2)
[23:16:27] [PASSED] 0x56BE (DG2)
[23:16:27] [PASSED] 0x56BF (DG2)
[23:16:27] [PASSED] 0x5690 (DG2)
[23:16:27] [PASSED] 0x5691 (DG2)
[23:16:27] [PASSED] 0x5692 (DG2)
[23:16:27] [PASSED] 0x56A5 (DG2)
[23:16:27] [PASSED] 0x56A6 (DG2)
[23:16:27] [PASSED] 0x56B0 (DG2)
[23:16:27] [PASSED] 0x56B1 (DG2)
[23:16:27] [PASSED] 0x56BA (DG2)
[23:16:27] [PASSED] 0x56BB (DG2)
[23:16:27] [PASSED] 0x56BC (DG2)
[23:16:27] [PASSED] 0x56BD (DG2)
[23:16:27] [PASSED] 0x5693 (DG2)
[23:16:27] [PASSED] 0x5694 (DG2)
[23:16:27] [PASSED] 0x5695 (DG2)
[23:16:27] [PASSED] 0x56A3 (DG2)
[23:16:27] [PASSED] 0x56A4 (DG2)
[23:16:27] [PASSED] 0x56B2 (DG2)
[23:16:27] [PASSED] 0x56B3 (DG2)
[23:16:27] [PASSED] 0x5696 (DG2)
[23:16:27] [PASSED] 0x5697 (DG2)
[23:16:27] [PASSED] 0xB69 (PVC)
[23:16:27] [PASSED] 0xB6E (PVC)
[23:16:27] [PASSED] 0xBD4 (PVC)
[23:16:27] [PASSED] 0xBD5 (PVC)
[23:16:27] [PASSED] 0xBD6 (PVC)
[23:16:27] [PASSED] 0xBD7 (PVC)
[23:16:27] [PASSED] 0xBD8 (PVC)
[23:16:27] [PASSED] 0xBD9 (PVC)
[23:16:27] [PASSED] 0xBDA (PVC)
[23:16:27] [PASSED] 0xBDB (PVC)
[23:16:27] [PASSED] 0xBE0 (PVC)
[23:16:27] [PASSED] 0xBE1 (PVC)
[23:16:27] [PASSED] 0xBE5 (PVC)
[23:16:27] [PASSED] 0x7D40 (METEORLAKE)
[23:16:27] [PASSED] 0x7D45 (METEORLAKE)
[23:16:27] [PASSED] 0x7D55 (METEORLAKE)
[23:16:27] [PASSED] 0x7D60 (METEORLAKE)
[23:16:27] [PASSED] 0x7DD5 (METEORLAKE)
[23:16:27] [PASSED] 0x6420 (LUNARLAKE)
[23:16:27] [PASSED] 0x64A0 (LUNARLAKE)
[23:16:27] [PASSED] 0x64B0 (LUNARLAKE)
[23:16:27] [PASSED] 0xE202 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE209 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE20B (BATTLEMAGE)
[23:16:27] [PASSED] 0xE20C (BATTLEMAGE)
[23:16:27] [PASSED] 0xE20D (BATTLEMAGE)
[23:16:27] [PASSED] 0xE210 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE211 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE212 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE216 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE220 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE221 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE222 (BATTLEMAGE)
[23:16:27] [PASSED] 0xE223 (BATTLEMAGE)
[23:16:27] [PASSED] 0xB080 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB081 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB082 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB083 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB084 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB085 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB086 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB087 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB08F (PANTHERLAKE)
[23:16:27] [PASSED] 0xB090 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB0A1 (PANTHERLAKE)
[23:16:27] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:16:27] [PASSED] 0xFD80 (PANTHERLAKE)
[23:16:27] [PASSED] 0xFD81 (PANTHERLAKE)
[23:16:27] [PASSED] 0xD740 (NOVALAKE_S)
[23:16:27] [PASSED] 0xD741 (NOVALAKE_S)
[23:16:27] [PASSED] 0xD742 (NOVALAKE_S)
[23:16:27] [PASSED] 0xD743 (NOVALAKE_S)
[23:16:27] [PASSED] 0xD745 (NOVALAKE_S)
[23:16:27] [PASSED] 0xD74A (NOVALAKE_S)
[23:16:27] [PASSED] 0xD74B (NOVALAKE_S)
[23:16:27] [PASSED] 0x674C (CRESCENTISLAND)
[23:16:27] [PASSED] 0x674D (CRESCENTISLAND)
[23:16:27] [PASSED] 0x674E (CRESCENTISLAND)
[23:16:27] [PASSED] 0x674F (CRESCENTISLAND)
[23:16:27] [PASSED] 0x6750 (CRESCENTISLAND)
[23:16:27] [PASSED] 0x6751 (CRESCENTISLAND)
[23:16:27] [PASSED] 0x6752 (CRESCENTISLAND)
[23:16:27] [PASSED] 0xD750 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD751 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD752 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD753 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD754 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD755 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD756 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD757 (NOVALAKE_P)
[23:16:27] [PASSED] 0xD75F (NOVALAKE_P)
[23:16:27] =============== [PASSED] check_platform_desc ===============
[23:16:27] ===================== [PASSED] xe_pci ======================
[23:16:27] ============= xe_rtp_tables_test (5 subtests) ==============
[23:16:27] ================== xe_rtp_table_gt_test  ===================
[23:16:27] [PASSED] gt_was/14011060649
[23:16:27] [PASSED] gt_was/14011059788
[23:16:27] [PASSED] gt_was/14015795083
[23:16:27] [PASSED] gt_was/16021867713
[23:16:27] [PASSED] gt_was/14019449301
[23:16:27] [PASSED] gt_was/16028005424
[23:16:27] [PASSED] gt_was/14026578760
[23:16:27] [PASSED] gt_was/1409420604
[23:16:27] [PASSED] gt_was/1408615072
[23:16:27] [PASSED] gt_was/22010523718
[23:16:27] [PASSED] gt_was/14011006942
[23:16:27] [PASSED] gt_was/14014830051
[23:16:27] [PASSED] gt_was/18018781329
[23:16:27] [PASSED] gt_was/1509235366
[23:16:27] [PASSED] gt_was/18018781329
[23:16:27] [PASSED] gt_was/16016694945
[23:16:27] [PASSED] gt_was/14018575942
[23:16:27] [PASSED] gt_was/22016670082
[23:16:27] [PASSED] gt_was/22016670082
[23:16:27] [PASSED] gt_was/14017421178
[23:16:27] [PASSED] gt_was/16025250150
[23:16:27] [PASSED] gt_was/14021871409
[23:16:27] [PASSED] gt_was/16021865536
[23:16:27] [PASSED] gt_was/14021486841
[23:16:27] [PASSED] gt_was/14025160223
[23:16:27] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[23:16:27] [PASSED] gt_was/14025635424
[23:16:27] [PASSED] gt_was/16028005424
[23:16:27] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:16:27] ================== xe_rtp_table_gt_test  ===================
[23:16:27] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[23:16:27] [PASSED] gt_tunings/Tuning: 32B Access Enable
[23:16:27] [PASSED] gt_tunings/Tuning: L3 cache
[23:16:27] [PASSED] gt_tunings/Tuning: L3 cache - media
[23:16:27] [PASSED] gt_tunings/Tuning: Compression Overfetch
[23:16:27] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[23:16:27] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[23:16:27] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[23:16:27] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[23:16:27] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[23:16:27] [PASSED] gt_tunings/Tuning: Stateless compression control
[23:16:27] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[23:16:27] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[23:16:27] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[23:16:27] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[23:16:27] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[23:16:27] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:16:27] ================== xe_rtp_table_oob_test  ==================
[23:16:27] [PASSED] oob_was/1607983814
[23:16:27] [PASSED] oob_was/16010904313
[23:16:27] [PASSED] oob_was/18022495364
[23:16:27] [PASSED] oob_was/22012773006
[23:16:27] [PASSED] oob_was/14014475959
[23:16:27] [PASSED] oob_was/22011391025
[23:16:27] [PASSED] oob_was/22012727170
[23:16:27] [PASSED] oob_was/22012727685
[23:16:27] [PASSED] oob_was/22016596838
[23:16:27] [PASSED] oob_was/18020744125
[23:16:27] [PASSED] oob_was/1409600907
[23:16:27] [PASSED] oob_was/22014953428
[23:16:27] [PASSED] oob_was/16017236439
[23:16:27] [PASSED] oob_was/14019821291
[23:16:27] [PASSED] oob_was/14015076503
[23:16:27] [PASSED] oob_was/22016122933
[23:16:27] [PASSED] oob_was/14018913170
[23:16:27] [PASSED] oob_was/14018094691
[23:16:27] [PASSED] oob_was/18024947630
[23:16:27] [PASSED] oob_was/16022287689
[23:16:27] [PASSED] oob_was/13011645652
[23:16:27] [PASSED] oob_was/14022293748
[23:16:27] [PASSED] oob_was/22019794406
[23:16:27] [PASSED] oob_was/22019338487
[23:16:27] [PASSED] oob_was/16023588340
[23:16:27] [PASSED] oob_was/14019789679
[23:16:27] [PASSED] oob_was/14022866841
[23:16:27] [PASSED] oob_was/16021333562
[23:16:27] [PASSED] oob_was/14016712196
[23:16:27] [PASSED] oob_was/14015568240
[23:16:27] [PASSED] oob_was/18013179988
[23:16:27] [PASSED] oob_was/1508761755
[23:16:27] [PASSED] oob_was/16023105232
[23:16:27] [PASSED] oob_was/16026508708
[23:16:27] [PASSED] oob_was/14020001231
[23:16:27] [PASSED] oob_was/16023683509
[23:16:27] [PASSED] oob_was/14025515070
[23:16:27] [PASSED] oob_was/15015404425_disable
[23:16:27] [PASSED] oob_was/16026007364
[23:16:27] [PASSED] oob_was/14020316580
[23:16:27] [PASSED] oob_was/14025883347
[23:16:27] [PASSED] oob_was/16029380221
[23:16:27] [PASSED] oob_was/22022079272
[23:16:27] [PASSED] oob_was/16029897822
[23:16:27] [PASSED] oob_was/14026539277
[23:16:27] [PASSED] oob_was/14027054324
[23:16:27] [PASSED] oob_was/14025941587
[23:16:27] [PASSED] oob_was/16030224309
[23:16:27] [PASSED] oob_was/16031259911
[23:16:27] ============== [PASSED] xe_rtp_table_oob_test ==============
[23:16:27] ================ xe_rtp_table_dev_oob_test  ================
[23:16:27] [PASSED] device_oob_was/22010954014
[23:16:27] [PASSED] device_oob_was/15015404425
[23:16:27] [PASSED] device_oob_was/22019338487_display
[23:16:27] [PASSED] device_oob_was/14022085890
[23:16:27] [PASSED] device_oob_was/14026633728
[23:16:27] [PASSED] device_oob_was/14026746987
[23:16:27] [PASSED] device_oob_was/14026779378
[23:16:27] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[23:16:27] ========== xe_rtp_table_missing_upper_bound_test  ==========
[23:16:27] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[23:16:27] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[23:16:27] [PASSED] register_whitelist/1806527549
[23:16:27] [PASSED] register_whitelist/allow_read_ctx_timestamp
[23:16:27] [PASSED] register_whitelist/allow_read_queue_timestamp
[23:16:27] [PASSED] register_whitelist/16014440446
[23:16:27] [PASSED] register_whitelist/16017236439
[23:16:27] [PASSED] register_whitelist/16020183090
[23:16:27] [PASSED] register_whitelist/14024997852
[23:16:27] [PASSED] register_whitelist/14024997852
[23:16:27] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[23:16:27] =============== [PASSED] xe_rtp_tables_test ================
[23:16:27] =================== xe_rtp (3 subtests) ====================
[23:16:27] =================== xe_rtp_rules_tests  ====================
[23:16:27] [PASSED] no
[23:16:27] [PASSED] yes
[23:16:27] [PASSED] no-and-no
[23:16:27] [PASSED] no-and-yes
[23:16:27] [PASSED] yes-and-no
[23:16:27] [PASSED] yes-and-yes
[23:16:27] [PASSED] no-or-no
[23:16:27] [PASSED] no-or-yes
[23:16:27] [PASSED] yes-or-no
[23:16:27] [PASSED] yes-or-yes
[23:16:27] [PASSED] no-yes-or-yes-no
[23:16:27] [PASSED] no-yes-or-yes-yes
[23:16:27] [PASSED] yes-yes-or-no-yes
[23:16:27] [PASSED] yes-yes-or-yes-yes
[23:16:27] [PASSED] no-no-or-yes-or-no
[23:16:27] [PASSED] or
[23:16:27] [PASSED] or-yes
[23:16:27] [PASSED] or-no
[23:16:27] [PASSED] yes-or
[23:16:27] [PASSED] no-or
[23:16:27] [PASSED] no-or-or-yes
[23:16:27] [PASSED] yes-or-or-no
[23:16:27] [PASSED] no-or-or-no
[23:16:27] [PASSED] missing-context-engine-class
[23:16:27] [PASSED] missing-context-engine-class-or-yes
[23:16:27] [PASSED] missing-context-engine-class-or-or-yes
[23:16:27] =============== [PASSED] xe_rtp_rules_tests ================
[23:16:27] =============== xe_rtp_process_to_sr_tests  ================
[23:16:27] [PASSED] coalesce-same-reg
[23:16:27] [PASSED] coalesce-same-reg-literal-and-func
[23:16:27] [PASSED] no-match-no-add
[23:16:27] [PASSED] two-regs-two-entries
[23:16:27] [PASSED] clr-one-set-other
[23:16:27] [PASSED] set-field
[23:16:27] [PASSED] conflict-duplicate
[23:16:27] [PASSED] conflict-not-disjoint
[23:16:27] [PASSED] conflict-not-disjoint-literal-and-func
[23:16:27] [PASSED] conflict-reg-type
[23:16:27] [PASSED] bad-mcr-reg-forced-to-regular
[23:16:27] [PASSED] bad-regular-reg-forced-to-mcr
[23:16:27] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:16:27] ================== xe_rtp_process_tests  ===================
[23:16:27] [PASSED] active1
[23:16:27] [PASSED] active2
[23:16:27] [PASSED] active-inactive
[23:16:27] [PASSED] inactive-active
[23:16:27] [PASSED] inactive-active-inactive
[23:16:27] [PASSED] inactive-inactive-inactive
[23:16:27] ============== [PASSED] xe_rtp_process_tests ===============
[23:16:27] ===================== [PASSED] xe_rtp ======================
[23:16:27] ==================== xe_wa (1 subtest) =====================
[23:16:27] ======================== xe_wa_gt  =========================
[23:16:27] [PASSED] TIGERLAKE B0
[23:16:27] [PASSED] DG1 A0
[23:16:27] [PASSED] DG1 B0
[23:16:27] [PASSED] ALDERLAKE_S A0
[23:16:27] [PASSED] ALDERLAKE_S B0
[23:16:27] [PASSED] ALDERLAKE_S C0
[23:16:27] [PASSED] ALDERLAKE_S D0
[23:16:27] [PASSED] ALDERLAKE_P A0
[23:16:27] [PASSED] ALDERLAKE_P B0
[23:16:27] [PASSED] ALDERLAKE_P C0
[23:16:27] [PASSED] ALDERLAKE_S RPLS D0
[23:16:27] [PASSED] ALDERLAKE_P RPLU E0
[23:16:27] [PASSED] DG2 G10 C0
[23:16:27] [PASSED] DG2 G11 B1
[23:16:27] [PASSED] DG2 G12 A1
[23:16:27] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:16:27] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:16:27] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:16:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:16:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:16:27] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:16:27] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:16:27] ==================== [PASSED] xe_wa_gt =====================
[23:16:27] ====================== [PASSED] xe_wa ======================
[23:16:27] ============================================================
[23:16:27] Testing complete. Ran 840 tests: passed: 811, skipped: 29
[23:16:27] Elapsed time: 41.824s total, 1.852s configuring, 39.206s building, 0.726s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:16:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:16:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:16:54] Starting KUnit Kernel (1/1)...
[23:16:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:16:54] ============ drm_test_pick_cmdline (2 subtests) ============
[23:16:54] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:16:54] =============== drm_test_pick_cmdline_named  ===============
[23:16:54] [PASSED] NTSC
[23:16:54] [PASSED] NTSC-J
[23:16:54] [PASSED] PAL
[23:16:54] [PASSED] PAL-M
[23:16:54] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:16:54] ============== [PASSED] drm_test_pick_cmdline ==============
[23:16:54] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:16:54] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:16:54] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:16:54] =========== drm_validate_clone_mode (2 subtests) ===========
[23:16:54] ============== drm_test_check_in_clone_mode  ===============
[23:16:54] [PASSED] in_clone_mode
[23:16:54] [PASSED] not_in_clone_mode
[23:16:54] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:16:54] =============== drm_test_check_valid_clones  ===============
[23:16:54] [PASSED] not_in_clone_mode
[23:16:54] [PASSED] valid_clone
[23:16:54] [PASSED] invalid_clone
[23:16:54] =========== [PASSED] drm_test_check_valid_clones ===========
[23:16:54] ============= [PASSED] drm_validate_clone_mode =============
[23:16:54] ============= drm_validate_modeset (1 subtest) =============
[23:16:54] [PASSED] drm_test_check_connector_changed_modeset
[23:16:54] ============== [PASSED] drm_validate_modeset ===============
[23:16:54] ====== drm_test_bridge_get_current_state (1 subtest) =======
[23:16:54] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:16:54] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:16:54] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:16:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:16:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:16:54] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[23:16:54] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:16:54] ============== drm_bridge_alloc (2 subtests) ===============
[23:16:54] [PASSED] drm_test_drm_bridge_alloc_basic
[23:16:54] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:16:54] ================ [PASSED] drm_bridge_alloc =================
[23:16:54] ============= drm_bridge_bus_fmt (5 subtests) ==============
[23:16:54] [PASSED] drm_test_bridge_rgb_yuv_rgb
[23:16:54] [PASSED] drm_test_bridge_must_convert_to_yuv444
[23:16:54] [PASSED] drm_test_bridge_hdmi_auto_rgb
[23:16:54] [PASSED] drm_test_bridge_auto_first
[23:16:54] [PASSED] drm_test_bridge_rgb_yuv_no_path
[23:16:54] =============== [PASSED] drm_bridge_bus_fmt ================
[23:16:54] ============= drm_cmdline_parser (40 subtests) =============
[23:16:54] [PASSED] drm_test_cmdline_force_d_only
[23:16:54] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:16:54] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:16:54] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:16:54] [PASSED] drm_test_cmdline_force_e_only
[23:16:54] [PASSED] drm_test_cmdline_res
[23:16:54] [PASSED] drm_test_cmdline_res_vesa
[23:16:54] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:16:54] [PASSED] drm_test_cmdline_res_rblank
[23:16:54] [PASSED] drm_test_cmdline_res_bpp
[23:16:54] [PASSED] drm_test_cmdline_res_refresh
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:16:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:16:54] [PASSED] drm_test_cmdline_res_margins_force_on
[23:16:54] [PASSED] drm_test_cmdline_res_vesa_margins
[23:16:54] [PASSED] drm_test_cmdline_name
[23:16:54] [PASSED] drm_test_cmdline_name_bpp
[23:16:54] [PASSED] drm_test_cmdline_name_option
[23:16:54] [PASSED] drm_test_cmdline_name_bpp_option
[23:16:54] [PASSED] drm_test_cmdline_rotate_0
[23:16:54] [PASSED] drm_test_cmdline_rotate_90
[23:16:54] [PASSED] drm_test_cmdline_rotate_180
[23:16:54] [PASSED] drm_test_cmdline_rotate_270
[23:16:54] [PASSED] drm_test_cmdline_hmirror
[23:16:54] [PASSED] drm_test_cmdline_vmirror
[23:16:54] [PASSED] drm_test_cmdline_margin_options
[23:16:54] [PASSED] drm_test_cmdline_multiple_options
[23:16:54] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:16:54] [PASSED] drm_test_cmdline_extra_and_option
[23:16:54] [PASSED] drm_test_cmdline_freestanding_options
[23:16:54] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:16:54] [PASSED] drm_test_cmdline_panel_orientation
[23:16:54] ================ drm_test_cmdline_invalid  =================
[23:16:54] [PASSED] margin_only
[23:16:54] [PASSED] interlace_only
[23:16:54] [PASSED] res_missing_x
[23:16:54] [PASSED] res_missing_y
[23:16:54] [PASSED] res_bad_y
[23:16:54] [PASSED] res_missing_y_bpp
[23:16:54] [PASSED] res_bad_bpp
[23:16:54] [PASSED] res_bad_refresh
[23:16:54] [PASSED] res_bpp_refresh_force_on_off
[23:16:54] [PASSED] res_invalid_mode
[23:16:54] [PASSED] res_bpp_wrong_place_mode
[23:16:54] [PASSED] name_bpp_refresh
[23:16:54] [PASSED] name_refresh
[23:16:54] [PASSED] name_refresh_wrong_mode
[23:16:54] [PASSED] name_refresh_invalid_mode
[23:16:54] [PASSED] rotate_multiple
[23:16:54] [PASSED] rotate_invalid_val
[23:16:54] [PASSED] rotate_truncated
[23:16:54] [PASSED] invalid_option
[23:16:54] [PASSED] invalid_tv_option
[23:16:54] [PASSED] truncated_tv_option
[23:16:54] ============ [PASSED] drm_test_cmdline_invalid =============
[23:16:54] =============== drm_test_cmdline_tv_options  ===============
[23:16:54] [PASSED] NTSC
[23:16:54] [PASSED] NTSC_443
[23:16:54] [PASSED] NTSC_J
[23:16:54] [PASSED] PAL
[23:16:54] [PASSED] PAL_M
[23:16:54] [PASSED] PAL_N
[23:16:54] [PASSED] SECAM
[23:16:54] [PASSED] MONO_525
[23:16:54] [PASSED] MONO_625
[23:16:54] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:16:54] =============== [PASSED] drm_cmdline_parser ================
[23:16:54] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:16:54] [PASSED] drm_test_connector_hdmi_init_valid
[23:16:54] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:16:54] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:16:54] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:16:54] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:16:54] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:16:54] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:16:54] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:16:54] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:16:54] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:16:54] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:16:54] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:16:54] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:16:54] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:16:54] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:16:54] [PASSED] drm_test_connector_hdmi_init_null_product
[23:16:54] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:16:54] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:16:54] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:16:54] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:16:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:16:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:16:54] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:16:54] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:16:54] [PASSED] HDMI-A
[23:16:54] [PASSED] HDMI-B
[23:16:54] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:16:54] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:16:54] [PASSED] Unknown
[23:16:54] [PASSED] VGA
[23:16:54] [PASSED] DVI-I
[23:16:54] [PASSED] DVI-D
[23:16:54] [PASSED] DVI-A
[23:16:54] [PASSED] Composite
[23:16:54] [PASSED] SVIDEO
[23:16:54] [PASSED] LVDS
[23:16:54] [PASSED] Component
[23:16:54] [PASSED] DIN
[23:16:54] [PASSED] DP
[23:16:54] [PASSED] TV
[23:16:54] [PASSED] eDP
[23:16:54] [PASSED] Virtual
[23:16:54] [PASSED] DSI
[23:16:54] [PASSED] DPI
[23:16:54] [PASSED] Writeback
[23:16:54] [PASSED] SPI
[23:16:54] [PASSED] USB
[23:16:54] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:16:54] ============ [PASSED] drmm_connector_hdmi_init =============
[23:16:54] ============= drmm_connector_init (3 subtests) =============
[23:16:54] [PASSED] drm_test_drmm_connector_init
[23:16:54] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:16:54] ========= drm_test_drmm_connector_init_type_valid  =========
[23:16:54] [PASSED] Unknown
[23:16:54] [PASSED] VGA
[23:16:54] [PASSED] DVI-I
[23:16:54] [PASSED] DVI-D
[23:16:54] [PASSED] DVI-A
[23:16:54] [PASSED] Composite
[23:16:54] [PASSED] SVIDEO
[23:16:54] [PASSED] LVDS
[23:16:54] [PASSED] Component
[23:16:54] [PASSED] DIN
[23:16:54] [PASSED] DP
[23:16:54] [PASSED] HDMI-A
[23:16:54] [PASSED] HDMI-B
[23:16:54] [PASSED] TV
[23:16:54] [PASSED] eDP
[23:16:54] [PASSED] Virtual
[23:16:54] [PASSED] DSI
[23:16:54] [PASSED] DPI
[23:16:54] [PASSED] Writeback
[23:16:54] [PASSED] SPI
[23:16:54] [PASSED] USB
[23:16:54] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:16:54] =============== [PASSED] drmm_connector_init ===============
[23:16:54] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_init
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:16:54] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:16:54] [PASSED] Unknown
[23:16:54] [PASSED] VGA
[23:16:54] [PASSED] DVI-I
[23:16:54] [PASSED] DVI-D
[23:16:54] [PASSED] DVI-A
[23:16:54] [PASSED] Composite
[23:16:54] [PASSED] SVIDEO
[23:16:54] [PASSED] LVDS
[23:16:54] [PASSED] Component
[23:16:54] [PASSED] DIN
[23:16:54] [PASSED] DP
[23:16:54] [PASSED] HDMI-A
[23:16:54] [PASSED] HDMI-B
[23:16:54] [PASSED] TV
[23:16:54] [PASSED] eDP
[23:16:54] [PASSED] Virtual
[23:16:54] [PASSED] DSI
[23:16:54] [PASSED] DPI
[23:16:54] [PASSED] Writeback
[23:16:54] [PASSED] SPI
[23:16:54] [PASSED] USB
[23:16:54] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:16:54] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:16:54] [PASSED] Unknown
[23:16:54] [PASSED] VGA
[23:16:54] [PASSED] DVI-I
[23:16:54] [PASSED] DVI-D
[23:16:54] [PASSED] DVI-A
[23:16:54] [PASSED] Composite
[23:16:54] [PASSED] SVIDEO
[23:16:54] [PASSED] LVDS
[23:16:54] [PASSED] Component
[23:16:54] [PASSED] DIN
[23:16:54] [PASSED] DP
[23:16:54] [PASSED] HDMI-A
[23:16:54] [PASSED] HDMI-B
[23:16:54] [PASSED] TV
[23:16:54] [PASSED] eDP
[23:16:54] [PASSED] Virtual
[23:16:54] [PASSED] DSI
[23:16:54] [PASSED] DPI
[23:16:54] [PASSED] Writeback
[23:16:54] [PASSED] SPI
[23:16:54] [PASSED] USB
[23:16:54] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:16:54] =========== [PASSED] drm_connector_dynamic_init ============
[23:16:54] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:16:54] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:16:54] ======= drm_connector_dynamic_register (7 subtests) ========
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:16:54] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:16:54] ========= [PASSED] drm_connector_dynamic_register ==========
[23:16:54] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:16:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:16:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:16:54] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:16:54] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:16:54] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:16:54] [PASSED] NTSC
[23:16:54] [PASSED] NTSC-443
[23:16:54] [PASSED] NTSC-J
[23:16:54] [PASSED] PAL
[23:16:54] [PASSED] PAL-M
[23:16:54] [PASSED] PAL-N
[23:16:54] [PASSED] SECAM
[23:16:54] [PASSED] Mono
[23:16:54] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:16:54] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:16:54] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:16:54] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:16:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:16:54] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:16:54] [PASSED] VIC 96
[23:16:54] [PASSED] VIC 97
[23:16:54] [PASSED] VIC 101
[23:16:54] [PASSED] VIC 102
[23:16:54] [PASSED] VIC 106
[23:16:54] [PASSED] VIC 107
[23:16:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:16:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:16:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:16:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:16:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:16:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:16:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:16:54] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:16:54] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:16:54] [PASSED] Automatic
[23:16:54] [PASSED] Full
[23:16:54] [PASSED] Limited 16:235
[23:16:54] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:16:54] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:16:54] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:16:54] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:16:54] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:16:54] [PASSED] RGB
[23:16:54] [PASSED] YUV 4:2:0
[23:16:54] [PASSED] YUV 4:2:2
[23:16:54] [PASSED] YUV 4:4:4
[23:16:54] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:16:54] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:16:54] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:16:54] ============= drm_damage_helper (21 subtests) ==============
[23:16:54] [PASSED] drm_test_damage_iter_no_damage
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:16:54] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:16:54] [PASSED] drm_test_damage_iter_simple_damage
[23:16:54] [PASSED] drm_test_damage_iter_single_damage
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:16:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:16:54] [PASSED] drm_test_damage_iter_damage
[23:16:54] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:16:54] [PASSED] drm_test_damage_iter_damage_one_outside
[23:16:54] [PASSED] drm_test_damage_iter_damage_src_moved
[23:16:54] [PASSED] drm_test_damage_iter_damage_not_visible
[23:16:54] ================ [PASSED] drm_damage_helper ================
[23:16:54] ============== drm_dp_mst_helper (3 subtests) ==============
[23:16:54] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:16:54] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:16:54] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:16:54] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:16:54] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:16:54] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:16:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:16:54] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:16:54] [PASSED] Link rate 2000000 lane count 4
[23:16:54] [PASSED] Link rate 2000000 lane count 2
[23:16:54] [PASSED] Link rate 2000000 lane count 1
[23:16:54] [PASSED] Link rate 1350000 lane count 4
[23:16:54] [PASSED] Link rate 1350000 lane count 2
[23:16:54] [PASSED] Link rate 1350000 lane count 1
[23:16:54] [PASSED] Link rate 1000000 lane count 4
[23:16:54] [PASSED] Link rate 1000000 lane count 2
[23:16:54] [PASSED] Link rate 1000000 lane count 1
[23:16:54] [PASSED] Link rate 810000 lane count 4
[23:16:54] [PASSED] Link rate 810000 lane count 2
[23:16:54] [PASSED] Link rate 810000 lane count 1
[23:16:54] [PASSED] Link rate 540000 lane count 4
[23:16:54] [PASSED] Link rate 540000 lane count 2
[23:16:54] [PASSED] Link rate 540000 lane count 1
[23:16:54] [PASSED] Link rate 270000 lane count 4
[23:16:54] [PASSED] Link rate 270000 lane count 2
[23:16:54] [PASSED] Link rate 270000 lane count 1
[23:16:54] [PASSED] Link rate 162000 lane count 4
[23:16:54] [PASSED] Link rate 162000 lane count 2
[23:16:54] [PASSED] Link rate 162000 lane count 1
[23:16:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:16:54] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:16:54] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:16:54] [PASSED] DP_POWER_UP_PHY with port number
[23:16:54] [PASSED] DP_POWER_DOWN_PHY with port number
[23:16:54] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:16:54] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:16:54] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:16:54] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:16:54] [PASSED] DP_QUERY_PAYLOAD with port number
[23:16:54] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:16:54] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:16:54] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:16:54] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:16:54] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:16:54] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:16:54] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:16:54] [PASSED] DP_REMOTE_I2C_READ with port number
[23:16:54] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:16:54] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:16:54] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:16:54] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:16:54] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:16:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:16:54] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:16:54] ================ [PASSED] drm_dp_mst_helper ================
[23:16:54] ================== drm_exec (7 subtests) ===================
[23:16:54] [PASSED] sanitycheck
[23:16:54] [PASSED] test_lock
[23:16:54] [PASSED] test_lock_unlock
[23:16:54] [PASSED] test_duplicates
[23:16:54] [PASSED] test_prepare
[23:16:54] [PASSED] test_prepare_array
[23:16:54] [PASSED] test_multiple_loops
[23:16:54] ==================== [PASSED] drm_exec =====================
[23:16:54] =========== drm_format_helper_test (17 subtests) ===========
[23:16:54] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:16:54] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:16:54] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:16:54] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:16:54] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:16:54] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:16:54] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:16:54] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:16:54] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:16:54] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:16:54] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:16:54] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:16:54] ==================== drm_test_fb_swab  =====================
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ================ [PASSED] drm_test_fb_swab =================
[23:16:54] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:16:54] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:16:54] [PASSED] single_pixel_source_buffer
[23:16:54] [PASSED] single_pixel_clip_rectangle
[23:16:54] [PASSED] well_known_colors
[23:16:54] [PASSED] destination_pitch
[23:16:54] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:16:54] ================= drm_test_fb_clip_offset  =================
[23:16:54] [PASSED] pass through
[23:16:54] [PASSED] horizontal offset
[23:16:54] [PASSED] vertical offset
[23:16:54] [PASSED] horizontal and vertical offset
[23:16:54] [PASSED] horizontal offset (custom pitch)
[23:16:54] [PASSED] vertical offset (custom pitch)
[23:16:54] [PASSED] horizontal and vertical offset (custom pitch)
[23:16:54] ============= [PASSED] drm_test_fb_clip_offset =============
[23:16:54] =================== drm_test_fb_memcpy  ====================
[23:16:54] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:16:54] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:16:54] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:16:54] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:16:54] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:16:54] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:16:54] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:16:54] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:16:54] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:16:54] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:16:54] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:16:54] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:16:54] =============== [PASSED] drm_test_fb_memcpy ================
[23:16:54] ============= [PASSED] drm_format_helper_test ==============
[23:16:54] ================= drm_format (18 subtests) =================
[23:16:54] [PASSED] drm_test_format_block_width_invalid
[23:16:54] [PASSED] drm_test_format_block_width_one_plane
[23:16:54] [PASSED] drm_test_format_block_width_two_plane
[23:16:54] [PASSED] drm_test_format_block_width_three_plane
[23:16:54] [PASSED] drm_test_format_block_width_tiled
[23:16:54] [PASSED] drm_test_format_block_height_invalid
[23:16:54] [PASSED] drm_test_format_block_height_one_plane
[23:16:54] [PASSED] drm_test_format_block_height_two_plane
[23:16:54] [PASSED] drm_test_format_block_height_three_plane
[23:16:54] [PASSED] drm_test_format_block_height_tiled
[23:16:54] [PASSED] drm_test_format_min_pitch_invalid
[23:16:54] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:16:54] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:16:54] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:16:54] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:16:54] [PASSED] drm_test_format_min_pitch_two_plane
[23:16:54] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:16:54] [PASSED] drm_test_format_min_pitch_tiled
[23:16:54] =================== [PASSED] drm_format ====================
[23:16:54] ============== drm_framebuffer (10 subtests) ===============
[23:16:54] ========== drm_test_framebuffer_check_src_coords  ==========
[23:16:54] [PASSED] Success: source fits into fb
[23:16:54] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:16:54] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:16:54] [PASSED] Fail: overflowing fb with source width
[23:16:54] [PASSED] Fail: overflowing fb with source height
[23:16:54] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:16:54] [PASSED] drm_test_framebuffer_cleanup
[23:16:54] =============== drm_test_framebuffer_create  ===============
[23:16:54] [PASSED] ABGR8888 normal sizes
[23:16:54] [PASSED] ABGR8888 max sizes
[23:16:54] [PASSED] ABGR8888 pitch greater than min required
[23:16:54] [PASSED] ABGR8888 pitch less than min required
[23:16:54] [PASSED] ABGR8888 Invalid width
[23:16:54] [PASSED] ABGR8888 Invalid buffer handle
[23:16:54] [PASSED] No pixel format
[23:16:54] [PASSED] ABGR8888 Width 0
[23:16:54] [PASSED] ABGR8888 Height 0
[23:16:54] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:16:54] [PASSED] ABGR8888 Large buffer offset
[23:16:54] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:16:54] [PASSED] ABGR8888 Invalid flag
[23:16:54] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:16:54] [PASSED] ABGR8888 Valid buffer modifier
[23:16:54] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:16:54] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] NV12 Normal sizes
[23:16:54] [PASSED] NV12 Max sizes
[23:16:54] [PASSED] NV12 Invalid pitch
[23:16:54] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:16:54] [PASSED] NV12 different  modifier per-plane
[23:16:54] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:16:54] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] NV12 Modifier for inexistent plane
[23:16:54] [PASSED] NV12 Handle for inexistent plane
[23:16:54] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:16:54] [PASSED] YVU420 Normal sizes
[23:16:54] [PASSED] YVU420 Max sizes
[23:16:54] [PASSED] YVU420 Invalid pitch
[23:16:54] [PASSED] YVU420 Different pitches
[23:16:54] [PASSED] YVU420 Different buffer offsets/pitches
[23:16:54] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:16:54] [PASSED] YVU420 Valid modifier
[23:16:54] [PASSED] YVU420 Different modifiers per plane
[23:16:54] [PASSED] YVU420 Modifier for inexistent plane
[23:16:54] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:16:54] [PASSED] X0L2 Normal sizes
[23:16:54] [PASSED] X0L2 Max sizes
[23:16:54] [PASSED] X0L2 Invalid pitch
[23:16:54] [PASSED] X0L2 Pitch greater than minimum required
[23:16:54] [PASSED] X0L2 Handle for inexistent plane
[23:16:54] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:16:54] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:16:54] [PASSED] X0L2 Valid modifier
[23:16:54] [PASSED] X0L2 Modifier for inexistent plane
[23:16:54] =========== [PASSED] drm_test_framebuffer_create ===========
[23:16:54] [PASSED] drm_test_framebuffer_free
[23:16:54] [PASSED] drm_test_framebuffer_init
[23:16:54] [PASSED] drm_test_framebuffer_init_bad_format
[23:16:54] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:16:54] [PASSED] drm_test_framebuffer_lookup
[23:16:54] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:16:54] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:16:54] ================= [PASSED] drm_framebuffer =================
[23:16:54] ================ drm_gem_shmem (8 subtests) ================
[23:16:54] [PASSED] drm_gem_shmem_test_obj_create
[23:16:54] [PASSED] drm_gem_shmem_test_obj_create_private
[23:16:54] [PASSED] drm_gem_shmem_test_pin_pages
[23:16:54] [PASSED] drm_gem_shmem_test_vmap
[23:16:54] [PASSED] drm_gem_shmem_test_get_sg_table
[23:16:54] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:16:54] [PASSED] drm_gem_shmem_test_madvise
[23:16:54] [PASSED] drm_gem_shmem_test_purge
[23:16:54] ================== [PASSED] drm_gem_shmem ==================
[23:16:54] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:16:54] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:16:54] [PASSED] Automatic
[23:16:54] [PASSED] Full
[23:16:54] [PASSED] Limited 16:235
[23:16:54] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:16:54] [PASSED] drm_test_check_disable_connector
[23:16:54] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:16:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:16:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:16:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:16:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:16:54] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:16:54] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:16:54] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:16:54] [PASSED] drm_test_check_output_bpc_dvi
[23:16:54] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:16:54] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:16:54] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:16:54] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:16:54] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:16:54] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:16:54] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:16:54] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:16:54] ============ drm_test_check_hdmi_color_format  =============
[23:16:54] [PASSED] AUTO -> RGB
[23:16:54] [PASSED] YCBCR422 -> YUV422
[23:16:54] [PASSED] YCBCR420 -> YUV420
[23:16:54] [PASSED] YCBCR444 -> YUV444
[23:16:54] [PASSED] RGB -> RGB
[23:16:54] ======== [PASSED] drm_test_check_hdmi_color_format =========
[23:16:54] ======== drm_test_check_hdmi_color_format_420_only  ========
[23:16:54] [PASSED] RGB should fail
[23:16:54] [PASSED] YUV444 should fail
[23:16:54] [PASSED] YUV422 should fail
[23:16:54] [PASSED] YUV420 should work
[23:16:54] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[23:16:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:16:54] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:16:54] [PASSED] drm_test_check_broadcast_rgb_value
[23:16:54] [PASSED] drm_test_check_bpc_8_value
[23:16:54] [PASSED] drm_test_check_bpc_10_value
[23:16:54] [PASSED] drm_test_check_bpc_12_value
[23:16:54] [PASSED] drm_test_check_format_value
[23:16:54] [PASSED] drm_test_check_tmds_char_value
[23:16:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:16:54] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[23:16:54] [PASSED] drm_test_check_mode_valid
[23:16:54] [PASSED] drm_test_check_mode_valid_reject
[23:16:54] [PASSED] drm_test_check_mode_valid_reject_rate
[23:16:54] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:16:54] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[23:16:54] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[23:16:54] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[23:16:54] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:16:54] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:16:54] [PASSED] drm_test_check_infoframes
[23:16:54] [PASSED] drm_test_check_reject_avi_infoframe
[23:16:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:16:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:16:54] [PASSED] drm_test_check_reject_audio_infoframe
[23:16:54] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:16:54] ================= drm_managed (2 subtests) =================
[23:16:54] [PASSED] drm_test_managed_release_action
[23:16:54] [PASSED] drm_test_managed_run_action
[23:16:54] =================== [PASSED] drm_managed ===================
[23:16:54] =================== drm_mm (6 subtests) ====================
[23:16:54] [PASSED] drm_test_mm_init
[23:16:54] [PASSED] drm_test_mm_debug
[23:16:54] [PASSED] drm_test_mm_align32
[23:16:54] [PASSED] drm_test_mm_align64
[23:16:54] [PASSED] drm_test_mm_lowest
[23:16:54] [PASSED] drm_test_mm_highest
[23:16:54] ===================== [PASSED] drm_mm ======================
[23:16:54] ============= drm_modes_analog_tv (5 subtests) =============
[23:16:54] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:16:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:16:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:16:54] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:16:54] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:16:54] =============== [PASSED] drm_modes_analog_tv ===============
[23:16:54] ============== drm_panic_helper (3 subtests) ===============
[23:16:54] ============= drm_test_panic_screen_user_map  ==============
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] ========= [PASSED] drm_test_panic_screen_user_map ==========
[23:16:54] ============= drm_test_panic_screen_user_page  =============
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] ========= [PASSED] drm_test_panic_screen_user_page =========
[23:16:54] ========== drm_test_panic_screen_user_set_pixel  ===========
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[23:16:54] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[23:16:54] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[23:16:54] ================ [PASSED] drm_panic_helper =================
[23:16:54] ============== drm_plane_helper (2 subtests) ===============
[23:16:54] =============== drm_test_check_plane_state  ================
[23:16:54] [PASSED] clipping_simple
[23:16:54] [PASSED] clipping_rotate_reflect
[23:16:54] [PASSED] positioning_simple
[23:16:54] [PASSED] upscaling
[23:16:54] [PASSED] downscaling
[23:16:54] [PASSED] rounding1
[23:16:54] [PASSED] rounding2
[23:16:54] [PASSED] rounding3
[23:16:54] [PASSED] rounding4
[23:16:54] =========== [PASSED] drm_test_check_plane_state ============
[23:16:54] =========== drm_test_check_invalid_plane_state  ============
[23:16:54] [PASSED] positioning_invalid
[23:16:54] [PASSED] upscaling_invalid
[23:16:54] [PASSED] downscaling_invalid
[23:16:54] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:16:54] ================ [PASSED] drm_plane_helper =================
[23:16:54] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:16:54] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:16:54] [PASSED] None
[23:16:54] [PASSED] PAL
[23:16:54] [PASSED] NTSC
[23:16:54] [PASSED] Both, NTSC Default
[23:16:54] [PASSED] Both, PAL Default
[23:16:54] [PASSED] Both, NTSC Default, with PAL on command-line
[23:16:54] [PASSED] Both, PAL Default, with NTSC on command-line
[23:16:54] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:16:54] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:16:54] ================== drm_rect (9 subtests) ===================
[23:16:54] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:16:54] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:16:54] [PASSED] drm_test_rect_clip_scaled_clipped
[23:16:54] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:16:54] ================= drm_test_rect_intersect  =================
[23:16:54] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:16:54] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:16:54] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:16:54] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:16:54] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:16:54] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:16:54] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:16:54] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:16:54] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:16:54] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:16:54] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:16:54] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:16:54] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:16:54] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:16:54] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:16:54] ============= [PASSED] drm_test_rect_intersect =============
[23:16:54] ================ drm_test_rect_calc_hscale  ================
[23:16:54] [PASSED] normal use
[23:16:54] [PASSED] out of max range
[23:16:54] [PASSED] out of min range
[23:16:54] [PASSED] zero dst
[23:16:54] [PASSED] negative src
[23:16:54] [PASSED] negative dst
[23:16:54] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:16:54] ================ drm_test_rect_calc_vscale  ================
[23:16:54] [PASSED] normal use
[23:16:54] [PASSED] out of max range
[23:16:54] [PASSED] out of min range
[23:16:54] [PASSED] zero dst
[23:16:54] [PASSED] negative src
[23:16:54] [PASSED] negative dst
[23:16:54] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:16:54] ================== drm_test_rect_rotate  ===================
[23:16:54] [PASSED] reflect-x
[23:16:54] [PASSED] reflect-y
[23:16:54] [PASSED] rotate-0
[23:16:54] [PASSED] rotate-90
[23:16:54] [PASSED] rotate-180
[23:16:54] [PASSED] rotate-270
[23:16:54] ============== [PASSED] drm_test_rect_rotate ===============
[23:16:54] ================ drm_test_rect_rotate_inv  =================
[23:16:54] [PASSED] reflect-x
[23:16:54] [PASSED] reflect-y
[23:16:54] [PASSED] rotate-0
[23:16:54] [PASSED] rotate-90
[23:16:54] [PASSED] rotate-180
[23:16:54] [PASSED] rotate-270
[23:16:54] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:16:54] ==================== [PASSED] drm_rect =====================
[23:16:54] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:16:54] ============ drm_test_sysfb_build_fourcc_list  =============
[23:16:54] [PASSED] no native formats
[23:16:54] [PASSED] XRGB8888 as native format
[23:16:54] [PASSED] remove duplicates
[23:16:54] [PASSED] convert alpha formats
[23:16:54] [PASSED] random formats
[23:16:54] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:16:54] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:16:54] ================== drm_fixp (2 subtests) ===================
[23:16:54] [PASSED] drm_test_int2fixp
[23:16:54] [PASSED] drm_test_sm2fixp
[23:16:54] ==================== [PASSED] drm_fixp =====================
[23:16:54] ============================================================
[23:16:54] Testing complete. Ran 667 tests: passed: 667
[23:16:54] Elapsed time: 27.252s total, 1.827s configuring, 25.009s building, 0.411s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:16:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:16:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:17:06] Starting KUnit Kernel (1/1)...
[23:17:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:17:06] ================= ttm_device (5 subtests) ==================
[23:17:06] [PASSED] ttm_device_init_basic
[23:17:06] [PASSED] ttm_device_init_multiple
[23:17:06] [PASSED] ttm_device_fini_basic
[23:17:06] [PASSED] ttm_device_init_no_vma_man
[23:17:06] ================== ttm_device_init_pools  ==================
[23:17:06] [PASSED] No DMA allocations, no DMA32 required
[23:17:06] [PASSED] DMA allocations, DMA32 required
[23:17:06] [PASSED] No DMA allocations, DMA32 required
[23:17:06] [PASSED] DMA allocations, no DMA32 required
[23:17:06] ============== [PASSED] ttm_device_init_pools ==============
[23:17:06] =================== [PASSED] ttm_device ====================
[23:17:06] ================== ttm_pool (8 subtests) ===================
[23:17:06] ================== ttm_pool_alloc_basic  ===================
[23:17:06] [PASSED] One page
[23:17:06] [PASSED] More than one page
[23:17:06] [PASSED] Above the allocation limit
[23:17:06] [PASSED] One page, with coherent DMA mappings enabled
[23:17:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:17:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:17:06] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:17:06] [PASSED] One page
[23:17:06] [PASSED] More than one page
[23:17:06] [PASSED] Above the allocation limit
[23:17:06] [PASSED] One page, with coherent DMA mappings enabled
[23:17:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:17:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:17:06] [PASSED] ttm_pool_alloc_order_caching_match
[23:17:06] [PASSED] ttm_pool_alloc_caching_mismatch
[23:17:06] [PASSED] ttm_pool_alloc_order_mismatch
[23:17:06] [PASSED] ttm_pool_free_dma_alloc
[23:17:06] [PASSED] ttm_pool_free_no_dma_alloc
[23:17:06] [PASSED] ttm_pool_fini_basic
[23:17:06] ==================== [PASSED] ttm_pool =====================
[23:17:06] ================ ttm_resource (8 subtests) =================
[23:17:06] ================= ttm_resource_init_basic  =================
[23:17:06] [PASSED] Init resource in TTM_PL_SYSTEM
[23:17:06] [PASSED] Init resource in TTM_PL_VRAM
[23:17:06] [PASSED] Init resource in a private placement
[23:17:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:17:06] ============= [PASSED] ttm_resource_init_basic =============
[23:17:06] [PASSED] ttm_resource_init_pinned
[23:17:06] [PASSED] ttm_resource_fini_basic
[23:17:06] [PASSED] ttm_resource_manager_init_basic
[23:17:06] [PASSED] ttm_resource_manager_usage_basic
[23:17:06] [PASSED] ttm_resource_manager_set_used_basic
[23:17:06] [PASSED] ttm_sys_man_alloc_basic
[23:17:06] [PASSED] ttm_sys_man_free_basic
[23:17:06] ================== [PASSED] ttm_resource ===================
[23:17:06] =================== ttm_tt (15 subtests) ===================
[23:17:06] ==================== ttm_tt_init_basic  ====================
[23:17:06] [PASSED] Page-aligned size
[23:17:06] [PASSED] Extra pages requested
[23:17:06] ================ [PASSED] ttm_tt_init_basic ================
[23:17:06] [PASSED] ttm_tt_init_misaligned
[23:17:06] [PASSED] ttm_tt_fini_basic
[23:17:06] [PASSED] ttm_tt_fini_sg
[23:17:06] [PASSED] ttm_tt_fini_shmem
[23:17:06] [PASSED] ttm_tt_create_basic
[23:17:06] [PASSED] ttm_tt_create_invalid_bo_type
[23:17:06] [PASSED] ttm_tt_create_ttm_exists
[23:17:06] [PASSED] ttm_tt_create_failed
[23:17:06] [PASSED] ttm_tt_destroy_basic
[23:17:06] [PASSED] ttm_tt_populate_null_ttm
[23:17:06] [PASSED] ttm_tt_populate_populated_ttm
[23:17:06] [PASSED] ttm_tt_unpopulate_basic
[23:17:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:17:06] [PASSED] ttm_tt_swapin_basic
[23:17:06] ===================== [PASSED] ttm_tt ======================
[23:17:06] =================== ttm_bo (14 subtests) ===================
[23:17:06] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:17:06] [PASSED] Cannot be interrupted and sleeps
[23:17:06] [PASSED] Cannot be interrupted, locks straight away
[23:17:06] [PASSED] Can be interrupted, sleeps
[23:17:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:17:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:17:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:17:06] [PASSED] ttm_bo_reserve_double_resv
[23:17:06] [PASSED] ttm_bo_reserve_interrupted
[23:17:06] [PASSED] ttm_bo_reserve_deadlock
[23:17:06] [PASSED] ttm_bo_unreserve_basic
[23:17:06] [PASSED] ttm_bo_unreserve_pinned
[23:17:06] [PASSED] ttm_bo_unreserve_bulk
[23:17:06] [PASSED] ttm_bo_fini_basic
[23:17:06] [PASSED] ttm_bo_fini_shared_resv
[23:17:06] [PASSED] ttm_bo_pin_basic
[23:17:06] [PASSED] ttm_bo_pin_unpin_resource
[23:17:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:17:06] ===================== [PASSED] ttm_bo ======================
[23:17:06] ============== ttm_bo_validate (22 subtests) ===============
[23:17:06] ============== ttm_bo_init_reserved_sys_man  ===============
[23:17:06] [PASSED] Buffer object for userspace
[23:17:06] [PASSED] Kernel buffer object
[23:17:06] [PASSED] Shared buffer object
[23:17:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:17:06] ============== ttm_bo_init_reserved_mock_man  ==============
[23:17:06] [PASSED] Buffer object for userspace
[23:17:06] [PASSED] Kernel buffer object
[23:17:06] [PASSED] Shared buffer object
[23:17:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:17:06] [PASSED] ttm_bo_init_reserved_resv
[23:17:06] ================== ttm_bo_validate_basic  ==================
[23:17:06] [PASSED] Buffer object for userspace
[23:17:06] [PASSED] Kernel buffer object
[23:17:06] [PASSED] Shared buffer object
[23:17:06] ============== [PASSED] ttm_bo_validate_basic ==============
[23:17:06] [PASSED] ttm_bo_validate_invalid_placement
[23:17:06] ============= ttm_bo_validate_same_placement  ==============
[23:17:06] [PASSED] System manager
[23:17:06] [PASSED] VRAM manager
[23:17:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:17:06] [PASSED] ttm_bo_validate_failed_alloc
[23:17:06] [PASSED] ttm_bo_validate_pinned
[23:17:06] [PASSED] ttm_bo_validate_busy_placement
[23:17:06] ================ ttm_bo_validate_multihop  =================
[23:17:06] [PASSED] Buffer object for userspace
[23:17:06] [PASSED] Kernel buffer object
[23:17:06] [PASSED] Shared buffer object
[23:17:06] ============ [PASSED] ttm_bo_validate_multihop =============
[23:17:06] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:17:06] [PASSED] Buffer object in system domain, no page vector
[23:17:06] [PASSED] Buffer object in system domain with an existing page vector
[23:17:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:17:06] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:17:06] [PASSED] Buffer object for userspace
[23:17:06] [PASSED] Kernel buffer object
[23:17:06] [PASSED] Shared buffer object
[23:17:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:17:06] [PASSED] ttm_bo_validate_move_fence_signaled
[23:17:06] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:17:06] [PASSED] Waits for GPU
[23:17:06] [PASSED] Tries to lock straight away
[23:17:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:17:06] [PASSED] ttm_bo_validate_swapout
[23:17:06] [PASSED] ttm_bo_validate_happy_evict
[23:17:06] [PASSED] ttm_bo_validate_all_pinned_evict
[23:17:06] [PASSED] ttm_bo_validate_allowed_only_evict
[23:17:06] [PASSED] ttm_bo_validate_deleted_evict
[23:17:06] [PASSED] ttm_bo_validate_busy_domain_evict
[23:17:06] [PASSED] ttm_bo_validate_evict_gutting
[23:17:06] [PASSED] ttm_bo_validate_recrusive_evict
[23:17:06] ================= [PASSED] ttm_bo_validate =================
[23:17:06] ============================================================
[23:17:06] Testing complete. Ran 102 tests: passed: 102
[23:17:06] Elapsed time: 12.248s total, 1.855s configuring, 10.127s building, 0.213s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[23:17:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:17:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:17:17] Starting KUnit Kernel (1/1)...
[23:17:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:17:17] =============== dma-buf-fence (12 subtests) ================
[23:17:17] [PASSED] test_sanitycheck
[23:17:17] [PASSED] test_signaling
[23:17:17] [PASSED] test_add_callback
[23:17:17] [PASSED] test_late_add_callback
[23:17:17] [PASSED] test_rm_callback
[23:17:17] [PASSED] test_late_rm_callback
[23:17:17] [PASSED] test_status
[23:17:17] [PASSED] test_error
[23:17:17] [PASSED] test_wait
[23:17:17] [PASSED] test_wait_timeout
[23:17:17] [PASSED] test_stub
[23:17:17] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[23:17:17] ================== [PASSED] dma-buf-fence ==================
[23:17:17] ============ dma-buf-fence-chain (11 subtests) =============
[23:17:17] [PASSED] test_sanitycheck
[23:17:17] [PASSED] test_find_seqno
[23:17:17] [PASSED] test_find_signaled
[23:17:17] [PASSED] test_find_out_of_order
[23:17:22] [PASSED] test_find_gap
[23:17:22] [PASSED] test_find_race
[23:17:22] [PASSED] test_signal_forward
[23:17:22] [PASSED] test_signal_backward
[23:17:22] [PASSED] test_wait_forward
[23:17:22] [PASSED] test_wait_backward
[23:17:22] [PASSED] test_wait_random
[23:17:22] =============== [PASSED] dma-buf-fence-chain ===============
[23:17:22] ============ dma-buf-fence-unwrap (11 subtests) ============
[23:17:22] [PASSED] test_sanitycheck
[23:17:22] [PASSED] test_unwrap_array
[23:17:22] [PASSED] test_unwrap_chain
[23:17:22] [PASSED] test_unwrap_chain_array
[23:17:22] [PASSED] test_unwrap_merge
[23:17:22] [PASSED] test_unwrap_merge_duplicate
[23:17:22] [PASSED] test_unwrap_merge_seqno
[23:17:22] [PASSED] test_unwrap_merge_order
[23:17:22] [PASSED] test_unwrap_merge_complex
[23:17:22] [PASSED] test_unwrap_merge_complex_seqno
[23:17:22] [PASSED] test_dedup_empty
[23:17:22] ============== [PASSED] dma-buf-fence-unwrap ===============
[23:17:22] ================ dma-buf-resv (5 subtests) =================
[23:17:22] [PASSED] test_sanitycheck
[23:17:22] ===================== test_signaling  ======================
[23:17:22] [PASSED] kernel
[23:17:22] [PASSED] write
[23:17:22] [PASSED] read
[23:17:22] [PASSED] bookkeep
[23:17:22] ================= [PASSED] test_signaling ==================
[23:17:22] ====================== test_for_each  ======================
[23:17:22] [PASSED] kernel
[23:17:22] [PASSED] write
[23:17:22] [PASSED] read
[23:17:22] [PASSED] bookkeep
[23:17:22] ================== [PASSED] test_for_each ==================
[23:17:22] ================= test_for_each_unlocked  ==================
[23:17:22] [PASSED] kernel
[23:17:22] [PASSED] write
[23:17:22] [PASSED] read
[23:17:22] [PASSED] bookkeep
[23:17:22] ============= [PASSED] test_for_each_unlocked ==============
[23:17:22] ===================== test_get_fences  =====================
[23:17:22] [PASSED] kernel
[23:17:22] [PASSED] write
[23:17:22] [PASSED] read
[23:17:22] [PASSED] bookkeep
[23:17:22] ================= [PASSED] test_get_fences =================
[23:17:22] ================== [PASSED] dma-buf-resv ===================
[23:17:22] ============================================================
[23:17:22] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[23:17:22] Elapsed time: 15.861s total, 1.841s configuring, 8.749s building, 5.255s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1456 bytes --]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)
URL   : https://patchwork.freedesktop.org/series/176761/
State : success

== Summary ==

CI Bug Log - changes from xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6_BAT -> xe-pw-176761v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-176761v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [ABORT][1] ([Intel XE#9463]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463


Build changes
-------------

  * Linux: xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6 -> xe-pw-176761v2

  IGT_9173: 9173
  xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6: 238c1e3e984e2b7f948cb24165314b8d719a23d6
  xe-pw-176761v2: 176761v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/index.html

[-- Attachment #2: Type: text/html, Size: 2021 bytes --]

✓ Xe.CI.FULL: success for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 24335 bytes --]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911 (rev2)
URL   : https://patchwork.freedesktop.org/series/176761/
State : success

== Summary ==

CI Bug Log - changes from xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6_FULL -> xe-pw-176761v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-176761v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-ptl:          NOTRUN -> [SKIP][1] ([Intel XE#5901])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-180:
    - shard-ptl:          NOTRUN -> [SKIP][2] ([Intel XE#5808]) +4 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          [PASS][3] -> [SKIP][4] ([Intel XE#367])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-10/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-ptl:          NOTRUN -> [SKIP][5] ([Intel XE#367])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2:
    - shard-bmg:          [PASS][6] -> [INCOMPLETE][7] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2652]) +7 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][9] ([Intel XE#5822]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-ptl:          NOTRUN -> [SKIP][10] ([Intel XE#5824])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
    - shard-ptl:          NOTRUN -> [SKIP][11] ([Intel XE#2252]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-ptl:          NOTRUN -> [SKIP][12] ([Intel XE#6507])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@suspend-resume:
    - shard-ptl:          NOTRUN -> [SKIP][13] ([Intel XE#7642])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-ptl:          NOTRUN -> [SKIP][14] ([Intel XE#5900]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_dp_link_training@non-uhbr-sst-direct-train:
    - shard-ptl:          NOTRUN -> [SKIP][15] ([Intel XE#9534])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_dp_link_training@non-uhbr-sst-direct-train.html

  * igt@kms_dsc@dsc-with-bpc-ultrajoiner:
    - shard-ptl:          NOTRUN -> [SKIP][16] ([Intel XE#5907])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_dsc@dsc-with-bpc-ultrajoiner.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][17] ([Intel XE#2316]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-ptl:          [PASS][18] -> [FAIL][19] ([Intel XE#3098]) +1 other test fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-ptl-8/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-ptl:          NOTRUN -> [SKIP][20] ([Intel XE#7178])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-ptl:          NOTRUN -> [SKIP][21] ([Intel XE#7179])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#5812]) +20 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][23] ([Intel XE#5800] / [Intel XE#6312]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-stridechange:
    - shard-ptl:          NOTRUN -> [SKIP][24] ([Intel XE#6312]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-stridechange.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][25] ([Intel XE#7865]) +6 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][26] ([Intel XE#7061] / [Intel XE#7356])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-mmap-wc.html

  * igt@kms_hdr@static-toggle:
    - shard-ptl:          NOTRUN -> [SKIP][27] ([Intel XE#5917] / [Intel XE#6174])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_hdr@static-toggle.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping:
    - shard-ptl:          NOTRUN -> [SKIP][28] ([Intel XE#7283])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-ptl:          NOTRUN -> [SKIP][29] ([Intel XE#4596] / [Intel XE#5854])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c:
    - shard-ptl:          NOTRUN -> [SKIP][30] ([Intel XE#6886]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#1131])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-ptl:          NOTRUN -> [SKIP][32] ([Intel XE#7304])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-primary-page-flip@edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][33] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_psr@fbc-psr2-primary-page-flip@edp-1.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-ptl:          NOTRUN -> [SKIP][34] ([Intel XE#5813])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@xe_evict@evict-large:
    - shard-ptl:          NOTRUN -> [SKIP][35] ([Intel XE#5764]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_evict@evict-large.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd:
    - shard-ptl:          NOTRUN -> [SKIP][36] ([Intel XE#6144])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd.html

  * igt@xe_exec_balancer@no-exec-parallel-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][37] ([Intel XE#7482]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_exec_balancer@no-exec-parallel-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][38] ([Intel XE#5575] / [Intel XE#7484])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][39] ([Intel XE#8374]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic-smem:
    - shard-ptl:          NOTRUN -> [SKIP][40] ([Intel XE#8364]) +7 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic-smem.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-ptl:          [PASS][41] -> [FAIL][42] ([Intel XE#7850])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-ptl-4/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-2/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#8378]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_exec_threads@threads-multi-queue-fd-userptr-rebind.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-ptl:          NOTRUN -> [SKIP][44] ([Intel XE#5100] / [Intel XE#7408])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - shard-ptl:          NOTRUN -> [SKIP][45] ([Intel XE#6964]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  * igt@xe_pm@d3hot-i2c:
    - shard-ptl:          NOTRUN -> [SKIP][46] ([Intel XE#5742] / [Intel XE#7400])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-ptl:          [PASS][47] -> [ABORT][48] ([Intel XE#9362])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-ptl-6/igt@xe_pm@s2idle-vm-bind-userptr.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-4/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pm@s4-basic-exec:
    - shard-lnl:          [PASS][49] -> [ABORT][50] ([Intel XE#9362])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-lnl-7/igt@xe_pm@s4-basic-exec.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-lnl-7/igt@xe_pm@s4-basic-exec.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][51] -> [DMESG-WARN][52] ([Intel XE#7727])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-lnl-2/igt@xe_pm@s4-mocs.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-lnl-5/igt@xe_pm@s4-mocs.html

  * igt@xe_pm_residency@gt-c6-freeze@gt1:
    - shard-bmg:          [PASS][53] -> [FAIL][54] ([Intel XE#9254])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-1/igt@xe_pm_residency@gt-c6-freeze@gt1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-7/igt@xe_pm_residency@gt-c6-freeze@gt1.html

  * igt@xe_query@multigpu-query-config:
    - shard-ptl:          NOTRUN -> [SKIP][55] ([Intel XE#6019]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_query@multigpu-query-config.html

  
#### Possible fixes ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [FAIL][56] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          [FAIL][58] ([Intel XE#1231]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-lnl-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-lnl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][60] ([Intel XE#301]) -> [PASS][61] +1 other test pass
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][62] ([Intel XE#1503]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-2/igt@kms_hdr@invalid-hdr.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-lnl:          [FAIL][64] ([Intel XE#7850]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-lnl-2/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-lnl-8/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_pm@s4-mocs:
    - shard-ptl:          [DMESG-WARN][66] ([Intel XE#7727]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-ptl-1/igt@xe_pm@s4-mocs.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_pm@s4-mocs.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-ptl:          [ABORT][68] ([Intel XE#9362]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-ptl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-ptl-7/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-bmg:          [FAIL][70] ([Intel XE#9254]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-1/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-7/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [DMESG-WARN][72] ([Intel XE#9365]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-6/igt@xe_survivability@runtime-survivability.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-6/igt@xe_survivability@runtime-survivability.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][74] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][75] ([Intel XE#1729] / [Intel XE#7424])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][76] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][77] ([Intel XE#2426] / [Intel XE#5848])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7727
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#9254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9254
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
  [Intel XE#9534]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9534


Build changes
-------------

  * Linux: xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6 -> xe-pw-176761v2

  IGT_9173: 9173
  xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6: 238c1e3e984e2b7f948cb24165314b8d719a23d6
  xe-pw-176761v2: 176761v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v2/index.html

[-- Attachment #2: Type: text/html, Size: 26744 bytes --]

Re: [PATCH v2 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[Vivekanandan, Balasubramani]

On 30.10.2026 19:57, Gustavo Sousa wrote:
> The function adjust_idledly() currently does the following adjustments
> to the IDLEDLY register:
> 
> - Wa_14025941587 defines a minimum value for the idle delay.
> 
> - Wa_16023105232 defines a maximum value for the idle delay and also
>   unsets INHIBIT_SWITCH_UNTIL_PREEMPTED.
> 
> We have an upcoming workaround that will also define a minimum idle
> delay.
> 
> Let's reorganize the logic in adjust_idledly() in a way to make it
> easier to reason about and also easier to extend.
> 
> Do that by having the workaround-specific logic only responsible for
> defining min_idledly_ps or max_idledly_ps, and then keeping the logic of
> how to apply them to the register field (with the right rounding up or
> down) separate.
> 
> This separation drops the helper function idledly_floor_ticks(), the
> clamped_below_maxcnt variable, and the extra quantization check,
> arguably making the code easier to follow.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 100 ++++++++++++++++----------------------
>  1 file changed, 41 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index eb99284af3cc..01a7baf061eb 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -596,99 +596,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  	xe_reg_whitelist_process_engine(hwe);
>  }
>  
> -static u32 idledly_floor_ticks(u64 idledly_ps, u64 idledly_units_ps)
> -{
> -	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
> -}
> -
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
> -	u32 idledly_reg_val, maxcnt_reg_val;
> +	u32 idledly_reg_val;
> +	u32 idledly;
>  	u64 idledly_units_ps = 8 * gt->info.timestamp_base;
> -	u64 maxcnt_units_ps = 640000;
>  	u64 idledly_ps, idledly_hw_ps;
> -	u64 maxcnt_ps;
> +	u64 min_idledly_ps = 0;
> +	u64 max_idledly_ps = -1;
>  	bool inhibit_switch = false;
>  	bool wa_applied = false;
> -	bool clamped_below_maxcnt = false;
>  
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>  		return;
>  
>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		u32 mincnt_idledly_ps = 5000000;
> -
>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>  		if (!idledly_units_ps)
>  			return;
>  
>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +		idledly_ps = idledly * idledly_units_ps;
>  		idledly_hw_ps = idledly_ps;
>  
> -		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> -		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
> -
> -		/*
> -		 * Wa_14025941587 is applied before Wa_16023105232, which takes
> -		 * priority if the two ever conflict (not expected in practice).
> -		 */
> -		if (XE_GT_WA(gt, 14025941587) &&
> -		    idledly_ps < mincnt_idledly_ps) {
> -			idledly_ps = mincnt_idledly_ps;
> -			wa_applied = true;
> -		}
> +		if (XE_GT_WA(gt, 14025941587))
> +			min_idledly_ps = max(min_idledly_ps, 5000000);

There is no need of check, we can directly assign 5000000.

+ Tilak

Regards,
Bala

>  
>  		if (XE_GT_WA(gt, 16023105232)) {
> +			u64 maxcnt_units_ps = 640000;
> +			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +
> +			max_idledly_ps = min_t(u64,
> +					       max_idledly_ps,
> +					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> +
>  			/* Clear the inhibit switch without disturbing a valid delay. */
>  			if (inhibit_switch) {
>  				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>  				wa_applied = true;
>  			}
> +		}
>  
> -			/* Warn only on the value read from hardware. */
> -			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
> +		/*
> +		 * min_idledly_ps is applied before max_idledly_ps, which takes
> +		 * priority if the two ever conflict (not expected in practice).
> +		 */
> +		if (idledly_ps < min_idledly_ps) {
> +			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> +			idledly_ps = idledly * idledly_units_ps;
> +			wa_applied = true;
> +		}
>  
> -			if (idledly_ps >= maxcnt_ps) {
> -				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
> -				clamped_below_maxcnt = true;
> -				wa_applied = true;
> +		if (idledly_ps >= max_idledly_ps) {
> +			if (max_idledly_ps) {
> +				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
> +				idledly_ps = idledly * idledly_units_ps;
> +			} else {
> +				idledly = 0;
> +				idledly_ps = 0;
>  			}
> +
> +			wa_applied = true;
>  		}
>  
> -		if (wa_applied) {
> -			u32 idledly_ticks;
> -
> -			/*
> -			 * Wa_16023105232 requires idledly < maxcnt, so floor
> -			 * that clamp; otherwise round up to guarantee the
> -			 * Wa_14025941587 minimum survives tick quantization.
> -			 */
> -			if (clamped_below_maxcnt)
> -				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
> -			else
> -				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
> -
> -			/*
> -			 * Tick quantization can still push the rounded-up value
> -			 * to/above maxcnt; re-floor here so Wa_16023105232 keeps
> -			 * priority even in that case.
> -			 */
> -			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
> -			    idledly_ticks * idledly_units_ps >= maxcnt_ps) {
> -				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
> -					  hwe->name, idledly_ticks, maxcnt_ps);
> -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
> -				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
> -			}
> +		/* Warn only if the value read from *hardware* exceeds the maximum. */
> +		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
>  
> +		if (wa_applied) {
>  			idledly_reg_val &= ~IDLE_DELAY;
> -			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
> -			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
> -				  hwe->name, idledly_ps, maxcnt_ps,
> +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
> +
> +			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
> +				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
>  				  !!inhibit_switch, gt->info.timestamp_base);
>  			xe_mmio_write32(&gt->mmio,
>  					RING_IDLEDLY(hwe->mmio_base),
> 
> -- 
> 2.56.0
> 

Re: [PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Vivekanandan, Balasubramani]

On 30.10.2026 19:57, Gustavo Sousa wrote:
> Re-organize adjust_idledly() so that we return and avoid touching the
> hardware if no applicable workaround was found.
> 
> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
>  1 file changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 01a7baf061eb..32d33c70e7f4 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	u64 idledly_ps, idledly_hw_ps;
>  	u64 min_idledly_ps = 0;
>  	u64 max_idledly_ps = -1;
> -	bool inhibit_switch = false;
> +	bool clear_inhibit_switch = false;
>  	bool wa_applied = false;
>  
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
> @@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  		if (!idledly_units_ps)
>  			return;
>  
> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> -		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> -		idledly_ps = idledly * idledly_units_ps;
> -		idledly_hw_ps = idledly_ps;
> -
>  		if (XE_GT_WA(gt, 14025941587))
>  			min_idledly_ps = max(min_idledly_ps, 5000000);
>  
> @@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  					       max_idledly_ps,
>  					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>  
> -			/* Clear the inhibit switch without disturbing a valid delay. */
> -			if (inhibit_switch) {
> -				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -				wa_applied = true;
> -			}
> +			clear_inhibit_switch = true;
>  		}
>  
> +		/* No applicable workaround found. */
> +		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> +			return;

We can skip the check for "max_idledly_ps == -1".

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

> +
> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> +
> +		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> +			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +			wa_applied = true;
> +		}
> +
> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +		idledly_ps = idledly * idledly_units_ps;
> +		idledly_hw_ps = idledly_ps;
> +
>  		/*
>  		 * min_idledly_ps is applied before max_idledly_ps, which takes
>  		 * priority if the two ever conflict (not expected in practice).
> @@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  
>  			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
>  				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
> -				  !!inhibit_switch, gt->info.timestamp_base);
> +				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
> +				  gt->info.timestamp_base);
>  			xe_mmio_write32(&gt->mmio,
>  					RING_IDLEDLY(hwe->mmio_base),
>  					idledly_reg_val);
> 
> -- 
> 2.56.0
> 

Re: [PATCH v2 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly()

[Vivekanandan, Balasubramani]

On 30.10.2026 19:57, Gustavo Sousa wrote:
> With the latest change, adjust_idledly() now only touches hardware
> when necessary and has workaround-specific logic well scoped into
> individual "if" statements.  The early workaround checks are now
> redundant and can be dropped.  Do that.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 108 +++++++++++++++++++-------------------
>  1 file changed, 53 insertions(+), 55 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 32d33c70e7f4..08bd8754ad09 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -611,77 +611,75 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>  		return;
>  
> -	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> -		if (!idledly_units_ps)
> -			return;
> +	/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> +	if (!idledly_units_ps)
> +		return;
>  
> -		if (XE_GT_WA(gt, 14025941587))
> -			min_idledly_ps = max(min_idledly_ps, 5000000);
> +	if (XE_GT_WA(gt, 14025941587))
> +		min_idledly_ps = max(min_idledly_ps, 5000000);
>  
> -		if (XE_GT_WA(gt, 16023105232)) {
> -			u64 maxcnt_units_ps = 640000;
> -			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +	if (XE_GT_WA(gt, 16023105232)) {
> +		u64 maxcnt_units_ps = 640000;
> +		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>  
> -			max_idledly_ps = min_t(u64,
> -					       max_idledly_ps,
> -					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> +		max_idledly_ps = min_t(u64,
> +				       max_idledly_ps,
> +				       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>  
> -			clear_inhibit_switch = true;
> -		}
> +		clear_inhibit_switch = true;
> +	}
>  
> -		/* No applicable workaround found. */
> -		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> -			return;
> +	/* No applicable workaround found. */
> +	if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> +		return;
>  
> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> +	idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>  
> -		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> -			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -			wa_applied = true;
> -		}
> +	if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> +		idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		wa_applied = true;
> +	}
> +
> +	idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +	idledly_ps = idledly * idledly_units_ps;
> +	idledly_hw_ps = idledly_ps;
>  
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +	/*
> +	 * min_idledly_ps is applied before max_idledly_ps, which takes
> +	 * priority if the two ever conflict (not expected in practice).
> +	 */
> +	if (idledly_ps < min_idledly_ps) {
> +		idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
>  		idledly_ps = idledly * idledly_units_ps;
> -		idledly_hw_ps = idledly_ps;
> +		wa_applied = true;
> +	}
>  
> -		/*
> -		 * min_idledly_ps is applied before max_idledly_ps, which takes
> -		 * priority if the two ever conflict (not expected in practice).
> -		 */
> -		if (idledly_ps < min_idledly_ps) {
> -			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> +	if (idledly_ps >= max_idledly_ps) {
> +		if (max_idledly_ps) {
> +			idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
>  			idledly_ps = idledly * idledly_units_ps;
> -			wa_applied = true;
> +		} else {
> +			idledly = 0;
> +			idledly_ps = 0;
>  		}
>  
> -		if (idledly_ps >= max_idledly_ps) {
> -			if (max_idledly_ps) {
> -				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
> -				idledly_ps = idledly * idledly_units_ps;
> -			} else {
> -				idledly = 0;
> -				idledly_ps = 0;
> -			}
> -
> -			wa_applied = true;
> -		}
> +		wa_applied = true;
> +	}
>  
> -		/* Warn only if the value read from *hardware* exceeds the maximum. */
> -		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
> +	/* Warn only if the value read from *hardware* exceeds the maximum. */
> +	xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
>  
> -		if (wa_applied) {
> -			idledly_reg_val &= ~IDLE_DELAY;
> -			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
> +	if (wa_applied) {
> +		idledly_reg_val &= ~IDLE_DELAY;
> +		idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
>  
> -			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
> -				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
> -				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
> -				  gt->info.timestamp_base);
> -			xe_mmio_write32(&gt->mmio,
> -					RING_IDLEDLY(hwe->mmio_base),
> -					idledly_reg_val);
> -		}
> +		xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
> +			  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
> +			  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
> +			  gt->info.timestamp_base);
> +		xe_mmio_write32(&gt->mmio,
> +				RING_IDLEDLY(hwe->mmio_base),
> +				idledly_reg_val);
>  	}
>  }
>  
> 
> -- 
> 2.56.0
> 

Re: [PATCH v2 07/10] drm/xe: Replace MAXCNT comment with a comment on adjust_idledly()

[Matt Atwood]

On Fri, Oct 30, 2026 at 07:57:46PM -0300, Gustavo Sousa wrote:
> The adjust_idledly() function does more than what the comment on the
> call site says.  Drop that outdated comment and document
> adjust_idledly() at its definition instead.
> 
> v2:
>   - Add a comment above adjust_idledly() instead of just dropping the
>     call-site comment. (Matt)
> 
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 08bd8754ad09..7950e118ee1d 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -596,6 +596,9 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  	xe_reg_whitelist_process_engine(hwe);
>  }
>  
> +/*
> + * Apply workarounds that require adjustments to RING_IDLEDLY.
> + */
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
> @@ -719,7 +722,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  			xe_hw_engine_enable_ring(hwe);
>  	}
>  
> -	/* Ensure IDLEDLY is lower than MAXCNT */
>  	adjust_idledly(hwe);
>  
>  	return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);
> 
> -- 
> 2.56.0
> 

Re: [PATCH v2 03/10] drm/xe: Use picosecond as common unit in adjust_idledly()

[Matt Atwood]

On Fri, Oct 30, 2026 at 07:57:42PM -0300, Gustavo Sousa wrote:
> Because gt->info.timestamp_base is given in picoseconds, we lose
> precision when calculating the current idle delay in nanoseconds.
> Let's avoid that by using picosecond as the common unit of time in
> adjust_idledly().
> 
> A good side effect of this is that we avoid issuing some integer
> divisions.
> 
> v2:
>   - Change idledly_units_ps and maxcnt_units_ps to u64 to avoid 32-bit
>     multiplication overflow. (Sashiko, Matt)
> 
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 55 +++++++++++++++++++--------------------
>  1 file changed, 27 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 50e8c5103bdc..eb99284af3cc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -596,17 +596,19 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  	xe_reg_whitelist_process_engine(hwe);
>  }
>  
> -static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps)
> +static u32 idledly_floor_ticks(u64 idledly_ps, u64 idledly_units_ps)
>  {
> -	return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps);
> +	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
>  }
>  
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
> -	u32 idledly, idledly_hw, idledly_reg_val, maxcnt;
> -	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
> -	u32 maxcnt_units_ns = 640;
> +	u32 idledly_reg_val, maxcnt_reg_val;
> +	u64 idledly_units_ps = 8 * gt->info.timestamp_base;
> +	u64 maxcnt_units_ps = 640000;
> +	u64 idledly_ps, idledly_hw_ps;
> +	u64 maxcnt_ps;
>  	bool inhibit_switch = false;
>  	bool wa_applied = false;
>  	bool clamped_below_maxcnt = false;
> @@ -615,29 +617,27 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  		return;
>  
>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		u32 mincnt_idledly_ns = 5000;
> +		u32 mincnt_idledly_ps = 5000000;
>  
>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>  		if (!idledly_units_ps)
>  			return;
>  
>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> -		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> -
>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> -		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
> -		idledly_hw = idledly;
> -		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
> -		maxcnt *= maxcnt_units_ns;
> +		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
> +		idledly_hw_ps = idledly_ps;
> +
> +		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
>  
>  		/*
>  		 * Wa_14025941587 is applied before Wa_16023105232, which takes
>  		 * priority if the two ever conflict (not expected in practice).
>  		 */
>  		if (XE_GT_WA(gt, 14025941587) &&
> -		    idledly < mincnt_idledly_ns) {
> -			idledly = mincnt_idledly_ns;
> +		    idledly_ps < mincnt_idledly_ps) {
> +			idledly_ps = mincnt_idledly_ps;
>  			wa_applied = true;
>  		}
>  
> @@ -649,11 +649,11 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  			}
>  
>  			/* Warn only on the value read from hardware. */
> -			xe_gt_WARN_ON(gt, idledly_hw >= maxcnt);
> +			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
>  
> -			if (idledly >= maxcnt) {
> +			if (idledly_ps >= maxcnt_ps) {
>  				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> -				idledly = maxcnt ? maxcnt - 1 : 0;
> +				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
>  				clamped_below_maxcnt = true;
>  				wa_applied = true;
>  			}
> @@ -668,10 +668,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  			 * Wa_14025941587 minimum survives tick quantization.
>  			 */
>  			if (clamped_below_maxcnt)
> -				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
> +				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
>  			else
> -				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
> -								 idledly_units_ps);
> +				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
>  
>  			/*
>  			 * Tick quantization can still push the rounded-up value
> @@ -679,17 +678,17 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  			 * priority even in that case.
>  			 */
>  			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
> -			    (u64)idledly_ticks * idledly_units_ps >= (u64)maxcnt * 1000) {
> -				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%u, so flooring\n",
> -					  hwe->name, idledly_ticks, maxcnt);
> -				idledly = maxcnt ? maxcnt - 1 : 0;
> -				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
> +			    idledly_ticks * idledly_units_ps >= maxcnt_ps) {
> +				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
> +					  hwe->name, idledly_ticks, maxcnt_ps);
> +				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
> +				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
>  			}
>  
>  			idledly_reg_val &= ~IDLE_DELAY;
>  			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
> -			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
> -				  hwe->name, idledly, maxcnt,
> +			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
> +				  hwe->name, idledly_ps, maxcnt_ps,
>  				  !!inhibit_switch, gt->info.timestamp_base);
>  			xe_mmio_write32(&gt->mmio,
>  					RING_IDLEDLY(hwe->mmio_base),
> 
> -- 
> 2.56.0
> 

Re: [PATCH v2 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[Gustavo Sousa]

"Vivekanandan, Balasubramani" <balasubramani.vivekanandan@intel.com>
writes:

> On 30.10.2026 19:57, Gustavo Sousa wrote:
>> The function adjust_idledly() currently does the following adjustments
>> to the IDLEDLY register:
>> 
>> - Wa_14025941587 defines a minimum value for the idle delay.
>> 
>> - Wa_16023105232 defines a maximum value for the idle delay and also
>>   unsets INHIBIT_SWITCH_UNTIL_PREEMPTED.
>> 
>> We have an upcoming workaround that will also define a minimum idle
>> delay.
>> 
>> Let's reorganize the logic in adjust_idledly() in a way to make it
>> easier to reason about and also easier to extend.
>> 
>> Do that by having the workaround-specific logic only responsible for
>> defining min_idledly_ps or max_idledly_ps, and then keeping the logic of
>> how to apply them to the register field (with the right rounding up or
>> down) separate.
>> 
>> This separation drops the helper function idledly_floor_ticks(), the
>> clamped_below_maxcnt variable, and the extra quantization check,
>> arguably making the code easier to follow.
>> 
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_hw_engine.c | 100 ++++++++++++++++----------------------
>>  1 file changed, 41 insertions(+), 59 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index eb99284af3cc..01a7baf061eb 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -596,99 +596,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>>  	xe_reg_whitelist_process_engine(hwe);
>>  }
>>  
>> -static u32 idledly_floor_ticks(u64 idledly_ps, u64 idledly_units_ps)
>> -{
>> -	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
>> -}
>> -
>>  static void adjust_idledly(struct xe_hw_engine *hwe)
>>  {
>>  	struct xe_gt *gt = hwe->gt;
>> -	u32 idledly_reg_val, maxcnt_reg_val;
>> +	u32 idledly_reg_val;
>> +	u32 idledly;
>>  	u64 idledly_units_ps = 8 * gt->info.timestamp_base;
>> -	u64 maxcnt_units_ps = 640000;
>>  	u64 idledly_ps, idledly_hw_ps;
>> -	u64 maxcnt_ps;
>> +	u64 min_idledly_ps = 0;
>> +	u64 max_idledly_ps = -1;
>>  	bool inhibit_switch = false;
>>  	bool wa_applied = false;
>> -	bool clamped_below_maxcnt = false;
>>  
>>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>>  		return;
>>  
>>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
>> -		u32 mincnt_idledly_ps = 5000000;
>> -
>>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>>  		if (!idledly_units_ps)
>>  			return;
>>  
>>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
>> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> +		idledly_ps = idledly * idledly_units_ps;
>>  		idledly_hw_ps = idledly_ps;
>>  
>> -		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>> -		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
>> -
>> -		/*
>> -		 * Wa_14025941587 is applied before Wa_16023105232, which takes
>> -		 * priority if the two ever conflict (not expected in practice).
>> -		 */
>> -		if (XE_GT_WA(gt, 14025941587) &&
>> -		    idledly_ps < mincnt_idledly_ps) {
>> -			idledly_ps = mincnt_idledly_ps;
>> -			wa_applied = true;
>> -		}
>> +		if (XE_GT_WA(gt, 14025941587))
>> +			min_idledly_ps = max(min_idledly_ps, 5000000);
>
> There is no need of check, we can directly assign 5000000.

You are right, but still I would prefer this approach as a standard way
of setting min_idledly_ps.  It makes it easier to add new minimum values
before or after this "if" statement.  This also makes it easy to
move/drop this statement in the future if needed.

--
Gustavo Sousa

>
> + Tilak
>
> Regards,
> Bala
>
>>  
>>  		if (XE_GT_WA(gt, 16023105232)) {
>> +			u64 maxcnt_units_ps = 640000;
>> +			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>> +
>> +			max_idledly_ps = min_t(u64,
>> +					       max_idledly_ps,
>> +					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>> +
>>  			/* Clear the inhibit switch without disturbing a valid delay. */
>>  			if (inhibit_switch) {
>>  				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>>  				wa_applied = true;
>>  			}
>> +		}
>>  
>> -			/* Warn only on the value read from hardware. */
>> -			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
>> +		/*
>> +		 * min_idledly_ps is applied before max_idledly_ps, which takes
>> +		 * priority if the two ever conflict (not expected in practice).
>> +		 */
>> +		if (idledly_ps < min_idledly_ps) {
>> +			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
>> +			idledly_ps = idledly * idledly_units_ps;
>> +			wa_applied = true;
>> +		}
>>  
>> -			if (idledly_ps >= maxcnt_ps) {
>> -				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
>> -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
>> -				clamped_below_maxcnt = true;
>> -				wa_applied = true;
>> +		if (idledly_ps >= max_idledly_ps) {
>> +			if (max_idledly_ps) {
>> +				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
>> +				idledly_ps = idledly * idledly_units_ps;
>> +			} else {
>> +				idledly = 0;
>> +				idledly_ps = 0;
>>  			}
>> +
>> +			wa_applied = true;
>>  		}
>>  
>> -		if (wa_applied) {
>> -			u32 idledly_ticks;
>> -
>> -			/*
>> -			 * Wa_16023105232 requires idledly < maxcnt, so floor
>> -			 * that clamp; otherwise round up to guarantee the
>> -			 * Wa_14025941587 minimum survives tick quantization.
>> -			 */
>> -			if (clamped_below_maxcnt)
>> -				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
>> -			else
>> -				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
>> -
>> -			/*
>> -			 * Tick quantization can still push the rounded-up value
>> -			 * to/above maxcnt; re-floor here so Wa_16023105232 keeps
>> -			 * priority even in that case.
>> -			 */
>> -			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
>> -			    idledly_ticks * idledly_units_ps >= maxcnt_ps) {
>> -				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
>> -					  hwe->name, idledly_ticks, maxcnt_ps);
>> -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
>> -				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
>> -			}
>> +		/* Warn only if the value read from *hardware* exceeds the maximum. */
>> +		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
>>  
>> +		if (wa_applied) {
>>  			idledly_reg_val &= ~IDLE_DELAY;
>> -			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
>> -			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
>> -				  hwe->name, idledly_ps, maxcnt_ps,
>> +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
>> +
>> +			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
>> +				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
>>  				  !!inhibit_switch, gt->info.timestamp_base);
>>  			xe_mmio_write32(&gt->mmio,
>>  					RING_IDLEDLY(hwe->mmio_base),
>> 
>> -- 
>> 2.56.0
>> 

Re: [PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Gustavo Sousa]

"Vivekanandan, Balasubramani" <balasubramani.vivekanandan@intel.com>
writes:

> On 30.10.2026 19:57, Gustavo Sousa wrote:
>> Re-organize adjust_idledly() so that we return and avoid touching the
>> hardware if no applicable workaround was found.
>> 
>> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
>>  1 file changed, 19 insertions(+), 13 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 01a7baf061eb..32d33c70e7f4 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  	u64 idledly_ps, idledly_hw_ps;
>>  	u64 min_idledly_ps = 0;
>>  	u64 max_idledly_ps = -1;
>> -	bool inhibit_switch = false;
>> +	bool clear_inhibit_switch = false;
>>  	bool wa_applied = false;
>>  
>>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>> @@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  		if (!idledly_units_ps)
>>  			return;
>>  
>> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>> -		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> -		idledly_ps = idledly * idledly_units_ps;
>> -		idledly_hw_ps = idledly_ps;
>> -
>>  		if (XE_GT_WA(gt, 14025941587))
>>  			min_idledly_ps = max(min_idledly_ps, 5000000);
>>  
>> @@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  					       max_idledly_ps,
>>  					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>>  
>> -			/* Clear the inhibit switch without disturbing a valid delay. */
>> -			if (inhibit_switch) {
>> -				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -				wa_applied = true;
>> -			}
>> +			clear_inhibit_switch = true;
>>  		}
>>  
>> +		/* No applicable workaround found. */
>> +		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
>> +			return;
>
> We can skip the check for "max_idledly_ps == -1".

You say that because of the "!clear_inhibit_switch" check?

If so, I would prefer that we keep the check so that we do not tie the
maximum idle delay with the clear_inhibit_switch flag.  It is true that
today the only workaround that defines a maximum idle delay also sets
clear_inhibit_switch, but I think we should make the logic treat those
two things orthogonally, like it is already being done below.

>
> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Thanks! :-)

Let me know if I can go ahead with you r-b on the patch as-is; or if you
prefer to further discuss this.

--
Gustavo Sousa

>
> Regards,
> Bala
>
>> +
>> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>> +
>> +		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
>> +			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> +			wa_applied = true;
>> +		}
>> +
>> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> +		idledly_ps = idledly * idledly_units_ps;
>> +		idledly_hw_ps = idledly_ps;
>> +
>>  		/*
>>  		 * min_idledly_ps is applied before max_idledly_ps, which takes
>>  		 * priority if the two ever conflict (not expected in practice).
>> @@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  
>>  			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
>>  				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
>> -				  !!inhibit_switch, gt->info.timestamp_base);
>> +				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
>> +				  gt->info.timestamp_base);
>>  			xe_mmio_write32(&gt->mmio,
>>  					RING_IDLEDLY(hwe->mmio_base),
>>  					idledly_reg_val);
>> 
>> -- 
>> 2.56.0
>> 

Re: [PATCH v2 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Matt Atwood]

On Tue, Nov 03, 2026 at 11:20:24AM -0300, Gustavo Sousa wrote:
> "Vivekanandan, Balasubramani" <balasubramani.vivekanandan@intel.com>
> writes:
> 
> > On 30.10.2026 19:57, Gustavo Sousa wrote:
> >> Re-organize adjust_idledly() so that we return and avoid touching the
> >> hardware if no applicable workaround was found.
> >> 
> >> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >>  drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
> >>  1 file changed, 19 insertions(+), 13 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> >> index 01a7baf061eb..32d33c70e7f4 100644
> >> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> >> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> >> @@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
> >>  	u64 idledly_ps, idledly_hw_ps;
> >>  	u64 min_idledly_ps = 0;
> >>  	u64 max_idledly_ps = -1;
> >> -	bool inhibit_switch = false;
> >> +	bool clear_inhibit_switch = false;
> >>  	bool wa_applied = false;
> >>  
> >>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
> >> @@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
> >>  		if (!idledly_units_ps)
> >>  			return;
> >>  
> >> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> >> -		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> >> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> >> -		idledly_ps = idledly * idledly_units_ps;
> >> -		idledly_hw_ps = idledly_ps;
> >> -
> >>  		if (XE_GT_WA(gt, 14025941587))
> >>  			min_idledly_ps = max(min_idledly_ps, 5000000);
> >>  
> >> @@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
> >>  					       max_idledly_ps,
> >>  					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> >>  
> >> -			/* Clear the inhibit switch without disturbing a valid delay. */
> >> -			if (inhibit_switch) {
> >> -				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> >> -				wa_applied = true;
> >> -			}
> >> +			clear_inhibit_switch = true;
> >>  		}
> >>  
> >> +		/* No applicable workaround found. */
> >> +		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> >> +			return;
> >
> > We can skip the check for "max_idledly_ps == -1".
> 
> You say that because of the "!clear_inhibit_switch" check?
> 
> If so, I would prefer that we keep the check so that we do not tie the
> maximum idle delay with the clear_inhibit_switch flag.  It is true that
> today the only workaround that defines a maximum idle delay also sets
> clear_inhibit_switch, but I think we should make the logic treat those
> two things orthogonally, like it is already being done below.
> 
> >
> > Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Thanks! :-)
> 
> Let me know if I can go ahead with you r-b on the patch as-is; or if you
> prefer to further discuss this.
> 
> --
I agree with Gustavo here, please keep in the check. With that
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Gustavo Sousa
> 
> >
> > Regards,
> > Bala
> >
> >> +
> >> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> >> +
> >> +		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> >> +			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> >> +			wa_applied = true;
> >> +		}
> >> +
> >> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> >> +		idledly_ps = idledly * idledly_units_ps;
> >> +		idledly_hw_ps = idledly_ps;
> >> +
> >>  		/*
> >>  		 * min_idledly_ps is applied before max_idledly_ps, which takes
> >>  		 * priority if the two ever conflict (not expected in practice).
> >> @@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
> >>  
> >>  			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
> >>  				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
> >> -				  !!inhibit_switch, gt->info.timestamp_base);
> >> +				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
> >> +				  gt->info.timestamp_base);
> >>  			xe_mmio_write32(&gt->mmio,
> >>  					RING_IDLEDLY(hwe->mmio_base),
> >>  					idledly_reg_val);
> >> 
> >> -- 
> >> 2.56.0
> >>