* [PATCH 00/16] Add DSC fractional bpp support
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).
The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.
The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.
Ankit Nautiyal (13):
drm/i915/dp: Remove extra logs for printing DSC info
drm/i915/dp: Avoid forcing DSC BPC for MST case
drm/i915/dp: Do not check for min DSC BPC for MST case
drm/i915/dp: Check if dsc forced bpc is in allowed limits
drm/i915/dp: Avoid left shift of DSC output bpp by 4
drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp
drm/i915/dp: Get optimal link config to have best compressed bpp
drm/i915/display: Store compressed bpp in U6.4 format
drm/i915/display: Consider fractional vdsc bpp while computing m_n
values
drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
drm/display/dp: Fix the DP DSC Receiver cap size
drm/display/dp: Add helper function to get DSC bpp prescision
drm/i915/dp: Iterate over output bpp with fractional step size
Swati Sharma (2):
drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
drm/i915/dsc: Allow DSC only with fractional bpp when forced from
debugfs
Vandita Kulkarni (1):
drm/i915/dsc/mtl: Add support for fractional bpp
drivers/gpu/drm/display/drm_dp_helper.c | 27 ++
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +-
drivers/gpu/drm/i915/display/intel_audio.c | 14 +-
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_debugfs.c | 84 ++++
.../drm/i915/display/intel_display_types.h | 17 +-
drivers/gpu/drm/i915/display/intel_dp.c | 389 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 14 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
.../gpu/drm/i915/display/intel_qp_tables.c | 3 -
drivers/gpu/drm/i915/display/intel_vdsc.c | 16 +-
include/drm/display/drm_dp.h | 2 +-
include/drm/display/drm_dp_helper.h | 1 +
16 files changed, 487 insertions(+), 132 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] [PATCH 01/16] drm/i915/dp: Remove extra logs for printing DSC info
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 80d95cec8f9d..93aebd3683a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1576,9 +1576,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 01/16] drm/i915/dp: Remove extra logs for printing DSC info
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 80d95cec8f9d..93aebd3683a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1576,9 +1576,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 93aebd3683a4..3d828ea0894d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8b0e4defa3f1..9be04c60cced 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ if (intel_dp->force_dsc_bpc) {
+ /*
+ * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
+ * Avoid force BPC for now.
+ */
+ drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
+ return -EINVAL;
+ }
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 93aebd3683a4..3d828ea0894d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8b0e4defa3f1..9be04c60cced 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ if (intel_dp->force_dsc_bpc) {
+ /*
+ * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
+ * Avoid force BPC for now.
+ */
+ drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
+ return -EINVAL;
+ }
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-24 16:23 ` Jani Nikula
-1 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2023-01-24 16:23 UTC (permalink / raw)
To: Ankit Nautiyal, dri-devel, intel-gfx
On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> For MST the bpc is hardcoded to 8, and pipe bpp to 24.
> So avoid forcing DSC bpc for MST case.
It's likely better to warn and ignore the debug flag than to bail out.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 93aebd3683a4..3d828ea0894d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> - if (compute_pipe_bpp)
> + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
> + pipe_bpp = intel_dp->force_dsc_bpc * 3;
> + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
> + } else if (compute_pipe_bpp) {
> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
> - else
> + } else {
> pipe_bpp = pipe_config->pipe_bpp;
> -
> - if (intel_dp->force_dsc_bpc) {
> - pipe_bpp = intel_dp->force_dsc_bpc * 3;
> - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
> }
>
> /* Min Input BPC for ICL+ is 8 */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8b0e4defa3f1..9be04c60cced 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> /* enable compression if the mode doesn't fit available BW */
> drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
> if (ret || intel_dp->force_dsc_en) {
> + if (intel_dp->force_dsc_bpc) {
> + /*
> + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
> + * Avoid force BPC for now.
> + */
> + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
> + return -EINVAL;
> + }
> /*
> * Try to get at least some timeslots and then see, if
> * we can fit there with DSC.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
@ 2023-01-24 16:23 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2023-01-24 16:23 UTC (permalink / raw)
To: Ankit Nautiyal, dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> For MST the bpc is hardcoded to 8, and pipe bpp to 24.
> So avoid forcing DSC bpc for MST case.
It's likely better to warn and ignore the debug flag than to bail out.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 93aebd3683a4..3d828ea0894d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> - if (compute_pipe_bpp)
> + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
> + pipe_bpp = intel_dp->force_dsc_bpc * 3;
> + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
> + } else if (compute_pipe_bpp) {
> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
> - else
> + } else {
> pipe_bpp = pipe_config->pipe_bpp;
> -
> - if (intel_dp->force_dsc_bpc) {
> - pipe_bpp = intel_dp->force_dsc_bpc * 3;
> - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
> }
>
> /* Min Input BPC for ICL+ is 8 */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8b0e4defa3f1..9be04c60cced 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> /* enable compression if the mode doesn't fit available BW */
> drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
> if (ret || intel_dp->force_dsc_en) {
> + if (intel_dp->force_dsc_bpc) {
> + /*
> + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
> + * Avoid force BPC for now.
> + */
> + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
> + return -EINVAL;
> + }
> /*
> * Try to get at least some timeslots and then see, if
> * we can fit there with DSC.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
2023-01-24 16:23 ` Jani Nikula
@ 2023-01-25 5:02 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 41+ messages in thread
From: Nautiyal, Ankit K @ 2023-01-25 5:02 UTC (permalink / raw)
To: Jani Nikula, dri-devel, intel-gfx
On 1/24/2023 9:53 PM, Jani Nikula wrote:
> On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> For MST the bpc is hardcoded to 8, and pipe bpp to 24.
>> So avoid forcing DSC bpc for MST case.
> It's likely better to warn and ignore the debug flag than to bail out.
Hmm..but then the test using this flag will not come to know that bpc it
wanted to force, was indeed used.
Currently there is no way to read the bpc that was selected by the
driver, and so the test can try to force DSC, and the bpc and rely on
whether the ioctl passes or fails.
Regards,
Ankit
>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
>> 2 files changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 93aebd3683a4..3d828ea0894d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> return -EINVAL;
>>
>> - if (compute_pipe_bpp)
>> + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
>> + pipe_bpp = intel_dp->force_dsc_bpc * 3;
>> + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
>> + } else if (compute_pipe_bpp) {
>> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
>> - else
>> + } else {
>> pipe_bpp = pipe_config->pipe_bpp;
>> -
>> - if (intel_dp->force_dsc_bpc) {
>> - pipe_bpp = intel_dp->force_dsc_bpc * 3;
>> - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
>> }
>>
>> /* Min Input BPC for ICL+ is 8 */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 8b0e4defa3f1..9be04c60cced 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>> /* enable compression if the mode doesn't fit available BW */
>> drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
>> if (ret || intel_dp->force_dsc_en) {
>> + if (intel_dp->force_dsc_bpc) {
>> + /*
>> + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
>> + * Avoid force BPC for now.
>> + */
>> + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
>> + return -EINVAL;
>> + }
>> /*
>> * Try to get at least some timeslots and then see, if
>> * we can fit there with DSC.
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 02/16] drm/i915/dp: Avoid forcing DSC BPC for MST case
@ 2023-01-25 5:02 ` Nautiyal, Ankit K
0 siblings, 0 replies; 41+ messages in thread
From: Nautiyal, Ankit K @ 2023-01-25 5:02 UTC (permalink / raw)
To: Jani Nikula, dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
On 1/24/2023 9:53 PM, Jani Nikula wrote:
> On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> For MST the bpc is hardcoded to 8, and pipe bpp to 24.
>> So avoid forcing DSC bpc for MST case.
> It's likely better to warn and ignore the debug flag than to bail out.
Hmm..but then the test using this flag will not come to know that bpc it
wanted to force, was indeed used.
Currently there is no way to read the bpc that was selected by the
driver, and so the test can try to force DSC, and the bpc and rely on
whether the ioctl passes or fails.
Regards,
Ankit
>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
>> 2 files changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 93aebd3683a4..3d828ea0894d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> return -EINVAL;
>>
>> - if (compute_pipe_bpp)
>> + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
>> + pipe_bpp = intel_dp->force_dsc_bpc * 3;
>> + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
>> + } else if (compute_pipe_bpp) {
>> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
>> - else
>> + } else {
>> pipe_bpp = pipe_config->pipe_bpp;
>> -
>> - if (intel_dp->force_dsc_bpc) {
>> - pipe_bpp = intel_dp->force_dsc_bpc * 3;
>> - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
>> }
>>
>> /* Min Input BPC for ICL+ is 8 */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 8b0e4defa3f1..9be04c60cced 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>> /* enable compression if the mode doesn't fit available BW */
>> drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
>> if (ret || intel_dp->force_dsc_en) {
>> + if (intel_dp->force_dsc_bpc) {
>> + /*
>> + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above,
>> + * Avoid force BPC for now.
>> + */
>> + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n");
>> + return -EINVAL;
>> + }
>> /*
>> * Try to get at least some timeslots and then see, if
>> * we can fit there with DSC.
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 03/16] drm/i915/dp: Do not check for min DSC BPC for MST case
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases only where pipe_bpp is to be computed.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 46 ++++++++++++++++---------
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d828ea0894d..d061fc3fa402 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1480,6 +1480,13 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ /* Min Input BPC for ICL+ is 8 */
+ return (pipe_bpp < 8 * 3);
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1491,7 +1498,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1501,27 +1507,35 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ int forced_bpc = intel_dp->force_dsc_bpc;
+ int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
- return -EINVAL;
+ /* Min Input BPC for ICL+ is 8 */
+ if (forced_bpc < 8) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Cannot force dsc bpc:%d, due to dsc bpc limits\n",
+ intel_dp->force_dsc_bpc);
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
+ pipe_config->pipe_bpp);
+ } else if (compute_pipe_bpp) {
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No DSC support for less than 8bpc\n");
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1544,7 +1558,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 03/16] drm/i915/dp: Do not check for min DSC BPC for MST case
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases only where pipe_bpp is to be computed.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 46 ++++++++++++++++---------
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d828ea0894d..d061fc3fa402 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1480,6 +1480,13 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ /* Min Input BPC for ICL+ is 8 */
+ return (pipe_bpp < 8 * 3);
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1491,7 +1498,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1501,27 +1507,35 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ int forced_bpc = intel_dp->force_dsc_bpc;
+ int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
- return -EINVAL;
+ /* Min Input BPC for ICL+ is 8 */
+ if (forced_bpc < 8) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Cannot force dsc bpc:%d, due to dsc bpc limits\n",
+ intel_dp->force_dsc_bpc);
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
+ pipe_config->pipe_bpp);
+ } else if (compute_pipe_bpp) {
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No DSC support for less than 8bpc\n");
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1544,7 +1558,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 04/16] drm/i915/dp: Check if dsc forced bpc is in allowed limits
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Add a check to use force DSC bpc only if it, along with the
corresponding bpp are within allowed limits.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d061fc3fa402..354dbd1d3164 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1510,19 +1510,20 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (forced_bpc < 8) {
+ if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */
+ forced_bpc > conn_state->max_requested_bpc ||
+ forced_bpp < limits->min_bpp ||
+ forced_bpp > limits->max_bpp) {
drm_dbg_kms(&dev_priv->drm,
- "Cannot force dsc bpc:%d, due to dsc bpc limits\n",
+ "Cannot force dsc bpc:%d, due to bpc/bpp limits\n",
intel_dp->force_dsc_bpc);
return -EINVAL;
}
pipe_config->pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
- pipe_config->pipe_bpp);
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
"No DSC support for less than 8bpc\n");
@@ -1530,7 +1531,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
}
pipe_config->pipe_bpp = pipe_bpp;
}
-
/*
* For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 04/16] drm/i915/dp: Check if dsc forced bpc is in allowed limits
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
Add a check to use force DSC bpc only if it, along with the
corresponding bpp are within allowed limits.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d061fc3fa402..354dbd1d3164 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1510,19 +1510,20 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (forced_bpc < 8) {
+ if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */
+ forced_bpc > conn_state->max_requested_bpc ||
+ forced_bpp < limits->min_bpp ||
+ forced_bpp > limits->max_bpp) {
drm_dbg_kms(&dev_priv->drm,
- "Cannot force dsc bpc:%d, due to dsc bpc limits\n",
+ "Cannot force dsc bpc:%d, due to bpc/bpp limits\n",
intel_dp->force_dsc_bpc);
return -EINVAL;
}
pipe_config->pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
- pipe_config->pipe_bpp);
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
"No DSC support for less than 8bpc\n");
@@ -1530,7 +1531,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
}
pipe_config->pipe_bpp = pipe_bpp;
}
-
/*
* For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 05/16] drm/i915/dp: Avoid left shift of DSC output bpp by 4
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 354dbd1d3164..c52e9979f0a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -749,11 +749,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1050,7 +1046,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1585,7 +1581,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
*/
if (compute_pipe_bpp) {
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_output_bpp,
pipe_config->pipe_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9be04c60cced..5b65e4c2c78f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -921,7 +921,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 05/16] drm/i915/dp: Avoid left shift of DSC output bpp by 4
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 354dbd1d3164..c52e9979f0a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -749,11 +749,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1050,7 +1046,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1585,7 +1581,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
*/
if (compute_pipe_bpp) {
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_output_bpp,
pipe_config->pipe_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9be04c60cced..5b65e4c2c78f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -921,7 +921,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 06/16] drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Currently the required dsc output bpp is set to be the largest
compressed bpp supported for max, lane, rate, and bpp.
The helper intel_dp_dsc_get_output_bpp gets the maximum supported
compressed bpp taking into account link configuration, input bpp,
bigjoiner considerations etc.
Similarly, the helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the functions to reflect that these return max DSC input and
output bpps.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++----
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c52e9979f0a4..c0b96cfb7528 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -702,12 +702,12 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1030,7 +1030,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
@@ -1040,13 +1040,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1375,7 +1375,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1518,7 +1518,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp = forced_bpp;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
@@ -1548,14 +1548,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (compute_pipe_bpp) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->pipe_bpp,
- timeslots);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->pipe_bpp,
+ timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index ef39e4f7a329..7cb8227a4d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -102,13 +102,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots);
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5b65e4c2c78f..df19691776ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -911,17 +911,17 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 06/16] drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
Currently the required dsc output bpp is set to be the largest
compressed bpp supported for max, lane, rate, and bpp.
The helper intel_dp_dsc_get_output_bpp gets the maximum supported
compressed bpp taking into account link configuration, input bpp,
bigjoiner considerations etc.
Similarly, the helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the functions to reflect that these return max DSC input and
output bpps.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++----
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c52e9979f0a4..c0b96cfb7528 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -702,12 +702,12 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1030,7 +1030,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
@@ -1040,13 +1040,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1375,7 +1375,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1518,7 +1518,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp = forced_bpp;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
@@ -1548,14 +1548,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (compute_pipe_bpp) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->pipe_bpp,
- timeslots);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->pipe_bpp,
+ timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index ef39e4f7a329..7cb8227a4d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -102,13 +102,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots);
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5b65e4c2c78f..df19691776ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -911,17 +911,17 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 07/16] drm/i915/dp: Get optimal link config to have best compressed bpp
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 278 ++++++++++++++++++++----
1 file changed, 232 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c0b96cfb7528..885d2f75ddbf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1476,6 +1476,195 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp,
+ const struct drm_display_mode *adjusted_mode)
+{
+ int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp);
+ int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
+
+ return mode_rate <= link_avail;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ u16 compressed_bpp)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int dsc_max_bpp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ dsc_max_bpp = intel_dp_dsc_get_output_bpp_max(dev_priv,
+ link_rate,
+ lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_bpp, 64);
+ if (compressed_bpp > dsc_max_bpp)
+ continue;
+
+ if (!is_dsc_bw_sufficient(link_rate, lane_count,
+ compressed_bpp, adjusted_mode))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static u16 dsc_max_sink_compressed_bppx16(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
+ (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static u16 dsc_min_compressed_bppx16(struct intel_crtc_state *pipe_config)
+{
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8 << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6 << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u16 compressed_bpp;
+ int dsc_min_bpp, dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int ret;
+
+ dsc_min_bpp = max(dsc_min_compressed_bppx16(pipe_config) >> 4, 8);
+ if (DISPLAY_VER(dev_priv) <= 12)
+ dsc_src_max_bpp = 23;
+ else
+ dsc_src_max_bpp = 27;
+ dsc_sink_max_bpp = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
+ pipe_config, pipe_bpp / 3) >> 4;
+
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ pipe_bpp,
+ compressed_bpp);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ int i, bpp, ret;
+ int num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+
+ /* Min DSC Input BPC for ICL+ is 8 */
+ dsc_min_bpc = 8;
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ for (i = 0; i < num_bpc; i++) {
+ bpp = dsc_bpc[i] * 3;
+
+ if (bpp < dsc_min_bpp)
+ break;
+
+ if (bpp > dsc_max_bpp)
+ continue;
+
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, bpp);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = bpp;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
static
bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
{
@@ -1502,6 +1691,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ /* Compute DSC input BPP and output/compressed BPP */
if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
@@ -1515,53 +1705,61 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
intel_dp->force_dsc_bpc);
return -EINVAL;
}
+ if (dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Compressed BPP not supported with forced bpc = %d\n",
+ intel_dp->force_dsc_bpc);
+ return -EINVAL;
+ }
+
pipe_config->pipe_bpp = forced_bpp;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
- return -EINVAL;
+ if (intel_dp_is_edp(intel_dp)) {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No DSC support for less than 8bpc\n");
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = pipe_bpp;
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_config->pipe_bpp);
+ } else {
+ /*
+ * For DP compute the optimal pipe bpp, link rate and
+ * num lanes with DSC.
+ */
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode\n");
+ return ret;
+ }
}
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else {
- u16 dsc_max_output_bpp = 0;
u8 dsc_dp_slice_count;
-
- if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp_max(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1572,18 +1770,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Compressed Slice Count not supported\n");
return -EINVAL;
}
-
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp,
- pipe_config->pipe_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 07/16] drm/i915/dp: Get optimal link config to have best compressed bpp
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 278 ++++++++++++++++++++----
1 file changed, 232 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c0b96cfb7528..885d2f75ddbf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1476,6 +1476,195 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp,
+ const struct drm_display_mode *adjusted_mode)
+{
+ int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp);
+ int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
+
+ return mode_rate <= link_avail;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ u16 compressed_bpp)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int dsc_max_bpp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ dsc_max_bpp = intel_dp_dsc_get_output_bpp_max(dev_priv,
+ link_rate,
+ lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_bpp, 64);
+ if (compressed_bpp > dsc_max_bpp)
+ continue;
+
+ if (!is_dsc_bw_sufficient(link_rate, lane_count,
+ compressed_bpp, adjusted_mode))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static u16 dsc_max_sink_compressed_bppx16(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
+ (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static u16 dsc_min_compressed_bppx16(struct intel_crtc_state *pipe_config)
+{
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8 << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6 << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u16 compressed_bpp;
+ int dsc_min_bpp, dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int ret;
+
+ dsc_min_bpp = max(dsc_min_compressed_bppx16(pipe_config) >> 4, 8);
+ if (DISPLAY_VER(dev_priv) <= 12)
+ dsc_src_max_bpp = 23;
+ else
+ dsc_src_max_bpp = 27;
+ dsc_sink_max_bpp = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
+ pipe_config, pipe_bpp / 3) >> 4;
+
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ pipe_bpp,
+ compressed_bpp);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ int i, bpp, ret;
+ int num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+
+ /* Min DSC Input BPC for ICL+ is 8 */
+ dsc_min_bpc = 8;
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ for (i = 0; i < num_bpc; i++) {
+ bpp = dsc_bpc[i] * 3;
+
+ if (bpp < dsc_min_bpp)
+ break;
+
+ if (bpp > dsc_max_bpp)
+ continue;
+
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, bpp);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = bpp;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
static
bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
{
@@ -1502,6 +1691,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ /* Compute DSC input BPP and output/compressed BPP */
if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
@@ -1515,53 +1705,61 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
intel_dp->force_dsc_bpc);
return -EINVAL;
}
+ if (dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Compressed BPP not supported with forced bpc = %d\n",
+ intel_dp->force_dsc_bpc);
+ return -EINVAL;
+ }
+
pipe_config->pipe_bpp = forced_bpp;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
- return -EINVAL;
+ if (intel_dp_is_edp(intel_dp)) {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No DSC support for less than 8bpc\n");
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = pipe_bpp;
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_config->pipe_bpp);
+ } else {
+ /*
+ * For DP compute the optimal pipe bpp, link rate and
+ * num lanes with DSC.
+ */
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode\n");
+ return ret;
+ }
}
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else {
- u16 dsc_max_output_bpp = 0;
u8 dsc_dp_slice_count;
-
- if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp_max(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1572,18 +1770,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Compressed Slice Count not supported\n");
return -EINVAL;
}
-
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp,
- pipe_config->pipe_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 08/16] drm/i915/display: Store compressed bpp in U6.4 format
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
.../drm/i915/display/intel_display_types.h | 16 +++++++++++-
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
6 files changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae14c794c4bc..f387450c4be2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -343,7 +343,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -903,7 +903,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
- mul = crtc_state->dsc.compressed_bpp;
+ mul = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@@ -927,7 +927,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1500,8 +1500,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- if (pipe_config->dsc.compressed_bpp) {
- int div = pipe_config->dsc.compressed_bpp;
+ if (dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)) {
+ int div = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 626c47e96a6d..a73cf477b5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -517,7 +517,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = crtc_state->dsc.compressed_bpp;
+ vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 78abe34c7a42..75343bca8750 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3482,7 +3482,7 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3;
crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
- VBT_DSC_MAX_BPP(dsc->max_bpp));
+ VBT_DSC_MAX_BPP(dsc->max_bpp)) << 4;
/*
* FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 32e8b2fc3cc6..e879a9483148 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1283,7 +1283,7 @@ struct intel_crtc_state {
struct {
bool compression_enable;
bool dsc_split;
- u16 compressed_bpp;
+ u16 compressed_bpp; /* U6.4 format (first 4 bits for fractional part) */
u8 slice_count;
struct drm_dsc_config config;
} dsc;
@@ -2062,4 +2062,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+/* Returns integral part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_integral_compressed_bpp(u16 compressed_bpp)
+{
+ return compressed_bpp >> 4;
+}
+
+/* Returns fractional part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_fractional_compressed_bpp(u16 compressed_bpp)
+{
+ return ((compressed_bpp & 0xF) * 10000 / 16);
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 885d2f75ddbf..ce7bffbdad9e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1606,7 +1606,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
pipe_bpp,
compressed_bpp);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = compressed_bpp;
+ pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
return 0;
}
}
@@ -1737,8 +1737,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd),
+ pipe_config->pipe_bpp << 4);
} else {
/*
* For DP compute the optimal pipe bpp, link rate and
@@ -1792,17 +1792,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d "
- "Compressed BPP = %d\n",
+ "Compressed BPP = %d.%d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
- "Compressed Bpp = %d Slice Count = %d\n",
+ "Compressed Bpp = %d.%d Slice Count = %d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp,
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp),
pipe_config->dsc.slice_count);
return 0;
@@ -1881,15 +1883,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable) {
drm_dbg_kms(&i915->drm,
- "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+ "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
drm_dbg_kms(&i915->drm,
"DP link rate required %i available %i\n",
intel_dp_link_required(adjusted_mode->crtc_clock,
- pipe_config->dsc.compressed_bpp),
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count));
} else {
@@ -2315,7 +2318,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed5c85229414 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -452,7 +452,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
- u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+ u16 compressed_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
@@ -1210,7 +1210,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
val = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
vdsc_cfg->bits_per_pixel = val;
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel;
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 08/16] drm/i915/display: Store compressed bpp in U6.4 format
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
.../drm/i915/display/intel_display_types.h | 16 +++++++++++-
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
6 files changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae14c794c4bc..f387450c4be2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -343,7 +343,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -903,7 +903,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
- mul = crtc_state->dsc.compressed_bpp;
+ mul = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@@ -927,7 +927,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1500,8 +1500,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- if (pipe_config->dsc.compressed_bpp) {
- int div = pipe_config->dsc.compressed_bpp;
+ if (dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)) {
+ int div = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 626c47e96a6d..a73cf477b5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -517,7 +517,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = crtc_state->dsc.compressed_bpp;
+ vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 78abe34c7a42..75343bca8750 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3482,7 +3482,7 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3;
crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
- VBT_DSC_MAX_BPP(dsc->max_bpp));
+ VBT_DSC_MAX_BPP(dsc->max_bpp)) << 4;
/*
* FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 32e8b2fc3cc6..e879a9483148 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1283,7 +1283,7 @@ struct intel_crtc_state {
struct {
bool compression_enable;
bool dsc_split;
- u16 compressed_bpp;
+ u16 compressed_bpp; /* U6.4 format (first 4 bits for fractional part) */
u8 slice_count;
struct drm_dsc_config config;
} dsc;
@@ -2062,4 +2062,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+/* Returns integral part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_integral_compressed_bpp(u16 compressed_bpp)
+{
+ return compressed_bpp >> 4;
+}
+
+/* Returns fractional part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_fractional_compressed_bpp(u16 compressed_bpp)
+{
+ return ((compressed_bpp & 0xF) * 10000 / 16);
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 885d2f75ddbf..ce7bffbdad9e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1606,7 +1606,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
pipe_bpp,
compressed_bpp);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = compressed_bpp;
+ pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
return 0;
}
}
@@ -1737,8 +1737,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd),
+ pipe_config->pipe_bpp << 4);
} else {
/*
* For DP compute the optimal pipe bpp, link rate and
@@ -1792,17 +1792,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d "
- "Compressed BPP = %d\n",
+ "Compressed BPP = %d.%d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
- "Compressed Bpp = %d Slice Count = %d\n",
+ "Compressed Bpp = %d.%d Slice Count = %d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp,
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp),
pipe_config->dsc.slice_count);
return 0;
@@ -1881,15 +1883,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable) {
drm_dbg_kms(&i915->drm,
- "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+ "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+ dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
drm_dbg_kms(&i915->drm,
"DP link rate required %i available %i\n",
intel_dp_link_required(adjusted_mode->crtc_clock,
- pipe_config->dsc.compressed_bpp),
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count));
} else {
@@ -2315,7 +2318,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed5c85229414 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -452,7 +452,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
- u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+ u16 compressed_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
@@ -1210,7 +1210,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
val = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
vdsc_cfg->bits_per_pixel = val;
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel;
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 09/16] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 734e8e613f8e..9912930890d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2748,10 +2748,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ef73730f32b0..3c2016edad18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -514,7 +514,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ce7bffbdad9e..3d08acb4505a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2178,7 +2178,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2318,7 +2318,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
+ output_bpp = pipe_config->dsc.compressed_bpp;
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
@@ -2350,7 +2350,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
&pipe_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index df19691776ca..67d6e261eb68 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -143,7 +143,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
@@ -237,7 +238,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ crtc_state->dsc.compression_enable);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 063f1da4f229..5ab6c2e983d5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -257,7 +257,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n, false);
+ link_bw, &pipe_config->fdi_m_n, false, false);
ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
if (ret == -EDEADLK)
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 09/16] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 734e8e613f8e..9912930890d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2748,10 +2748,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ef73730f32b0..3c2016edad18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -514,7 +514,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ce7bffbdad9e..3d08acb4505a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2178,7 +2178,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2318,7 +2318,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
+ output_bpp = pipe_config->dsc.compressed_bpp;
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
@@ -2350,7 +2350,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
&pipe_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index df19691776ca..67d6e261eb68 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -143,7 +143,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
@@ -237,7 +238,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ crtc_state->dsc.compression_enable);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 063f1da4f229..5ab6c2e983d5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -257,7 +257,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n, false);
+ link_bw, &pipe_config->fdi_m_n, false, false);
ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
if (ret == -EDEADLK)
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 10/16] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index a73cf477b5e6..30d75f637793 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -510,14 +510,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
unsigned int link_clks_available, link_clks_required;
unsigned int tu_data, tu_line, link_clks_active;
unsigned int h_active, h_total, hblank_delta, pixel_clk;
- unsigned int fec_coeff, cdclk, vdsc_bpp;
+ unsigned int fec_coeff, cdclk, vdsc_bppx16;
unsigned int link_clk, lanes;
unsigned int hblank_rise;
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
+ vdsc_bppx16 = crtc_state->dsc.compressed_bpp;
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
@@ -525,10 +525,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
- "lanes = %u vdsc_bpp = %u cdclk = %u\n",
- h_active, link_clk, lanes, vdsc_bpp, cdclk);
+ "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+ h_active, link_clk, lanes, vdsc_bppx16, cdclk);
- if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+ if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
return 0;
link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -540,8 +540,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
mul_u32_u32(link_clk, cdclk));
- tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
- mul_u32_u32(link_clk * lanes, fec_coeff));
+ tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+ mul_u32_u32(link_clk * lanes * 16, fec_coeff));
tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
mul_u32_u32(64 * pixel_clk, 1000000));
link_clks_active = (tu_line - 1) * 64 + tu_data;
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 10/16] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index a73cf477b5e6..30d75f637793 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -510,14 +510,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
unsigned int link_clks_available, link_clks_required;
unsigned int tu_data, tu_line, link_clks_active;
unsigned int h_active, h_total, hblank_delta, pixel_clk;
- unsigned int fec_coeff, cdclk, vdsc_bpp;
+ unsigned int fec_coeff, cdclk, vdsc_bppx16;
unsigned int link_clk, lanes;
unsigned int hblank_rise;
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
+ vdsc_bppx16 = crtc_state->dsc.compressed_bpp;
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
@@ -525,10 +525,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
- "lanes = %u vdsc_bpp = %u cdclk = %u\n",
- h_active, link_clk, lanes, vdsc_bpp, cdclk);
+ "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+ h_active, link_clk, lanes, vdsc_bppx16, cdclk);
- if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+ if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
return 0;
link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -540,8 +540,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
mul_u32_u32(link_clk, cdclk));
- tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
- mul_u32_u32(link_clk * lanes, fec_coeff));
+ tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+ mul_u32_u32(link_clk * lanes * 16, fec_coeff));
tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
mul_u32_u32(64 * pixel_clk, 1000000));
link_clks_active = (tu_line - 1) * 64 + tu_data;
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 11/16] drm/display/dp: Fix the DP DSC Receiver cap size
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..bdc05593f462 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1532,7 +1532,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 11/16] drm/display/dp: Fix the DP DSC Receiver cap size
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..bdc05593f462 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1532,7 +1532,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 12/16] drm/display/dp: Add helper function to get DSC bpp prescision
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 16565a0a5da6..db3288af4032 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
}
EXPORT_SYMBOL(drm_dp_read_desc);
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+ switch (bpp_increment_dpcd) {
+ case DP_DSC_BITS_PER_PIXEL_1_16:
+ return 16;
+ case DP_DSC_BITS_PER_PIXEL_1_8:
+ return 8;
+ case DP_DSC_BITS_PER_PIXEL_1_4:
+ return 4;
+ case DP_DSC_BITS_PER_PIXEL_1_2:
+ return 2;
+ case DP_DSC_BITS_PER_PIXEL_1_1:
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..0a0306b2e829 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 12/16] drm/display/dp: Add helper function to get DSC bpp prescision
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 16565a0a5da6..db3288af4032 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
}
EXPORT_SYMBOL(drm_dp_read_desc);
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+ switch (bpp_increment_dpcd) {
+ case DP_DSC_BITS_PER_PIXEL_1_16:
+ return 16;
+ case DP_DSC_BITS_PER_PIXEL_1_8:
+ return 8;
+ case DP_DSC_BITS_PER_PIXEL_1_4:
+ return 4;
+ case DP_DSC_BITS_PER_PIXEL_1_2:
+ return 2;
+ case DP_DSC_BITS_PER_PIXEL_1_1:
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..0a0306b2e829 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 13/16] drm/i915/dsc/mtl: Add support for fractional bpp
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Consider the fractional bpp while reading the qp values.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +++++++++---
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..a0094287dc81 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -21,9 +21,6 @@
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
* in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
*/
static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed5c85229414..3e39f682b19f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -378,6 +378,7 @@ calculate_rc_params(struct rc_parameters *rc,
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int fractional_bits = vdsc_cfg->bits_per_pixel & 0xf;
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
};
@@ -418,7 +419,13 @@ calculate_rc_params(struct rc_parameters *rc,
rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
- bpp_i = (2 * (bpp - 6));
+ /*
+ * QP table rows have values in increment of 0.5.
+ * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+ * and so on.
+ * 0.5 represented as 0x8 in U6.4 format.
+ */
+ bpp_i = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
rc->rc_range_params[buf_i].range_min_qp =
@@ -466,8 +473,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
- /* Gen 11 only supports integral values of bpp */
- vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 13/16] drm/i915/dsc/mtl: Add support for fractional bpp
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Consider the fractional bpp while reading the qp values.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +++++++++---
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..a0094287dc81 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -21,9 +21,6 @@
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
* in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
*/
static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed5c85229414..3e39f682b19f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -378,6 +378,7 @@ calculate_rc_params(struct rc_parameters *rc,
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int fractional_bits = vdsc_cfg->bits_per_pixel & 0xf;
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
};
@@ -418,7 +419,13 @@ calculate_rc_params(struct rc_parameters *rc,
rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
- bpp_i = (2 * (bpp - 6));
+ /*
+ * QP table rows have values in increment of 0.5.
+ * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+ * and so on.
+ * 0.5 represented as 0x8 in U6.4 format.
+ */
+ bpp_i = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
rc->rc_range_params[buf_i].range_min_qp =
@@ -466,8 +473,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
- /* Gen 11 only supports integral values of bpp */
- vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 14/16] drm/i915/dp: Iterate over output bpp with fractional step size
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++----------
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d08acb4505a..8dede5969af5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1476,10 +1476,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp,
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bppx16,
const struct drm_display_mode *adjusted_mode)
{
- int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp);
+ int mode_rate = DIV_ROUND_UP(intel_dp_link_required(adjusted_mode->crtc_clock,
+ compressed_bppx16), 16);
int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
return mode_rate <= link_avail;
@@ -1489,7 +1490,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
int pipe_bpp,
- u16 compressed_bpp)
+ u16 compressed_bppx16)
{
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1513,11 +1514,11 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_bpp, 64);
- if (compressed_bpp > dsc_max_bpp)
+ if (compressed_bppx16 > dsc_max_bpp << 16)
continue;
if (!is_dsc_bw_sufficient(link_rate, lane_count,
- compressed_bpp, adjusted_mode))
+ compressed_bppx16, adjusted_mode))
continue;
pipe_config->lane_count = lane_count;
@@ -1580,33 +1581,41 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int pipe_bpp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u16 compressed_bpp;
- int dsc_min_bpp, dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ u16 compressed_bppx16;
+ int dsc_min_bppx16, dsc_src_max_bppx16, dsc_sink_max_bppx16, dsc_max_bppx16;
+ u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+ u8 bppx16_step;
int ret;
- dsc_min_bpp = max(dsc_min_compressed_bppx16(pipe_config) >> 4, 8);
+ if (DISPLAY_VER(dev_priv) < 14 || bppx16_incr <= 1)
+ bppx16_step = 16;
+ else
+ bppx16_step = 16 / bppx16_incr;
+
+ dsc_min_bppx16 = max((int)dsc_min_compressed_bppx16(pipe_config), 8 << 4);
if (DISPLAY_VER(dev_priv) <= 12)
- dsc_src_max_bpp = 23;
+ dsc_src_max_bppx16 = 23 << 4;
else
- dsc_src_max_bpp = 27;
- dsc_sink_max_bpp = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
- pipe_config, pipe_bpp / 3) >> 4;
+ dsc_src_max_bppx16 = 27 << 4;
+ dsc_sink_max_bppx16 = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
+ pipe_config, pipe_bpp / 3);
- dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+ dsc_max_bppx16 = dsc_sink_max_bppx16 ?
+ min(dsc_sink_max_bppx16, dsc_src_max_bppx16) : dsc_src_max_bppx16;
/* Compressed BPP should be less than the Input DSC bpp */
- dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+ dsc_max_bppx16 = min(dsc_max_bppx16, (pipe_bpp << 4) - bppx16_step);
- for (compressed_bpp = dsc_max_bpp;
- compressed_bpp >= dsc_min_bpp;
- compressed_bpp--) {
+ for (compressed_bppx16 = dsc_max_bppx16;
+ compressed_bppx16 >= dsc_min_bppx16;
+ compressed_bppx16 -= bppx16_step) {
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
pipe_bpp,
- compressed_bpp);
+ compressed_bppx16);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
+ pipe_config->dsc.compressed_bpp = compressed_bppx16;
return 0;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 14/16] drm/i915/dp: Iterate over output bpp with fractional step size
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++----------
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d08acb4505a..8dede5969af5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1476,10 +1476,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp,
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bppx16,
const struct drm_display_mode *adjusted_mode)
{
- int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp);
+ int mode_rate = DIV_ROUND_UP(intel_dp_link_required(adjusted_mode->crtc_clock,
+ compressed_bppx16), 16);
int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
return mode_rate <= link_avail;
@@ -1489,7 +1490,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
int pipe_bpp,
- u16 compressed_bpp)
+ u16 compressed_bppx16)
{
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1513,11 +1514,11 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_bpp, 64);
- if (compressed_bpp > dsc_max_bpp)
+ if (compressed_bppx16 > dsc_max_bpp << 16)
continue;
if (!is_dsc_bw_sufficient(link_rate, lane_count,
- compressed_bpp, adjusted_mode))
+ compressed_bppx16, adjusted_mode))
continue;
pipe_config->lane_count = lane_count;
@@ -1580,33 +1581,41 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int pipe_bpp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u16 compressed_bpp;
- int dsc_min_bpp, dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ u16 compressed_bppx16;
+ int dsc_min_bppx16, dsc_src_max_bppx16, dsc_sink_max_bppx16, dsc_max_bppx16;
+ u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+ u8 bppx16_step;
int ret;
- dsc_min_bpp = max(dsc_min_compressed_bppx16(pipe_config) >> 4, 8);
+ if (DISPLAY_VER(dev_priv) < 14 || bppx16_incr <= 1)
+ bppx16_step = 16;
+ else
+ bppx16_step = 16 / bppx16_incr;
+
+ dsc_min_bppx16 = max((int)dsc_min_compressed_bppx16(pipe_config), 8 << 4);
if (DISPLAY_VER(dev_priv) <= 12)
- dsc_src_max_bpp = 23;
+ dsc_src_max_bppx16 = 23 << 4;
else
- dsc_src_max_bpp = 27;
- dsc_sink_max_bpp = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
- pipe_config, pipe_bpp / 3) >> 4;
+ dsc_src_max_bppx16 = 27 << 4;
+ dsc_sink_max_bppx16 = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
+ pipe_config, pipe_bpp / 3);
- dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+ dsc_max_bppx16 = dsc_sink_max_bppx16 ?
+ min(dsc_sink_max_bppx16, dsc_src_max_bppx16) : dsc_src_max_bppx16;
/* Compressed BPP should be less than the Input DSC bpp */
- dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+ dsc_max_bppx16 = min(dsc_max_bppx16, (pipe_bpp << 4) - bppx16_step);
- for (compressed_bpp = dsc_max_bpp;
- compressed_bpp >= dsc_min_bpp;
- compressed_bpp--) {
+ for (compressed_bppx16 = dsc_max_bppx16;
+ compressed_bppx16 >= dsc_min_bppx16;
+ compressed_bppx16 -= bppx16_step) {
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
pipe_bpp,
- compressed_bpp);
+ compressed_bppx16);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
+ pipe_config->dsc.compressed_bpp = compressed_bppx16;
return 0;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 15/16] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
From: Swati Sharma <swati2.sharma@intel.com>
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 84 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 1 +
2 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7bcd90384a46..2b36ec812293 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1772,6 +1772,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
+ seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+ drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
@@ -1895,6 +1897,85 @@ static const struct file_operations i915_dsc_bpc_fops = {
.write = i915_dsc_bpc_write
};
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct intel_dp *intel_dp;
+ struct intel_crtc_state *crtc_state;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ int ret;
+
+ if (!encoder)
+ return -ENODEV;
+
+ ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->state->crtc;
+ if (connector->status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ intel_dp = intel_attached_dp(to_intel_connector(connector));
+ crtc_state = to_intel_crtc_state(crtc->state);
+ seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+ str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ bool dsc_fractional_bpp_enable = false;
+ int ret;
+
+ if (len == 0)
+ return 0;
+
+ drm_dbg(&i915->drm,
+ "Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+ ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+ if (ret < 0)
+ return ret;
+
+ drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+ (dsc_fractional_bpp_enable) ? "true" : "false");
+ intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+ *offp += len;
+
+ return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_fractional_bpp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_fractional_bpp_write
+};
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2047,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
debugfs_create_file("i915_dsc_bpc", 0644, root,
connector, &i915_dsc_bpc_fops);
+
+ debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+ connector, &i915_dsc_fractional_bpp_fops);
}
if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e879a9483148..1c5930d78749 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1737,6 +1737,7 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+ bool force_dsc_fractional_bpp_en;
int force_dsc_bpc;
bool hobl_failed;
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 15/16] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
From: Swati Sharma <swati2.sharma@intel.com>
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 84 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 1 +
2 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7bcd90384a46..2b36ec812293 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1772,6 +1772,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
+ seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+ drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
@@ -1895,6 +1897,85 @@ static const struct file_operations i915_dsc_bpc_fops = {
.write = i915_dsc_bpc_write
};
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct intel_dp *intel_dp;
+ struct intel_crtc_state *crtc_state;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ int ret;
+
+ if (!encoder)
+ return -ENODEV;
+
+ ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->state->crtc;
+ if (connector->status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ intel_dp = intel_attached_dp(to_intel_connector(connector));
+ crtc_state = to_intel_crtc_state(crtc->state);
+ seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+ str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ bool dsc_fractional_bpp_enable = false;
+ int ret;
+
+ if (len == 0)
+ return 0;
+
+ drm_dbg(&i915->drm,
+ "Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+ ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+ if (ret < 0)
+ return ret;
+
+ drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+ (dsc_fractional_bpp_enable) ? "true" : "false");
+ intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+ *offp += len;
+
+ return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_fractional_bpp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_fractional_bpp_write
+};
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2047,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
debugfs_create_file("i915_dsc_bpc", 0644, root,
connector, &i915_dsc_bpc_fops);
+
+ debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+ connector, &i915_dsc_fractional_bpp_fops);
}
if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e879a9483148..1c5930d78749 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1737,6 +1737,7 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+ bool force_dsc_fractional_bpp_en;
int force_dsc_bpc;
bool hobl_failed;
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] [PATCH 16/16] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
2023-01-20 4:38 ` Ankit Nautiyal
@ 2023-01-20 4:38 ` Ankit Nautiyal
-1 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
From: Swati Sharma <swati2.sharma@intel.com>
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if we computed compressed bpp is
computed as integer.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8dede5969af5..48ade9077352 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1609,6 +1609,9 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
for (compressed_bppx16 = dsc_max_bppx16;
compressed_bppx16 >= dsc_min_bppx16;
compressed_bppx16 -= bppx16_step) {
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ (compressed_bppx16 % 16 == 0))
+ continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -1705,6 +1708,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
+ if (intel_dp->force_dsc_fractional_bpp_en)
+ drm_dbg_kms(&dev_priv->drm,
+ "Forcing DSC fractional bpp\n");
if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */
forced_bpc > conn_state->max_requested_bpc ||
forced_bpp < limits->min_bpp ||
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH 16/16] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
@ 2023-01-20 4:38 ` Ankit Nautiyal
0 siblings, 0 replies; 41+ messages in thread
From: Ankit Nautiyal @ 2023-01-20 4:38 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: manasi.d.navare, vandita.kulkarni, anusha.srivatsa, swati2.sharma,
stanislav.lisovskiy
From: Swati Sharma <swati2.sharma@intel.com>
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if we computed compressed bpp is
computed as integer.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8dede5969af5..48ade9077352 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1609,6 +1609,9 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
for (compressed_bppx16 = dsc_max_bppx16;
compressed_bppx16 >= dsc_min_bppx16;
compressed_bppx16 -= bppx16_step) {
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ (compressed_bppx16 % 16 == 0))
+ continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -1705,6 +1708,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
+ if (intel_dp->force_dsc_fractional_bpp_en)
+ drm_dbg_kms(&dev_priv->drm,
+ "Forcing DSC fractional bpp\n");
if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */
forced_bpc > conn_state->max_requested_bpc ||
forced_bpp < limits->min_bpp ||
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev3)
2023-01-20 4:38 ` Ankit Nautiyal
` (16 preceding siblings ...)
(?)
@ 2023-01-20 4:59 ` Patchwork
-1 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-01-20 4:59 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: Add DSC fractional bpp support (rev3)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim checkpatch failed
4c1f4eda3734 drm/i915/dp: Remove extra logs for printing DSC info
5fdac8c73b98 drm/i915/dp: Avoid forcing DSC BPC for MST case
67d3aecb4f52 drm/i915/dp: Do not check for min DSC BPC for MST case
9fce7a5186e1 drm/i915/dp: Check if dsc forced bpc is in allowed limits
19e498682147 drm/i915/dp: Avoid left shift of DSC output bpp by 4
afa1e6124be1 drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp
1c9e08e5dc4f drm/i915/dp: Get optimal link config to have best compressed bpp
4bb31dc56a68 drm/i915/display: Store compressed bpp in U6.4 format
-:180: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#180: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1895:
+ dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
total: 0 errors, 1 warnings, 0 checks, 160 lines checked
69a94d0ddb34 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
27a394713abb drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
cf77d0489b00 drm/display/dp: Fix the DP DSC Receiver cap size
176deceafca5 drm/display/dp: Add helper function to get DSC bpp prescision
ebe209a1e436 drm/i915/dsc/mtl: Add support for fractional bpp
05cf5409e44f drm/i915/dp: Iterate over output bpp with fractional step size
377ddb88d9f2 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
7a84402a9872 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support (rev3)
2023-01-20 4:38 ` Ankit Nautiyal
` (17 preceding siblings ...)
(?)
@ 2023-01-20 5:13 ` Patchwork
-1 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-01-20 5:13 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4712 bytes --]
== Series Details ==
Series: Add DSC fractional bpp support (rev3)
URL : https://patchwork.freedesktop.org/series/111391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12615 -> Patchwork_111391v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_111391v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: [PASS][3] -> [FAIL][4] ([fdo#103375])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: [DMESG-WARN][5] ([i915#7625]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [DMESG-WARN][7] ([i915#7699]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/bat-dg2-11/igt@i915_selftest@live@migrate.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [FAIL][9] ([fdo#103375]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7625]: https://gitlab.freedesktop.org/drm/intel/issues/7625
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
Build changes
-------------
* Linux: CI_DRM_12615 -> Patchwork_111391v3
CI-20190529: 20190529
CI_DRM_12615: 8692eb28d41136537cd24aaf78f4621ddddbfb3a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7126: 3aa9364a1e478010aba0d3dfe9183486560ecc60 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111391v3: 8692eb28d41136537cd24aaf78f4621ddddbfb3a @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
69d3ef5591ba drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
8af821a5cec0 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
8dfc1eaa6110 drm/i915/dp: Iterate over output bpp with fractional step size
e323a84131c0 drm/i915/dsc/mtl: Add support for fractional bpp
4a58addd39f1 drm/display/dp: Add helper function to get DSC bpp prescision
8014c07f1262 drm/display/dp: Fix the DP DSC Receiver cap size
72bbe0162def drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
c0f8f97e2d70 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
559eb8e01d61 drm/i915/display: Store compressed bpp in U6.4 format
28418c255ac5 drm/i915/dp: Get optimal link config to have best compressed bpp
de1a7f9fccb7 drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp
e5bc2f5a281c drm/i915/dp: Avoid left shift of DSC output bpp by 4
97eabe595415 drm/i915/dp: Check if dsc forced bpc is in allowed limits
9c6d5fac3229 drm/i915/dp: Do not check for min DSC BPC for MST case
7c2f5eb0a8e5 drm/i915/dp: Avoid forcing DSC BPC for MST case
cb4569d96ef2 drm/i915/dp: Remove extra logs for printing DSC info
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/index.html
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^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Add DSC fractional bpp support (rev3)
2023-01-20 4:38 ` Ankit Nautiyal
` (18 preceding siblings ...)
(?)
@ 2023-01-20 23:16 ` Patchwork
-1 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-01-20 23:16 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 21997 bytes --]
== Series Details ==
Series: Add DSC fractional bpp support (rev3)
URL : https://patchwork.freedesktop.org/series/111391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12615_full -> Patchwork_111391v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/index.html
Participating hosts (12 -> 11)
------------------------------
Additional (1): shard-rkl0
Missing (2): pig-skl-6260u pig-kbl-iris
Known issues
------------
Here are the changes found in Patchwork_111391v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@random:
- shard-glk: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@gem_lmem_swapping@random.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3886]) +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2346])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271]) +77 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2:
- shard-glk: NOTRUN -> [FAIL][6] ([i915#4573]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#658]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@kms_psr2_su@page_flip-nv12.html
#### Possible fixes ####
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][8] ([i915#2582]) -> [PASS][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@fbdev@unaligned-read.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_bad_reloc@negative-reloc-lut:
- {shard-rkl}: [SKIP][10] ([i915#3281]) -> [PASS][11] +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][12] ([i915#2842]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_madvise@dontneed-before-pwrite:
- {shard-rkl}: [SKIP][14] ([i915#3282]) -> [PASS][15] +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-2/igt@gem_madvise@dontneed-before-pwrite.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-5/igt@gem_madvise@dontneed-before-pwrite.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][16] ([i915#5566] / [i915#716]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-glk8/igt@gen9_exec_parse@allowed-single.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-glk4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@shadow-peek:
- {shard-rkl}: [SKIP][18] ([i915#2527]) -> [PASS][19] +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][20] ([fdo#109308]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-4/igt@i915_pm_rpm@i2c.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- {shard-tglu}: [SKIP][22] ([i915#1845] / [i915#7651]) -> [PASS][23] +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-tglu-6/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-tglu-2/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
* igt@kms_dp_aux_dev:
- {shard-rkl}: [SKIP][24] ([i915#1257]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_dp_aux_dev.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_dp_aux_dev.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- {shard-rkl}: [SKIP][26] ([i915#1849] / [i915#4098]) -> [PASS][27] +18 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- {shard-tglu}: [SKIP][28] ([i915#1849]) -> [PASS][29] +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][30] ([i915#1849]) -> [PASS][31] +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@sprite_plane_onoff:
- {shard-rkl}: [SKIP][32] ([i915#1072]) -> [PASS][33] +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_psr@sprite_plane_onoff.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- {shard-rkl}: [SKIP][34] ([i915#5461]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@exhaust-fences:
- {shard-rkl}: [SKIP][36] ([i915#1845] / [i915#4098]) -> [PASS][37] +20 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_rotation_crc@exhaust-fences.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a:
- {shard-rkl}: [SKIP][38] ([i915#4070] / [i915#4098]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html
* igt@kms_universal_plane@universal-plane-pipe-b-sanity:
- {shard-rkl}: [SKIP][40] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
* igt@kms_vblank@pipe-c-query-forked-busy:
- {shard-tglu}: [SKIP][42] ([i915#7651]) -> [PASS][43] +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-tglu-6/igt@kms_vblank@pipe-c-query-forked-busy.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-tglu-2/igt@kms_vblank@pipe-c-query-forked-busy.html
* igt@perf@gen12-oa-tlb-invalidate:
- {shard-rkl}: [SKIP][44] ([fdo#109289]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-3/igt@perf@gen12-oa-tlb-invalidate.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][46] ([i915#2434]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-2/igt@perf@mi-rpc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-5/igt@perf@mi-rpc.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][48] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12615/shard-rkl-1/igt@prime_vgem@coherency-gtt.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12615 -> Patchwork_111391v3
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12615: 8692eb28d41136537cd24aaf78f4621ddddbfb3a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7126: 3aa9364a1e478010aba0d3dfe9183486560ecc60 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111391v3: 8692eb28d41136537cd24aaf78f4621ddddbfb3a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v3/index.html
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