From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Byron Lathi <bslathi19@gmail.com>,
peter.maydell@linaro.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: Re: [PATCH] Target/arm: Implement Cortex-A5
Date: Fri, 17 Dec 2021 18:12:12 +0000 [thread overview]
Message-ID: <8735mrdrqu.fsf@linaro.org> (raw)
In-Reply-To: <d0f649f7-4d5d-9b15-829c-d5cef2137797@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> On 12/13/21 1:02 PM, Alex Bennée wrote:
>>> + cpu->midr = 0x410fc0f1;
>> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f)
>> but
>> I can't find the actual value in the TRM.
>
> https://developer.arm.com/documentation/ddi0434/c
>
> has exactly this value at the top of table 4-9.
Ahh good find - 0x410FC051 it is.
>
>>> + cpu->reset_fpsid = 0x41023051;
>> I think for the a5 the FPU is optional so maybe we need a cpu option
>> here? Or maybe just assume it's enabled on QEMUs version?
>
> Yeah, there's no entry for fpsid in the above manual.
>
>>> + cpu->isar.id_mmfr0 = 0x00100103;
>> the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency
>> not supported.
>
> Again, this does match table 4-9.
0x00100003
>
>
> r~
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org, Byron Lathi <bslathi19@gmail.com>
Subject: Re: [PATCH] Target/arm: Implement Cortex-A5
Date: Fri, 17 Dec 2021 18:12:12 +0000 [thread overview]
Message-ID: <8735mrdrqu.fsf@linaro.org> (raw)
In-Reply-To: <d0f649f7-4d5d-9b15-829c-d5cef2137797@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> On 12/13/21 1:02 PM, Alex Bennée wrote:
>>> + cpu->midr = 0x410fc0f1;
>> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f)
>> but
>> I can't find the actual value in the TRM.
>
> https://developer.arm.com/documentation/ddi0434/c
>
> has exactly this value at the top of table 4-9.
Ahh good find - 0x410FC051 it is.
>
>>> + cpu->reset_fpsid = 0x41023051;
>> I think for the a5 the FPU is optional so maybe we need a cpu option
>> here? Or maybe just assume it's enabled on QEMUs version?
>
> Yeah, there's no entry for fpsid in the above manual.
>
>>> + cpu->isar.id_mmfr0 = 0x00100103;
>> the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency
>> not supported.
>
> Again, this does match table 4-9.
0x00100003
>
>
> r~
--
Alex Bennée
next prev parent reply other threads:[~2021-12-17 18:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-13 18:24 [PATCH] Target/arm: Implement Cortex-A5 Byron Lathi
2021-12-13 20:06 ` Philippe Mathieu-Daudé
2021-12-13 20:46 ` Richard Henderson
2021-12-13 21:02 ` Alex Bennée
2021-12-13 21:02 ` Alex Bennée
2021-12-13 21:46 ` Richard Henderson
2021-12-13 22:34 ` Byron Lathi
2021-12-13 22:34 ` Byron Lathi
2021-12-17 18:12 ` Alex Bennée [this message]
2021-12-17 18:12 ` Alex Bennée
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