[PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Stanislav Lisovskiy]

Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.

We could not come up with any better solution
yet, as PLL divider values both for MIPI(DSI PLL) and
CDCLK(DE PLL) are correct, however seems that due to some
boundary conditions, when clocking is too low we get
wrong timings for DSI display.
Similar workaround exists for VLV though, so just
took similar condition into use. At least that way
GLK platform will start to be usable again, with
current drm-tip.

v2: Fixed commit subject as suggested.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ae40a8679314..2b23f8500362 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	    IS_VALLEYVIEW(dev_priv))
 		min_cdclk = max(320000, min_cdclk);
 
+	/*
+	 * On Geminilake once the CDCLK gets as low as 79200
+	 * picture gets unstable, despite that values are
+	 * correct for DSI PLL and DE PLL.
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    IS_GEMINILAKE(dev_priv))
+		min_cdclk = max(158400, min_cdclk);
+
 	if (min_cdclk > dev_priv->max_cdclk_freq) {
 		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
 			      min_cdclk, dev_priv->max_cdclk_freq);
-- 
2.17.1

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Re: [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Jani Nikula]

On Tue, 30 Apr 2019, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> Currently due to regression CI machine
> displays show corrupt picture.
> Problem is when CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
> We could not come up with any better solution
> yet, as PLL divider values both for MIPI(DSI PLL) and
> CDCLK(DE PLL) are correct, however seems that due to some
> boundary conditions, when clocking is too low we get
> wrong timings for DSI display.
> Similar workaround exists for VLV though, so just
> took similar condition into use. At least that way
> GLK platform will start to be usable again, with
> current drm-tip.
>
> v2: Fixed commit subject as suggested.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Do we have a bugzilla link?

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ae40a8679314..2b23f8500362 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	    IS_VALLEYVIEW(dev_priv))
>  		min_cdclk = max(320000, min_cdclk);
>  
> +	/*
> +	 * On Geminilake once the CDCLK gets as low as 79200
> +	 * picture gets unstable, despite that values are
> +	 * correct for DSI PLL and DE PLL.
> +	 */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> +	    IS_GEMINILAKE(dev_priv))
> +		min_cdclk = max(158400, min_cdclk);
> +
>  	if (min_cdclk > dev_priv->max_cdclk_freq) {
>  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
>  			      min_cdclk, dev_priv->max_cdclk_freq);

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Lisovskiy, Stanislav]

On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2019, Stanislav Lisovskiy <
> stanislav.lisovskiy@intel.com> wrote:
> > Currently due to regression CI machine
> > displays show corrupt picture.
> > Problem is when CDCLK is as low as 79200, picture gets
> > unstable, while DSI and DE pll values were
> > confirmed to be correct.
> > Limiting to 158400 as agreed with Ville.
> > 
> > We could not come up with any better solution
> > yet, as PLL divider values both for MIPI(DSI PLL) and
> > CDCLK(DE PLL) are correct, however seems that due to some
> > boundary conditions, when clocking is too low we get
> > wrong timings for DSI display.
> > Similar workaround exists for VLV though, so just
> > took similar condition into use. At least that way
> > GLK platform will start to be usable again, with
> > current drm-tip.
> > 
> > v2: Fixed commit subject as suggested.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Do we have a bugzilla link?
> 
> BR,
> Jani.

No, or at least I'm not aware of. I just got a machine from CI for
investigation :) I guess it might be worth to create a bug for that.


Martin: do we have a bug for CI GLK issue?

-Stanislav

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index ae40a8679314..2b23f8500362 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const
> > struct intel_crtc_state *crtc_state)
> >  	    IS_VALLEYVIEW(dev_priv))
> >  		min_cdclk = max(320000, min_cdclk);
> >  
> > +	/*
> > +	 * On Geminilake once the CDCLK gets as low as 79200
> > +	 * picture gets unstable, despite that values are
> > +	 * correct for DSI PLL and DE PLL.
> > +	 */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > +	    IS_GEMINILAKE(dev_priv))
> > +		min_cdclk = max(158400, min_cdclk);
> > +
> >  	if (min_cdclk > dev_priv->max_cdclk_freq) {
> >  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d
> > kHz)\n",
> >  			      min_cdclk, dev_priv->max_cdclk_freq);
> 
> 
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Re: [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Peres, Martin]

On 30/04/2019 11:01, Lisovskiy, Stanislav wrote:
> On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
>> On Tue, 30 Apr 2019, Stanislav Lisovskiy <
>> stanislav.lisovskiy@intel.com> wrote:
>>> Currently due to regression CI machine
>>> displays show corrupt picture.
>>> Problem is when CDCLK is as low as 79200, picture gets
>>> unstable, while DSI and DE pll values were
>>> confirmed to be correct.
>>> Limiting to 158400 as agreed with Ville.
>>>
>>> We could not come up with any better solution
>>> yet, as PLL divider values both for MIPI(DSI PLL) and
>>> CDCLK(DE PLL) are correct, however seems that due to some
>>> boundary conditions, when clocking is too low we get
>>> wrong timings for DSI display.
>>> Similar workaround exists for VLV though, so just
>>> took similar condition into use. At least that way
>>> GLK platform will start to be usable again, with
>>> current drm-tip.
>>>
>>> v2: Fixed commit subject as suggested.
>>>
>>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Do we have a bugzilla link?
>>
>> BR,
>> Jani.
> 
> No, or at least I'm not aware of. I just got a machine from CI for
> investigation :) I guess it might be worth to create a bug for that.
> 
> 
> Martin: do we have a bug for CI GLK issue?

No idea. Check it out:
http://gfx-ci.fi.intel.com/cibuglog-ng/results/knownfailures?query=machine_name+%3D+%27fi-glk-dsi%27+AND+NOT+status_name+%3D+%27skip%27

This possibly could explain all the CRC mismatches we get on GLK-dsi?
Time will tell.

Martin

> 
> -Stanislav
> 
>>
>>
>>> ---
>>>  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>>> b/drivers/gpu/drm/i915/intel_cdclk.c
>>> index ae40a8679314..2b23f8500362 100644
>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>> @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const
>>> struct intel_crtc_state *crtc_state)
>>>  	    IS_VALLEYVIEW(dev_priv))
>>>  		min_cdclk = max(320000, min_cdclk);
>>>  
>>> +	/*
>>> +	 * On Geminilake once the CDCLK gets as low as 79200
>>> +	 * picture gets unstable, despite that values are
>>> +	 * correct for DSI PLL and DE PLL.
>>> +	 */
>>> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>>> +	    IS_GEMINILAKE(dev_priv))
>>> +		min_cdclk = max(158400, min_cdclk);
>>> +
>>>  	if (min_cdclk > dev_priv->max_cdclk_freq) {
>>>  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d
>>> kHz)\n",
>>>  			      min_cdclk, dev_priv->max_cdclk_freq);
>>
>>
> 

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Re: [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Saarinen, Jani]

HI, 
> -----Original Message-----
> From: Lisovskiy, Stanislav
> Sent: tiistai 30. huhtikuuta 2019 11.01
> To: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com
> Cc: Saarinen, Jani <jani.saarinen@intel.com>; Peres, Martin
> <martin.peres@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake
> 
> On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
> > On Tue, 30 Apr 2019, Stanislav Lisovskiy <
> > stanislav.lisovskiy@intel.com> wrote:
> > > Currently due to regression CI machine displays show corrupt
> > > picture.
> > > Problem is when CDCLK is as low as 79200, picture gets unstable,
> > > while DSI and DE pll values were confirmed to be correct.
> > > Limiting to 158400 as agreed with Ville.
> > >
> > > We could not come up with any better solution yet, as PLL divider
> > > values both for MIPI(DSI PLL) and CDCLK(DE PLL) are correct, however
> > > seems that due to some boundary conditions, when clocking is too low
> > > we get wrong timings for DSI display.
> > > Similar workaround exists for VLV though, so just took similar
> > > condition into use. At least that way GLK platform will start to be
> > > usable again, with current drm-tip.
> > >
> > > v2: Fixed commit subject as suggested.
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Do we have a bugzilla link?
> >
> > BR,
> > Jani.
> 
> No, or at least I'm not aware of. I just got a machine from CI for investigation :) I
> guess it might be worth to create a bug for that.
> 
> 
> Martin: do we have a bug for CI GLK issue?
We did had some bugs, but not sure if those are related to this issue. 

> 
> -Stanislav
> 
> >
> >
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index ae40a8679314..2b23f8500362 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const
> > > struct intel_crtc_state *crtc_state)
> > >  	    IS_VALLEYVIEW(dev_priv))
> > >  		min_cdclk = max(320000, min_cdclk);
> > >
> > > +	/*
> > > +	 * On Geminilake once the CDCLK gets as low as 79200
> > > +	 * picture gets unstable, despite that values are
> > > +	 * correct for DSI PLL and DE PLL.
> > > +	 */
> > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > > +	    IS_GEMINILAKE(dev_priv))
> > > +		min_cdclk = max(158400, min_cdclk);
> > > +
> > >  	if (min_cdclk > dev_priv->max_cdclk_freq) {
> > >  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d
> kHz)\n",
> > >  			      min_cdclk, dev_priv->max_cdclk_freq);
> >
> >
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✗ Fi.CI.SPARSE: warning for drm/i915: Corrupt DSI picture fix for GeminiLake

[Patchwork]

== Series Details ==

Series: drm/i915: Corrupt DSI picture fix for GeminiLake
URL   : https://patchwork.freedesktop.org/series/60084/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Corrupt DSI picture fix for GeminiLake
-O:drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2275:29: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915: Corrupt DSI picture fix for GeminiLake

[Patchwork]

== Series Details ==

Series: drm/i915: Corrupt DSI picture fix for GeminiLake
URL   : https://patchwork.freedesktop.org/series/60084/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12902
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/60084/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12902 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live_contexts:
    - fi-skl-gvtdvm:      [PASS][3] -> [DMESG-FAIL][4] ([fdo#110235])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-y:           [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-icl-y/igt@gem_ctx_create@basic-files.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-icl-y/igt@gem_ctx_create@basic-files.html

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       [INCOMPLETE][7] ([fdo#108602] / [fdo#108744]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html

  
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235


Participating hosts (51 -> 42)
------------------------------

  Additional (1): fi-skl-guc 
  Missing    (10): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6014 -> Patchwork_12902

  CI_DRM_6014: b5b621db8397c5c726f5493095682f14d295429d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12902: 15f80f2efc96d825897faef3fb6ff532f8617aba @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

15f80f2efc96 drm/i915: Corrupt DSI picture fix for GeminiLake

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/
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