From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock
Date: Wed, 10 Apr 2019 11:09:47 +0300 [thread overview]
Message-ID: <8736mq46yc.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <155482686335.26510.14129836201457118845@skylake-alporthouse-com>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:09)
>> Unlike previous gens, we already hold the irq_lock on
>> entering the rps handler so we can't use it as it is.
>>
>> Make a gen11 specific rps interrupt handler without
>> locking.
>>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 6454ddc37f8b..619e6ab273e7 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1796,6 +1796,22 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>> /* The RPS events need forcewake, so we add them to a work queue and mask their
>> * IMR bits until the work is done. Other interrupts can be processed without
>> * the work queue. */
>> +static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
>> +{
>> + struct intel_rps *rps = &i915->gt_pm.rps;
>> + const u32 events = i915->pm_rps_events & pm_iir;
>> +
>> + lockdep_assert_held(&i915->irq_lock);
>> +
>> + if (events) {
>
> if (!events)
> return;
> ?
> Maybe you have reason for the indent later.
No reasons. I am avid fan of early return. This was explained by
copypasta from gen6 variant and then some interrupt event masked
between my ears. will send v2
>
>> + gen6_mask_pm_irq(i915, events);
>> + if (rps->interrupts_enabled) {
>> + rps->pm_iir |= events;
>> + schedule_work(&rps->work);
>> + }
>> + }
>
> All I can say is that this is evidence that we've never had an rps
> interrupt!
>
> I guess this patch needs to be first just in case an interrupt is
> sent.
Yeah, when got first ever sent, I witnessed spectacular fireworks.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Ta,
-Mika
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next prev parent reply other threads:[~2019-04-10 8:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
2019-04-09 16:51 ` Michal Wajdeczko
2019-04-09 16:13 ` [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis Mika Kuoppala
2019-04-09 16:16 ` Chris Wilson
2019-04-10 8:04 ` Mika Kuoppala
2019-04-09 16:13 ` [PATCH 4/7] drm/i915/icl: Enable media sampler powergate Mika Kuoppala
2019-04-09 16:34 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control Mika Kuoppala
2019-04-09 16:32 ` Chris Wilson
2019-04-10 8:05 ` Mika Kuoppala
2019-04-09 16:13 ` [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock Mika Kuoppala
2019-04-09 16:21 ` Chris Wilson
2019-04-10 8:09 ` Mika Kuoppala [this message]
2019-04-09 16:13 ` [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts Mika Kuoppala
2019-04-09 16:26 ` Chris Wilson
2019-04-10 8:20 ` Mika Kuoppala
2019-04-09 16:28 ` [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Chris Wilson
2019-04-09 16:57 ` Michal Wajdeczko
2019-04-09 17:04 ` Chris Wilson
2019-04-09 17:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2019-04-09 17:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-10 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-10 9:04 ` Chris Wilson
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