[PATCH 0/9] add more devicetree support in arch-mmp

[PATCH 0/9] add more devicetree support in arch-mmp

[Haojian Zhuang]

1. Fix the build issue in mmp-dt.c since irq interface changed.
2. Parse intc in new irq that could support both pxa168 and mmp2.
After arch-mmp is totally moved to device tree, irq-pxa168 and irq-mmp2
will be removed.
3. Parse interrupt in gpio controller.
4. Append timer with device tree.
5. Update documents.

[PATCH 0/9] add more devicetree support in arch-mmp

[Haojian Zhuang]

1. Fix the build issue in mmp-dt.c since irq interface changed.
2. Parse intc in new irq that could support both pxa168 and mmp2.
After arch-mmp is totally moved to device tree, irq-pxa168 and irq-mmp2
will be removed.
3. Parse interrupt in gpio controller.
4. Append timer with device tree.
5. Update documents.

[PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Haojian Zhuang]

Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/mach-mmp/mmp-dt.c |   22 ----------------------
 1 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 6707539..ca22e3c0 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
 	{}
 };
 
-static int __init mmp_intc_add_irq_domain(struct device_node *np,
-					   struct device_node *parent)
-{
-	irq_domain_add_simple(np, 0);
-	return 0;
-}
-
-static int __init mmp_gpio_add_irq_domain(struct device_node *np,
-					   struct device_node *parent)
-{
-	irq_domain_add_simple(np, IRQ_GPIO_START);
-	return 0;
-}
-
-static const struct of_device_id mmp_irq_match[] __initconst = {
-	{ .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
-	{ .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
-	{}
-};
-
 static void __init mmp_dt_init(void)
 {
 
-	of_irq_init(mmp_irq_match);
-
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     mmp_auxdata_lookup, NULL);
 }
-- 
1.7.5.4

[PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Haojian Zhuang]

Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-mmp/mmp-dt.c |   22 ----------------------
 1 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 6707539..ca22e3c0 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
 	{}
 };
 
-static int __init mmp_intc_add_irq_domain(struct device_node *np,
-					   struct device_node *parent)
-{
-	irq_domain_add_simple(np, 0);
-	return 0;
-}
-
-static int __init mmp_gpio_add_irq_domain(struct device_node *np,
-					   struct device_node *parent)
-{
-	irq_domain_add_simple(np, IRQ_GPIO_START);
-	return 0;
-}
-
-static const struct of_device_id mmp_irq_match[] __initconst = {
-	{ .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
-	{ .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
-	{}
-};
-
 static void __init mmp_dt_init(void)
 {
 
-	of_irq_init(mmp_irq_match);
-
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     mmp_auxdata_lookup, NULL);
 }
-- 
1.7.5.4

[PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Arnd Bergmann]

On Friday 27 April 2012, Haojian Zhuang wrote:
> Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>

This should also be fixed for v3.4, right?


> diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
> index 6707539..ca22e3c0 100644
> --- a/arch/arm/mach-mmp/mmp-dt.c
> +++ b/arch/arm/mach-mmp/mmp-dt.c
> @@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
>         {}
>  };
>  
> -static int __init mmp_intc_add_irq_domain(struct device_node *np,
> -                                          struct device_node *parent)
> -{
> -       irq_domain_add_simple(np, 0);
> -       return 0;
> -}
> -
> -static int __init mmp_gpio_add_irq_domain(struct device_node *np,
> -                                          struct device_node *parent)
> -{
> -       irq_domain_add_simple(np, IRQ_GPIO_START);
> -       return 0;
> -}
> -
> -static const struct of_device_id mmp_irq_match[] __initconst = {
> -       { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
> -       { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
> -       {}
> -};
> -
>  static void __init mmp_dt_init(void)
>  {
>  
> -       of_irq_init(mmp_irq_match);
> -
>         of_platform_populate(NULL, of_default_bus_match_table,
>                              mmp_auxdata_lookup, NULL);
>  }

Shouldn't you be calling irq_domain_add_legacy now?

	Arnd

Re: [PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Arnd Bergmann]

On Friday 27 April 2012, Haojian Zhuang wrote:
> Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

This should also be fixed for v3.4, right?


> diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
> index 6707539..ca22e3c0 100644
> --- a/arch/arm/mach-mmp/mmp-dt.c
> +++ b/arch/arm/mach-mmp/mmp-dt.c
> @@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
>         {}
>  };
>  
> -static int __init mmp_intc_add_irq_domain(struct device_node *np,
> -                                          struct device_node *parent)
> -{
> -       irq_domain_add_simple(np, 0);
> -       return 0;
> -}
> -
> -static int __init mmp_gpio_add_irq_domain(struct device_node *np,
> -                                          struct device_node *parent)
> -{
> -       irq_domain_add_simple(np, IRQ_GPIO_START);
> -       return 0;
> -}
> -
> -static const struct of_device_id mmp_irq_match[] __initconst = {
> -       { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
> -       { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
> -       {}
> -};
> -
>  static void __init mmp_dt_init(void)
>  {
>  
> -       of_irq_init(mmp_irq_match);
> -
>         of_platform_populate(NULL, of_default_bus_match_table,
>                              mmp_auxdata_lookup, NULL);
>  }

Shouldn't you be calling irq_domain_add_legacy now?

	Arnd

[PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 4:15 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday 27 April 2012, Haojian Zhuang wrote:
>> Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
>
> This should also be fixed for v3.4, right?
>
Since I have more code updated in irq, I update them together to avoid
dependency issue.
>
>> diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
>> index 6707539..ca22e3c0 100644
>> --- a/arch/arm/mach-mmp/mmp-dt.c
>> +++ b/arch/arm/mach-mmp/mmp-dt.c
>> @@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
>> ? ? ? ? {}
>> ?};
>>
>> -static int __init mmp_intc_add_irq_domain(struct device_node *np,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct device_node *parent)
>> -{
>> - ? ? ? irq_domain_add_simple(np, 0);
>> - ? ? ? return 0;
>> -}
>> -
>> -static int __init mmp_gpio_add_irq_domain(struct device_node *np,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct device_node *parent)
>> -{
>> - ? ? ? irq_domain_add_simple(np, IRQ_GPIO_START);
>> - ? ? ? return 0;
>> -}
>> -
>> -static const struct of_device_id mmp_irq_match[] __initconst = {
>> - ? ? ? { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
>> - ? ? ? { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
>> - ? ? ? {}
>> -};
>> -
>> ?static void __init mmp_dt_init(void)
>> ?{
>>
>> - ? ? ? of_irq_init(mmp_irq_match);
>> -
>> ? ? ? ? of_platform_populate(NULL, of_default_bus_match_table,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?mmp_auxdata_lookup, NULL);
>> ?}
>
> Shouldn't you be calling irq_domain_add_legacy now?
>
irq_domain_add_legacy() is used in irq.c. It's in another patch in this series.

Re: [PATCH 1/9] ARM: mmp: fix build issue on mmp with device tree

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 4:15 AM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Friday 27 April 2012, Haojian Zhuang wrote:
>> Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> This should also be fixed for v3.4, right?
>
Since I have more code updated in irq, I update them together to avoid
dependency issue.
>
>> diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
>> index 6707539..ca22e3c0 100644
>> --- a/arch/arm/mach-mmp/mmp-dt.c
>> +++ b/arch/arm/mach-mmp/mmp-dt.c
>> @@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
>>         {}
>>  };
>>
>> -static int __init mmp_intc_add_irq_domain(struct device_node *np,
>> -                                          struct device_node *parent)
>> -{
>> -       irq_domain_add_simple(np, 0);
>> -       return 0;
>> -}
>> -
>> -static int __init mmp_gpio_add_irq_domain(struct device_node *np,
>> -                                          struct device_node *parent)
>> -{
>> -       irq_domain_add_simple(np, IRQ_GPIO_START);
>> -       return 0;
>> -}
>> -
>> -static const struct of_device_id mmp_irq_match[] __initconst = {
>> -       { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
>> -       { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
>> -       {}
>> -};
>> -
>>  static void __init mmp_dt_init(void)
>>  {
>>
>> -       of_irq_init(mmp_irq_match);
>> -
>>         of_platform_populate(NULL, of_default_bus_match_table,
>>                              mmp_auxdata_lookup, NULL);
>>  }
>
> Shouldn't you be calling irq_domain_add_legacy now?
>
irq_domain_add_legacy() is used in irq.c. It's in another patch in this series.

[PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Haojian Zhuang]

Append four CONFIG_* MACRO to distinguish boards in arch-mmp.

CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
without device tree.

CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
device tree.

At the same time, only one of these four macro could be selected.
It's used to miss compiling all boards file together.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/configs/mmp2_defconfig   |    1 +
 arch/arm/configs/pxa168_defconfig |    1 +
 arch/arm/configs/pxa910_defconfig |    1 +
 arch/arm/mach-mmp/Kconfig         |   37 ++++++++++++++++++++++++++++++++++---
 4 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a58452..8c309d1 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP2_LEGACY=y
 CONFIG_MACH_BROWNSTONE=y
 CONFIG_MACH_FLINT=y
 CONFIG_MACH_MARVELL_JASPER=y
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
index 74d7e01..2abaa9f 100644
--- a/arch/arm/configs/pxa168_defconfig
+++ b/arch/arm/configs/pxa168_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP_LEGACY=y
 CONFIG_MACH_ASPENITE=y
 CONFIG_MACH_ZYLONITE2=y
 CONFIG_MACH_AVENGERS_LITE=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e..1e95263 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP_LEGACY=y
 CONFIG_MACH_TAVOREVB=y
 CONFIG_MACH_TTC_DKB=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a..5d49913 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,9 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+choice
+	prompt "Support Machines for MMP series"
+
 config MACH_MMP_DT
 	bool "Support MMP2 platforms from device tree"
 	select CPU_PXA168
@@ -12,8 +15,30 @@ config MACH_MMP_DT
 	  the device tree. Needn't select any other machine while
 	  MACH_MMP_DT is enabled.
 
+config MACH_MMP2_DT
+	bool "Support MMP2 platforms from device tree"
+	select CPU_MMP2
+	select USE_OF
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree.
+
+config MMP_LEGACY
+	bool "Support MMP platform without device tree"
+	help
+	  Include support for Marvell MMP based platforms in legacy
+	  mode without device tree.
+
+config MMP2_LEGACY
+	bool "Support MMP2 platform without device tree"
+	help
+	  Include support for Marvell MMP2 based platforms in legacy
+	  mode without device tree.
+endchoice
+
 config MACH_ASPENITE
 	bool "Marvell's PXA168 Aspenite Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -21,6 +46,7 @@ config MACH_ASPENITE
 
 config MACH_ZYLONITE2
 	bool "Marvell's PXA168 Zylonite2 Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -28,6 +54,7 @@ config MACH_ZYLONITE2
 
 config MACH_AVENGERS_LITE
 	bool "Marvell's PXA168 Avengers Lite Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -35,6 +62,7 @@ config MACH_AVENGERS_LITE
 
 config MACH_TAVOREVB
 	bool "Marvell's PXA910 TavorEVB Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA910
 	help
 	  Say 'Y' here if you want to support the Marvell PXA910-based
@@ -42,6 +70,7 @@ config MACH_TAVOREVB
 
 config MACH_TTC_DKB
 	bool "Marvell's PXA910 TavorEVB Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA910
 	help
 	  Say 'Y' here if you want to support the Marvell PXA910-based
@@ -49,7 +78,7 @@ config MACH_TTC_DKB
 
 config MACH_BROWNSTONE
 	bool "Marvell's Brownstone Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-based
@@ -60,7 +89,7 @@ config MACH_BROWNSTONE
 
 config MACH_FLINT
 	bool "Marvell's Flint Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-based
@@ -71,7 +100,7 @@ config MACH_FLINT
 
 config MACH_MARVELL_JASPER
 	bool "Marvell's Jasper Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-base
@@ -82,6 +111,7 @@ config MACH_MARVELL_JASPER
 
 config MACH_TETON_BGA
 	bool "Marvell's PXA168 Teton BGA Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -89,6 +119,7 @@ config MACH_TETON_BGA
 
 config MACH_GPLUGD
 	bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
-- 
1.7.5.4

[PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Haojian Zhuang]

Append four CONFIG_* MACRO to distinguish boards in arch-mmp.

CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
without device tree.

CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
device tree.

At the same time, only one of these four macro could be selected.
It's used to miss compiling all boards file together.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/configs/mmp2_defconfig   |    1 +
 arch/arm/configs/pxa168_defconfig |    1 +
 arch/arm/configs/pxa910_defconfig |    1 +
 arch/arm/mach-mmp/Kconfig         |   37 ++++++++++++++++++++++++++++++++++---
 4 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a58452..8c309d1 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP2_LEGACY=y
 CONFIG_MACH_BROWNSTONE=y
 CONFIG_MACH_FLINT=y
 CONFIG_MACH_MARVELL_JASPER=y
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
index 74d7e01..2abaa9f 100644
--- a/arch/arm/configs/pxa168_defconfig
+++ b/arch/arm/configs/pxa168_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP_LEGACY=y
 CONFIG_MACH_ASPENITE=y
 CONFIG_MACH_ZYLONITE2=y
 CONFIG_MACH_AVENGERS_LITE=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e..1e95263 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MMP_LEGACY=y
 CONFIG_MACH_TAVOREVB=y
 CONFIG_MACH_TTC_DKB=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a..5d49913 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,9 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+choice
+	prompt "Support Machines for MMP series"
+
 config MACH_MMP_DT
 	bool "Support MMP2 platforms from device tree"
 	select CPU_PXA168
@@ -12,8 +15,30 @@ config MACH_MMP_DT
 	  the device tree. Needn't select any other machine while
 	  MACH_MMP_DT is enabled.
 
+config MACH_MMP2_DT
+	bool "Support MMP2 platforms from device tree"
+	select CPU_MMP2
+	select USE_OF
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree.
+
+config MMP_LEGACY
+	bool "Support MMP platform without device tree"
+	help
+	  Include support for Marvell MMP based platforms in legacy
+	  mode without device tree.
+
+config MMP2_LEGACY
+	bool "Support MMP2 platform without device tree"
+	help
+	  Include support for Marvell MMP2 based platforms in legacy
+	  mode without device tree.
+endchoice
+
 config MACH_ASPENITE
 	bool "Marvell's PXA168 Aspenite Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -21,6 +46,7 @@ config MACH_ASPENITE
 
 config MACH_ZYLONITE2
 	bool "Marvell's PXA168 Zylonite2 Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -28,6 +54,7 @@ config MACH_ZYLONITE2
 
 config MACH_AVENGERS_LITE
 	bool "Marvell's PXA168 Avengers Lite Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -35,6 +62,7 @@ config MACH_AVENGERS_LITE
 
 config MACH_TAVOREVB
 	bool "Marvell's PXA910 TavorEVB Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA910
 	help
 	  Say 'Y' here if you want to support the Marvell PXA910-based
@@ -42,6 +70,7 @@ config MACH_TAVOREVB
 
 config MACH_TTC_DKB
 	bool "Marvell's PXA910 TavorEVB Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA910
 	help
 	  Say 'Y' here if you want to support the Marvell PXA910-based
@@ -49,7 +78,7 @@ config MACH_TTC_DKB
 
 config MACH_BROWNSTONE
 	bool "Marvell's Brownstone Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-based
@@ -60,7 +89,7 @@ config MACH_BROWNSTONE
 
 config MACH_FLINT
 	bool "Marvell's Flint Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-based
@@ -71,7 +100,7 @@ config MACH_FLINT
 
 config MACH_MARVELL_JASPER
 	bool "Marvell's Jasper Development Platform"
-	depends on !CPU_MOHAWK
+	depends on MMP2_LEGACY && !CPU_MOHAWK
 	select CPU_MMP2
 	help
 	  Say 'Y' here if you want to support the Marvell MMP2-base
@@ -82,6 +111,7 @@ config MACH_MARVELL_JASPER
 
 config MACH_TETON_BGA
 	bool "Marvell's PXA168 Teton BGA Development Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
@@ -89,6 +119,7 @@ config MACH_TETON_BGA
 
 config MACH_GPLUGD
 	bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
+	depends on MMP_LEGACY
 	select CPU_PXA168
 	help
 	  Say 'Y' here if you want to support the Marvell PXA168-based
-- 
1.7.5.4

[PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Arnd Bergmann]

On Friday 27 April 2012, Haojian Zhuang wrote:
> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
> 
> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
> without device tree.
> 
> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
> device tree.
> 
> At the same time, only one of these four macro could be selected.
> It's used to miss compiling all boards file together.

Can you explain why this is done? It seems counterintuitive to
have the DT and non-DT support be mutually exclusive.

	Arnd

Re: [PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Arnd Bergmann]

On Friday 27 April 2012, Haojian Zhuang wrote:
> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
> 
> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
> without device tree.
> 
> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
> device tree.
> 
> At the same time, only one of these four macro could be selected.
> It's used to miss compiling all boards file together.

Can you explain why this is done? It seems counterintuitive to
have the DT and non-DT support be mutually exclusive.

	Arnd

[PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 4:14 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday 27 April 2012, Haojian Zhuang wrote:
>> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
>>
>> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
>> without device tree.
>>
>> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
>> device tree.
>>
>> At the same time, only one of these four macro could be selected.
>> It's used to miss compiling all boards file together.
>
> Can you explain why this is done? It seems counterintuitive to
> have the DT and non-DT support be mutually exclusive.
>
If I selected DT support, I needn't select those machine support one
by one. I want to use
mmp-dt to support all PXA168/PXA910 boards, and use mmp2-dt to support
all mmp2 boards.
So I use exclusive statements in Kconfig for convenience.

Thanks
Haojian

Re: [PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 4:14 AM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Friday 27 April 2012, Haojian Zhuang wrote:
>> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
>>
>> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
>> without device tree.
>>
>> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
>> device tree.
>>
>> At the same time, only one of these four macro could be selected.
>> It's used to miss compiling all boards file together.
>
> Can you explain why this is done? It seems counterintuitive to
> have the DT and non-DT support be mutually exclusive.
>
If I selected DT support, I needn't select those machine support one
by one. I want to use
mmp-dt to support all PXA168/PXA910 boards, and use mmp2-dt to support
all mmp2 boards.
So I use exclusive statements in Kconfig for convenience.

Thanks
Haojian

[PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Arnd Bergmann]

On Wednesday 02 May 2012, Haojian Zhuang wrote:
> On Sat, Apr 28, 2012 at 4:14 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Friday 27 April 2012, Haojian Zhuang wrote:
> >> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
> >>
> >> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
> >> without device tree.
> >>
> >> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
> >> device tree.
> >>
> >> At the same time, only one of these four macro could be selected.
> >> It's used to miss compiling all boards file together.
> >
> > Can you explain why this is done? It seems counterintuitive to
> > have the DT and non-DT support be mutually exclusive.
> >
> If I selected DT support, I needn't select those machine support one
> by one. I want to use
> mmp-dt to support all PXA168/PXA910 boards, and use mmp2-dt to support
> all mmp2 boards.
> So I use exclusive statements in Kconfig for convenience.

Everyone else who is adding DT support does it so that one can boot
the same kernel using ATAG or DT mode, to allow testing in direct
comparison for the transitional period. Further, you can currently
build a single kernel that supports all board files including DT
support, with this patch you have to build two separate kernels,
which I consider a regression.

I guess this would be ok if you plan to remove the non-DT board files
from mach-mmp soon (e.g. v3.6) and only support DT booting, providing
the same feature set as today with the board files. If you think you
need longer than that, I would prefer if you make the two options
coexist in the kernel.

	Arnd

Re: [PATCH 2/9] ARM: mmp: distinguish mmp and mmp2 in Kconfig

[Arnd Bergmann]

On Wednesday 02 May 2012, Haojian Zhuang wrote:
> On Sat, Apr 28, 2012 at 4:14 AM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> > On Friday 27 April 2012, Haojian Zhuang wrote:
> >> Append four CONFIG_* MACRO to distinguish boards in arch-mmp.
> >>
> >> CONFIG_MMP_LEGACY and CONFIG_MMP2_LEGACY are used to support boards
> >> without device tree.
> >>
> >> CONFIG_MMP_DT and CONFIG_MMP2_DT are used to support boards with
> >> device tree.
> >>
> >> At the same time, only one of these four macro could be selected.
> >> It's used to miss compiling all boards file together.
> >
> > Can you explain why this is done? It seems counterintuitive to
> > have the DT and non-DT support be mutually exclusive.
> >
> If I selected DT support, I needn't select those machine support one
> by one. I want to use
> mmp-dt to support all PXA168/PXA910 boards, and use mmp2-dt to support
> all mmp2 boards.
> So I use exclusive statements in Kconfig for convenience.

Everyone else who is adding DT support does it so that one can boot
the same kernel using ATAG or DT mode, to allow testing in direct
comparison for the transitional period. Further, you can currently
build a single kernel that supports all board files including DT
support, with this patch you have to build two separate kernels,
which I consider a regression.

I guess this would be ok if you plan to remove the non-DT board files
from mach-mmp soon (e.g. v3.6) and only support DT booting, providing
the same feature set as today with the board files. If you think you
need longer than that, I would prefer if you make the two options
coexist in the kernel.

	Arnd

[PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

Append new interrupt driver that could support both pxa168 and mmp2
silicon. And this driver supports device tree.

Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
handle reserved NR_IRQS_LEGACY in irq domain.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/mach-mmp/Makefile                   |    2 +-
 arch/arm/mach-mmp/include/mach/entry-macro.S |    9 +
 arch/arm/mach-mmp/irq.c                      |  287 ++++++++++++++++++++++++++
 3 files changed, 297 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mmp/irq.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4fc0ff5..4e73a15 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,6 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
-obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
+obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o irq.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 9cff9e7..6b9d925 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -6,13 +6,19 @@
  * published by the Free Software Foundation.
  */
 
+#include <asm/irq.h>
 #include <mach/regs-icu.h>
 
 	.macro	get_irqnr_preamble, base, tmp
 	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
 	and	\tmp, \tmp, #0xff00
 	cmp	\tmp, #0x5800
+#ifdef CONFIG_OF
+	ldr	\base, =mmp_icu_base
+	ldr	\base, [\base, #0]
+#else
 	ldr	\base, =ICU_VIRT_BASE
+#endif
 	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register
 	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register
 	.endm
@@ -20,5 +26,8 @@
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	ldr	\tmp, [\base, #0]
 	and	\irqnr, \tmp, #0x3f
+#ifdef CONFIG_OF
+	add	\irqnr, \irqnr, #NR_IRQS_LEGACY
+#endif
 	tst	\tmp, #(1 << 6)
 	.endm
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 0000000..8d0890f
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,287 @@
+/*
+ *  linux/arch/arm/mach-mmp/irq.c
+ *
+ *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
+ *
+ *  Author:	Bin Yang <bin.yang@marvell.com>
+ *              Haojian Zhuang <haojian.zhuang@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "common.h"
+
+#define MAX_ICU_NR		16
+
+struct icu_chip_data {
+	int			nr_irqs;
+	unsigned int		virq_base;
+	unsigned int		cascade_irq;
+	void __iomem		*reg_status;
+	void __iomem		*reg_mask;
+	unsigned int		conf_enable;
+	unsigned int		conf_disable;
+	unsigned int		conf_mask;
+	struct irq_domain	*domain;
+};
+
+struct mmp_intc_conf {
+	unsigned int	conf_enable;
+	unsigned int	conf_disable;
+	unsigned int	conf_mask;
+};
+
+void __iomem *mmp_icu_base;
+static struct icu_chip_data icu_data[MAX_ICU_NR];
+static int max_icu_nr;
+
+static void icu_mask_irq(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+	int hwirq;
+	u32 r;
+
+	hwirq = d->irq - data->virq_base;
+	if (data == &icu_data[0]) {
+		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+		r &= ~data->conf_mask;
+		r |= data->conf_disable;
+		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+	} else {
+		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+		writel_relaxed(r, data->reg_mask);
+	}
+}
+
+static void icu_unmask_irq(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+	int hwirq;
+	u32 r;
+
+	hwirq = d->irq - data->virq_base;
+	if (data == &icu_data[0]) {
+		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+		r &= ~data->conf_mask;
+		r |= data->conf_enable;
+		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+	} else {
+		r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
+		writel_relaxed(r, data->reg_mask);
+	}
+}
+
+static struct irq_chip icu_irq_chip = {
+	.name		= "icu_irq",
+	.irq_ack	= icu_mask_irq,
+	.irq_mask	= icu_mask_irq,
+	.irq_unmask	= icu_unmask_irq,
+};
+
+static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_domain *domain;
+	struct icu_chip_data *data;
+	int i;
+	unsigned long mask, status, n;
+
+	for (i = 1; i < max_icu_nr; i++) {
+		if (irq == icu_data[i].cascade_irq) {
+			domain = icu_data[i].domain;
+			data = (struct icu_chip_data *)domain->host_data;
+			break;
+		}
+	}
+	if (i >= max_icu_nr) {
+		pr_err("Spurious irq %d in MMP INTC\n", irq);
+		return;
+	}
+
+	mask = readl_relaxed(data->reg_mask);
+	while (1) {
+		status = readl_relaxed(data->reg_status) & ~mask;
+		if (status == 0)
+			break;
+		n = find_first_bit(&status, BITS_PER_LONG);
+		while (n < BITS_PER_LONG) {
+			generic_handle_irq(icu_data[i].virq_base + n);
+			n = find_next_bit(&status, BITS_PER_LONG, n + 1);
+		}
+	}
+}
+
+static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
+				const u32 *intspec, unsigned int intsize,
+				unsigned long *out_hwirq,
+				unsigned int *out_type)
+{
+	*out_hwirq = intspec[0];
+	return 0;
+}
+
+const struct irq_domain_ops mmp_irq_domain_ops = {
+	.map		= mmp_irq_domain_map,
+	.xlate		= mmp_irq_domain_xlate,
+};
+
+static struct mmp_intc_conf mmp_conf = {
+	.conf_enable	= 0x51,
+	.conf_disable	= 0x0,
+	.conf_mask	= 0x7f,
+};
+
+static struct mmp_intc_conf mmp2_conf = {
+	.conf_enable	= 0x20,
+	.conf_disable	= 0x0,
+	.conf_mask	= 0x7f,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+	{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
+	{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
+	{}
+};
+
+static const struct of_device_id mmp_mux_irq_match[] __initconst = {
+	{ .compatible = "mrvl,mmp2-mux-intc" },
+	{}
+};
+
+int __init mmp_mux_init(struct device_node *parent)
+{
+	struct device_node *node;
+	const struct of_device_id *of_id;
+	struct resource res;
+	int i, irq_base, ret, irq;
+	u32 nr_irqs;
+
+	node = parent;
+	max_icu_nr = 1;
+	for (i = 1; i < MAX_ICU_NR; i++) {
+		node = of_find_matching_node(node, mmp_mux_irq_match);
+		if (!node)
+			break;
+		of_id = of_match_node(&mmp_mux_irq_match[0], node);
+		ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
+					   &nr_irqs);
+		if (ret) {
+			pr_err("Not found mrvl,intc-nr-irqs property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		ret = of_address_to_resource(node, 0, &res);
+		if (ret < 0) {
+			pr_err("Not found reg property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		icu_data[i].reg_status = mmp_icu_base + res.start;
+		ret = of_address_to_resource(node, 1, &res);
+		if (ret < 0) {
+			pr_err("Not found reg property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		icu_data[i].reg_mask = mmp_icu_base + res.start;
+		icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
+		if (!icu_data[i].cascade_irq) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+		if (irq_base < 0) {
+			pr_err("Failed to allocate IRQ numbers for mux intc\n");
+			ret = irq_base;
+			goto err;
+		}
+		irq_set_chained_handler(icu_data[i].cascade_irq,
+					icu_mux_irq_demux);
+		icu_data[i].nr_irqs = nr_irqs;
+		icu_data[i].virq_base = irq_base;
+		icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
+							   irq_base, 0,
+							   &mmp_irq_domain_ops,
+							   &icu_data[i]);
+		for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+			icu_mask_irq(irq_get_irq_data(irq));
+	}
+	max_icu_nr = i;
+	return 0;
+err:
+	of_node_put(node);
+	max_icu_nr = i;
+	return ret;
+}
+
+void __init mmp_dt_irq_init(void)
+{
+	struct device_node *node;
+	const struct of_device_id *of_id;
+	struct mmp_intc_conf *conf;
+	int nr_irqs, irq_base, ret, irq;
+
+	node = of_find_matching_node(NULL, intc_ids);
+	if (!node) {
+		pr_err("Failed to find interrupt controller in arch-mmp\n");
+		return;
+	}
+	of_id = of_match_node(intc_ids, node);
+	conf = of_id->data;
+
+	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
+	if (ret) {
+		pr_err("Not found mrvl,intc-nr-irqs property\n");
+		return;
+	}
+
+	mmp_icu_base = of_iomap(node, 0);
+	if (!mmp_icu_base) {
+		pr_err("Failed to get interrupt controller register\n");
+		return;
+	}
+
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (irq_base < 0) {
+		pr_err("Failed to allocate IRQ numbers\n");
+		goto err;
+	}
+	icu_data[0].conf_enable = conf->conf_enable;
+	icu_data[0].conf_disable = conf->conf_disable;
+	icu_data[0].conf_mask = conf->conf_mask;
+	icu_data[0].nr_irqs = nr_irqs;
+	icu_data[0].virq_base = irq_base;
+	icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs,
+						   irq_base, 0,
+						   &mmp_irq_domain_ops,
+						   &icu_data[0]);
+	irq_set_default_host(icu_data[0].domain);
+	for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+		icu_mask_irq(irq_get_irq_data(irq));
+	mmp_mux_init(node);
+	return;
+err:
+	iounmap(mmp_icu_base);
+}
-- 
1.7.5.4

[PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

Append new interrupt driver that could support both pxa168 and mmp2
silicon. And this driver supports device tree.

Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
handle reserved NR_IRQS_LEGACY in irq domain.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-mmp/Makefile                   |    2 +-
 arch/arm/mach-mmp/include/mach/entry-macro.S |    9 +
 arch/arm/mach-mmp/irq.c                      |  287 ++++++++++++++++++++++++++
 3 files changed, 297 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mmp/irq.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4fc0ff5..4e73a15 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,6 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
-obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
+obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o irq.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 9cff9e7..6b9d925 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -6,13 +6,19 @@
  * published by the Free Software Foundation.
  */
 
+#include <asm/irq.h>
 #include <mach/regs-icu.h>
 
 	.macro	get_irqnr_preamble, base, tmp
 	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
 	and	\tmp, \tmp, #0xff00
 	cmp	\tmp, #0x5800
+#ifdef CONFIG_OF
+	ldr	\base, =mmp_icu_base
+	ldr	\base, [\base, #0]
+#else
 	ldr	\base, =ICU_VIRT_BASE
+#endif
 	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register
 	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register
 	.endm
@@ -20,5 +26,8 @@
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	ldr	\tmp, [\base, #0]
 	and	\irqnr, \tmp, #0x3f
+#ifdef CONFIG_OF
+	add	\irqnr, \irqnr, #NR_IRQS_LEGACY
+#endif
 	tst	\tmp, #(1 << 6)
 	.endm
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 0000000..8d0890f
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,287 @@
+/*
+ *  linux/arch/arm/mach-mmp/irq.c
+ *
+ *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
+ *
+ *  Author:	Bin Yang <bin.yang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *              Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "common.h"
+
+#define MAX_ICU_NR		16
+
+struct icu_chip_data {
+	int			nr_irqs;
+	unsigned int		virq_base;
+	unsigned int		cascade_irq;
+	void __iomem		*reg_status;
+	void __iomem		*reg_mask;
+	unsigned int		conf_enable;
+	unsigned int		conf_disable;
+	unsigned int		conf_mask;
+	struct irq_domain	*domain;
+};
+
+struct mmp_intc_conf {
+	unsigned int	conf_enable;
+	unsigned int	conf_disable;
+	unsigned int	conf_mask;
+};
+
+void __iomem *mmp_icu_base;
+static struct icu_chip_data icu_data[MAX_ICU_NR];
+static int max_icu_nr;
+
+static void icu_mask_irq(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+	int hwirq;
+	u32 r;
+
+	hwirq = d->irq - data->virq_base;
+	if (data == &icu_data[0]) {
+		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+		r &= ~data->conf_mask;
+		r |= data->conf_disable;
+		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+	} else {
+		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+		writel_relaxed(r, data->reg_mask);
+	}
+}
+
+static void icu_unmask_irq(struct irq_data *d)
+{
+	struct irq_domain *domain = d->domain;
+	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+	int hwirq;
+	u32 r;
+
+	hwirq = d->irq - data->virq_base;
+	if (data == &icu_data[0]) {
+		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+		r &= ~data->conf_mask;
+		r |= data->conf_enable;
+		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+	} else {
+		r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
+		writel_relaxed(r, data->reg_mask);
+	}
+}
+
+static struct irq_chip icu_irq_chip = {
+	.name		= "icu_irq",
+	.irq_ack	= icu_mask_irq,
+	.irq_mask	= icu_mask_irq,
+	.irq_unmask	= icu_unmask_irq,
+};
+
+static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_domain *domain;
+	struct icu_chip_data *data;
+	int i;
+	unsigned long mask, status, n;
+
+	for (i = 1; i < max_icu_nr; i++) {
+		if (irq == icu_data[i].cascade_irq) {
+			domain = icu_data[i].domain;
+			data = (struct icu_chip_data *)domain->host_data;
+			break;
+		}
+	}
+	if (i >= max_icu_nr) {
+		pr_err("Spurious irq %d in MMP INTC\n", irq);
+		return;
+	}
+
+	mask = readl_relaxed(data->reg_mask);
+	while (1) {
+		status = readl_relaxed(data->reg_status) & ~mask;
+		if (status == 0)
+			break;
+		n = find_first_bit(&status, BITS_PER_LONG);
+		while (n < BITS_PER_LONG) {
+			generic_handle_irq(icu_data[i].virq_base + n);
+			n = find_next_bit(&status, BITS_PER_LONG, n + 1);
+		}
+	}
+}
+
+static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
+				const u32 *intspec, unsigned int intsize,
+				unsigned long *out_hwirq,
+				unsigned int *out_type)
+{
+	*out_hwirq = intspec[0];
+	return 0;
+}
+
+const struct irq_domain_ops mmp_irq_domain_ops = {
+	.map		= mmp_irq_domain_map,
+	.xlate		= mmp_irq_domain_xlate,
+};
+
+static struct mmp_intc_conf mmp_conf = {
+	.conf_enable	= 0x51,
+	.conf_disable	= 0x0,
+	.conf_mask	= 0x7f,
+};
+
+static struct mmp_intc_conf mmp2_conf = {
+	.conf_enable	= 0x20,
+	.conf_disable	= 0x0,
+	.conf_mask	= 0x7f,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+	{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
+	{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
+	{}
+};
+
+static const struct of_device_id mmp_mux_irq_match[] __initconst = {
+	{ .compatible = "mrvl,mmp2-mux-intc" },
+	{}
+};
+
+int __init mmp_mux_init(struct device_node *parent)
+{
+	struct device_node *node;
+	const struct of_device_id *of_id;
+	struct resource res;
+	int i, irq_base, ret, irq;
+	u32 nr_irqs;
+
+	node = parent;
+	max_icu_nr = 1;
+	for (i = 1; i < MAX_ICU_NR; i++) {
+		node = of_find_matching_node(node, mmp_mux_irq_match);
+		if (!node)
+			break;
+		of_id = of_match_node(&mmp_mux_irq_match[0], node);
+		ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
+					   &nr_irqs);
+		if (ret) {
+			pr_err("Not found mrvl,intc-nr-irqs property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		ret = of_address_to_resource(node, 0, &res);
+		if (ret < 0) {
+			pr_err("Not found reg property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		icu_data[i].reg_status = mmp_icu_base + res.start;
+		ret = of_address_to_resource(node, 1, &res);
+		if (ret < 0) {
+			pr_err("Not found reg property\n");
+			ret = -EINVAL;
+			goto err;
+		}
+		icu_data[i].reg_mask = mmp_icu_base + res.start;
+		icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
+		if (!icu_data[i].cascade_irq) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+		if (irq_base < 0) {
+			pr_err("Failed to allocate IRQ numbers for mux intc\n");
+			ret = irq_base;
+			goto err;
+		}
+		irq_set_chained_handler(icu_data[i].cascade_irq,
+					icu_mux_irq_demux);
+		icu_data[i].nr_irqs = nr_irqs;
+		icu_data[i].virq_base = irq_base;
+		icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
+							   irq_base, 0,
+							   &mmp_irq_domain_ops,
+							   &icu_data[i]);
+		for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+			icu_mask_irq(irq_get_irq_data(irq));
+	}
+	max_icu_nr = i;
+	return 0;
+err:
+	of_node_put(node);
+	max_icu_nr = i;
+	return ret;
+}
+
+void __init mmp_dt_irq_init(void)
+{
+	struct device_node *node;
+	const struct of_device_id *of_id;
+	struct mmp_intc_conf *conf;
+	int nr_irqs, irq_base, ret, irq;
+
+	node = of_find_matching_node(NULL, intc_ids);
+	if (!node) {
+		pr_err("Failed to find interrupt controller in arch-mmp\n");
+		return;
+	}
+	of_id = of_match_node(intc_ids, node);
+	conf = of_id->data;
+
+	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
+	if (ret) {
+		pr_err("Not found mrvl,intc-nr-irqs property\n");
+		return;
+	}
+
+	mmp_icu_base = of_iomap(node, 0);
+	if (!mmp_icu_base) {
+		pr_err("Failed to get interrupt controller register\n");
+		return;
+	}
+
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (irq_base < 0) {
+		pr_err("Failed to allocate IRQ numbers\n");
+		goto err;
+	}
+	icu_data[0].conf_enable = conf->conf_enable;
+	icu_data[0].conf_disable = conf->conf_disable;
+	icu_data[0].conf_mask = conf->conf_mask;
+	icu_data[0].nr_irqs = nr_irqs;
+	icu_data[0].virq_base = irq_base;
+	icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs,
+						   irq_base, 0,
+						   &mmp_irq_domain_ops,
+						   &icu_data[0]);
+	irq_set_default_host(icu_data[0].domain);
+	for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+		icu_mask_irq(irq_get_irq_data(irq));
+	mmp_mux_init(node);
+	return;
+err:
+	iounmap(mmp_icu_base);
+}
-- 
1.7.5.4

[PATCH 3/9] ARM: mmp: support DT in irq

[Grant Likely]

On Fri, 27 Apr 2012 16:39:11 +0800, Haojian Zhuang <haojian.zhuang@gmail.com> wrote:
> Append new interrupt driver that could support both pxa168 and mmp2
> silicon. And this driver supports device tree.
> 
> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
> handle reserved NR_IRQS_LEGACY in irq domain.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
> ---
>  arch/arm/mach-mmp/Makefile                   |    2 +-
>  arch/arm/mach-mmp/include/mach/entry-macro.S |    9 +
>  arch/arm/mach-mmp/irq.c                      |  287 ++++++++++++++++++++++++++

It shouldn't be necessary to create an entirely new irq controller
driver that duplicates the functionality of irq-mmp2.c and
irq-pxa168.c.  Instead, the existing drivers should be refactored to
work with both DT and non-DT user.

> diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
> index 9cff9e7..6b9d925 100644
> --- a/arch/arm/mach-mmp/include/mach/entry-macro.S
> +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
> @@ -6,13 +6,19 @@
>   * published by the Free Software Foundation.
>   */
>  
> +#include <asm/irq.h>
>  #include <mach/regs-icu.h>
>  
>  	.macro	get_irqnr_preamble, base, tmp
>  	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
>  	and	\tmp, \tmp, #0xff00
>  	cmp	\tmp, #0x5800
> +#ifdef CONFIG_OF
> +	ldr	\base, =mmp_icu_base
> +	ldr	\base, [\base, #0]
> +#else
>  	ldr	\base, =ICU_VIRT_BASE
> +#endif
>  	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register
>  	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register
>  	.endm
> @@ -20,5 +26,8 @@
>  	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
>  	ldr	\tmp, [\base, #0]
>  	and	\irqnr, \tmp, #0x3f
> +#ifdef CONFIG_OF
> +	add	\irqnr, \irqnr, #NR_IRQS_LEGACY
> +#endif

What do these do?  Does turning on CONFIG_OF break booting with atags?
If so then this will need to be reworked.  CONFIG_OF must not disable
non-devicetree usage.

g.

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Grant Likely]

On Fri, 27 Apr 2012 16:39:11 +0800, Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Append new interrupt driver that could support both pxa168 and mmp2
> silicon. And this driver supports device tree.
> 
> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
> handle reserved NR_IRQS_LEGACY in irq domain.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/mach-mmp/Makefile                   |    2 +-
>  arch/arm/mach-mmp/include/mach/entry-macro.S |    9 +
>  arch/arm/mach-mmp/irq.c                      |  287 ++++++++++++++++++++++++++

It shouldn't be necessary to create an entirely new irq controller
driver that duplicates the functionality of irq-mmp2.c and
irq-pxa168.c.  Instead, the existing drivers should be refactored to
work with both DT and non-DT user.

> diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
> index 9cff9e7..6b9d925 100644
> --- a/arch/arm/mach-mmp/include/mach/entry-macro.S
> +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
> @@ -6,13 +6,19 @@
>   * published by the Free Software Foundation.
>   */
>  
> +#include <asm/irq.h>
>  #include <mach/regs-icu.h>
>  
>  	.macro	get_irqnr_preamble, base, tmp
>  	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
>  	and	\tmp, \tmp, #0xff00
>  	cmp	\tmp, #0x5800
> +#ifdef CONFIG_OF
> +	ldr	\base, =mmp_icu_base
> +	ldr	\base, [\base, #0]
> +#else
>  	ldr	\base, =ICU_VIRT_BASE
> +#endif
>  	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register
>  	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register
>  	.endm
> @@ -20,5 +26,8 @@
>  	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
>  	ldr	\tmp, [\base, #0]
>  	and	\irqnr, \tmp, #0x3f
> +#ifdef CONFIG_OF
> +	add	\irqnr, \irqnr, #NR_IRQS_LEGACY
> +#endif

What do these do?  Does turning on CONFIG_OF break booting with atags?
If so then this will need to be reworked.  CONFIG_OF must not disable
non-devicetree usage.

g.

[PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 3:06 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Fri, 27 Apr 2012 16:39:11 +0800, Haojian Zhuang <haojian.zhuang@gmail.com> wrote:
>> Append new interrupt driver that could support both pxa168 and mmp2
>> silicon. And this driver supports device tree.
>>
>> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
>> handle reserved NR_IRQS_LEGACY in irq domain.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
>> ---
>> ?arch/arm/mach-mmp/Makefile ? ? ? ? ? ? ? ? ? | ? ?2 +-
>> ?arch/arm/mach-mmp/include/mach/entry-macro.S | ? ?9 +
>> ?arch/arm/mach-mmp/irq.c ? ? ? ? ? ? ? ? ? ? ?| ?287 ++++++++++++++++++++++++++
>
> It shouldn't be necessary to create an entirely new irq controller
> driver that duplicates the functionality of irq-mmp2.c and
> irq-pxa168.c. ?Instead, the existing drivers should be refactored to
> work with both DT and non-DT user.
>
New irq controller driver handles both pxa168 and mmp2. The register definition
is different. And some mux interrupt controllers are in mmp2. There
are different
interrupt numbers in each mux interrupt controller.

Directly merging these two drivers are a bit difficult. But I can make
use of DTS file
to record register address and interrupt numbers.

>> diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
>> index 9cff9e7..6b9d925 100644
>> --- a/arch/arm/mach-mmp/include/mach/entry-macro.S
>> +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
>> @@ -6,13 +6,19 @@
>> ? * published by the Free Software Foundation.
>> ? */
>>
>> +#include <asm/irq.h>
>> ?#include <mach/regs-icu.h>
>>
>> ? ? ? .macro ?get_irqnr_preamble, base, tmp
>> ? ? ? mrc ? ? p15, 0, \tmp, c0, c0, 0 ? ? ? ? @ CPUID
>> ? ? ? and ? ? \tmp, \tmp, #0xff00
>> ? ? ? cmp ? ? \tmp, #0x5800
>> +#ifdef CONFIG_OF
>> + ? ? ldr ? ? \base, =mmp_icu_base
>> + ? ? ldr ? ? \base, [\base, #0]
>> +#else
>> ? ? ? ldr ? ? \base, =ICU_VIRT_BASE
>> +#endif
>> ? ? ? addne ? \base, \base, #0x10c ? ? ? ? ? ?@ PJ1 AP INT SEL register
>> ? ? ? addeq ? \base, \base, #0x104 ? ? ? ? ? ?@ PJ4 IRQ SEL register
>> ? ? ? .endm
>> @@ -20,5 +26,8 @@
>> ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
>> ? ? ? ldr ? ? \tmp, [\base, #0]
>> ? ? ? and ? ? \irqnr, \tmp, #0x3f
>> +#ifdef CONFIG_OF
>> + ? ? add ? ? \irqnr, \irqnr, #NR_IRQS_LEGACY
>> +#endif
>
> What do these do? ?Does turning on CONFIG_OF break booting with atags?
> If so then this will need to be reworked. ?CONFIG_OF must not disable
> non-devicetree usage.
>
> g.

I use two CONFIG_OF in this file. The first one is used to record
register base address
of interrupt controller. In legacy code, the register address is
hardcoding. Do you mean
that I should remove this CONFIG_OF?

The second CONFIG_OF is used to do a rebase of interrupt number. Since
SPARSE IRQ
is enabled, NR_IRQS_LEGACY (16) is defined already. I have two
choices. Either I extended
to define ".nr_irqs" in machine script for internal interrupts, or I
reserve NR_IRQS_LEGACY and
allocate new irqs for internal interrupts. I choose the second
solution. Do you mean that I have to
use the first solution?

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Sat, Apr 28, 2012 at 3:06 AM, Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> wrote:
> On Fri, 27 Apr 2012 16:39:11 +0800, Haojian Zhuang <haojian.zhuang@gmail.com> wrote:
>> Append new interrupt driver that could support both pxa168 and mmp2
>> silicon. And this driver supports device tree.
>>
>> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
>> handle reserved NR_IRQS_LEGACY in irq domain.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  arch/arm/mach-mmp/Makefile                   |    2 +-
>>  arch/arm/mach-mmp/include/mach/entry-macro.S |    9 +
>>  arch/arm/mach-mmp/irq.c                      |  287 ++++++++++++++++++++++++++
>
> It shouldn't be necessary to create an entirely new irq controller
> driver that duplicates the functionality of irq-mmp2.c and
> irq-pxa168.c.  Instead, the existing drivers should be refactored to
> work with both DT and non-DT user.
>
New irq controller driver handles both pxa168 and mmp2. The register definition
is different. And some mux interrupt controllers are in mmp2. There
are different
interrupt numbers in each mux interrupt controller.

Directly merging these two drivers are a bit difficult. But I can make
use of DTS file
to record register address and interrupt numbers.

>> diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
>> index 9cff9e7..6b9d925 100644
>> --- a/arch/arm/mach-mmp/include/mach/entry-macro.S
>> +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
>> @@ -6,13 +6,19 @@
>>   * published by the Free Software Foundation.
>>   */
>>
>> +#include <asm/irq.h>
>>  #include <mach/regs-icu.h>
>>
>>       .macro  get_irqnr_preamble, base, tmp
>>       mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
>>       and     \tmp, \tmp, #0xff00
>>       cmp     \tmp, #0x5800
>> +#ifdef CONFIG_OF
>> +     ldr     \base, =mmp_icu_base
>> +     ldr     \base, [\base, #0]
>> +#else
>>       ldr     \base, =ICU_VIRT_BASE
>> +#endif
>>       addne   \base, \base, #0x10c            @ PJ1 AP INT SEL register
>>       addeq   \base, \base, #0x104            @ PJ4 IRQ SEL register
>>       .endm
>> @@ -20,5 +26,8 @@
>>       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
>>       ldr     \tmp, [\base, #0]
>>       and     \irqnr, \tmp, #0x3f
>> +#ifdef CONFIG_OF
>> +     add     \irqnr, \irqnr, #NR_IRQS_LEGACY
>> +#endif
>
> What do these do?  Does turning on CONFIG_OF break booting with atags?
> If so then this will need to be reworked.  CONFIG_OF must not disable
> non-devicetree usage.
>
> g.

I use two CONFIG_OF in this file. The first one is used to record
register base address
of interrupt controller. In legacy code, the register address is
hardcoding. Do you mean
that I should remove this CONFIG_OF?

The second CONFIG_OF is used to do a rebase of interrupt number. Since
SPARSE IRQ
is enabled, NR_IRQS_LEGACY (16) is defined already. I have two
choices. Either I extended
to define ".nr_irqs" in machine script for internal interrupts, or I
reserve NR_IRQS_LEGACY and
allocate new irqs for internal interrupts. I choose the second
solution. Do you mean that I have to
use the first solution?

[PATCH 3/9] ARM: mmp: support DT in irq

[Arnd Bergmann]

On Wednesday 02 May 2012, Haojian Zhuang wrote:
> I use two CONFIG_OF in this file. The first one is used to record
> register base address
> of interrupt controller. In legacy code, the register address is
> hardcoding. Do you mean
> that I should remove this CONFIG_OF?

Unless it's a noticeable performance impact, I would recommend just
always using the mmp_icu_base variable, even for when CONFIG_OF is
disabled.

	Arnd

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Arnd Bergmann]

On Wednesday 02 May 2012, Haojian Zhuang wrote:
> I use two CONFIG_OF in this file. The first one is used to record
> register base address
> of interrupt controller. In legacy code, the register address is
> hardcoding. Do you mean
> that I should remove this CONFIG_OF?

Unless it's a noticeable performance impact, I would recommend just
always using the mmp_icu_base variable, even for when CONFIG_OF is
disabled.

	Arnd

[PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Wed, May 2, 2012 at 8:51 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 02 May 2012, Haojian Zhuang wrote:
>> I use two CONFIG_OF in this file. The first one is used to record
>> register base address
>> of interrupt controller. In legacy code, the register address is
>> hardcoding. Do you mean
>> that I should remove this CONFIG_OF?
>
> Unless it's a noticeable performance impact, I would recommend just
> always using the mmp_icu_base variable, even for when CONFIG_OF is
> disabled.
>
> ? ? ? ?Arnd

But I appended new irq handler for DT support. I still need to reserve
this CONFIG_OF
since I need to keep compatible with legacy code. While everything in
arch-mmp is moved
into DT, I can remove this CONFIG_OF.

For the second CONFIG_OF, I can try to remove it.

Best Regards
Haojian

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Wed, May 2, 2012 at 8:51 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Wednesday 02 May 2012, Haojian Zhuang wrote:
>> I use two CONFIG_OF in this file. The first one is used to record
>> register base address
>> of interrupt controller. In legacy code, the register address is
>> hardcoding. Do you mean
>> that I should remove this CONFIG_OF?
>
> Unless it's a noticeable performance impact, I would recommend just
> always using the mmp_icu_base variable, even for when CONFIG_OF is
> disabled.
>
>        Arnd

But I appended new irq handler for DT support. I still need to reserve
this CONFIG_OF
since I need to keep compatible with legacy code. While everything in
arch-mmp is moved
into DT, I can remove this CONFIG_OF.

For the second CONFIG_OF, I can try to remove it.

Best Regards
Haojian

[PATCH 3/9] ARM: mmp: support DT in irq

[Arnd Bergmann]

On Friday 04 May 2012, Haojian Zhuang wrote:
> On Wed, May 2, 2012 at 8:51 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Wednesday 02 May 2012, Haojian Zhuang wrote:
> >> I use two CONFIG_OF in this file. The first one is used to record
> >> register base address
> >> of interrupt controller. In legacy code, the register address is
> >> hardcoding. Do you mean
> >> that I should remove this CONFIG_OF?
> >
> > Unless it's a noticeable performance impact, I would recommend just
> > always using the mmp_icu_base variable, even for when CONFIG_OF is
> > disabled.
> 
> But I appended new irq handler for DT support. I still need to reserve
> this CONFIG_OF
> since I need to keep compatible with legacy code.

You don't need to worry about out-of-tree code, it can adapt. For the
non-DT version, why can't you move the 'mmp_icu_base' variable into
common.c and just initialize it to ICU_VIRT_BASE?
If you do that, any combination of DT- and non-DT board files should
work with the same entry-macro.S code.

Another alternative would be to convert MMP over to
CONFIG_MULTI_IRQ_HANDLER and use different handle_irq functions.

	Arnd

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Arnd Bergmann]

On Friday 04 May 2012, Haojian Zhuang wrote:
> On Wed, May 2, 2012 at 8:51 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> > On Wednesday 02 May 2012, Haojian Zhuang wrote:
> >> I use two CONFIG_OF in this file. The first one is used to record
> >> register base address
> >> of interrupt controller. In legacy code, the register address is
> >> hardcoding. Do you mean
> >> that I should remove this CONFIG_OF?
> >
> > Unless it's a noticeable performance impact, I would recommend just
> > always using the mmp_icu_base variable, even for when CONFIG_OF is
> > disabled.
> 
> But I appended new irq handler for DT support. I still need to reserve
> this CONFIG_OF
> since I need to keep compatible with legacy code.

You don't need to worry about out-of-tree code, it can adapt. For the
non-DT version, why can't you move the 'mmp_icu_base' variable into
common.c and just initialize it to ICU_VIRT_BASE?
If you do that, any combination of DT- and non-DT board files should
work with the same entry-macro.S code.

Another alternative would be to convert MMP over to
CONFIG_MULTI_IRQ_HANDLER and use different handle_irq functions.

	Arnd

[PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi Haojian,

On Fri, Apr 27 2012, Haojian Zhuang wrote:
> Append new interrupt driver that could support both pxa168 and mmp2
> silicon. And this driver supports device tree.
>
> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
> handle reserved NR_IRQS_LEGACY in irq domain.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>

This patch (now in mainline) breaks boot on XO-1.75 (MMP2, non-DT).
I hit the error path below:

> +	for (i = 1; i < max_icu_nr; i++) {
> +		if (irq == icu_data[i].cascade_irq) {
> +			domain = icu_data[i].domain;
> +			data = (struct icu_chip_data *)domain->host_data;
> +			break;
> +		}
> +	}
> +	if (i >= max_icu_nr) {
> +		pr_err("Spurious irq %d in MMP INTC\n", irq);
> +		return;
> +	}

This error path is hit because i=8 and max_icu_nr=8, which is because
we never matched (irq == icu_data[i].cascade_irq) in the for loop above.
This test is outside of a DT path, but cascade_irq appears to only ever
be set *inside* a DT path:

> +		icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
> +		if (!icu_data[i].cascade_irq) {
> +			ret = -EINVAL;
> +			goto err;
> +		}

Did you test non-DT boot with these changes?

Thanks,

- Chris.
-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi Haojian,

On Fri, Apr 27 2012, Haojian Zhuang wrote:
> Append new interrupt driver that could support both pxa168 and mmp2
> silicon. And this driver supports device tree.
>
> Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, irq driver should
> handle reserved NR_IRQS_LEGACY in irq domain.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

This patch (now in mainline) breaks boot on XO-1.75 (MMP2, non-DT).
I hit the error path below:

> +	for (i = 1; i < max_icu_nr; i++) {
> +		if (irq == icu_data[i].cascade_irq) {
> +			domain = icu_data[i].domain;
> +			data = (struct icu_chip_data *)domain->host_data;
> +			break;
> +		}
> +	}
> +	if (i >= max_icu_nr) {
> +		pr_err("Spurious irq %d in MMP INTC\n", irq);
> +		return;
> +	}

This error path is hit because i=8 and max_icu_nr=8, which is because
we never matched (irq == icu_data[i].cascade_irq) in the for loop above.
This test is outside of a DT path, but cascade_irq appears to only ever
be set *inside* a DT path:

> +		icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
> +		if (!icu_data[i].cascade_irq) {
> +			ret = -EINVAL;
> +			goto err;
> +		}

Did you test non-DT boot with these changes?

Thanks,

- Chris.
-- 
Chris Ball   <cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org>   <http://printf.net/>
One Laptop Per Child

[PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Thu, May 31, 2012 at 3:38 AM, Chris Ball <cjb@laptop.org> wrote:
> Hi Haojian,
>

>
> Did you test non-DT boot with these changes?
>
I tested non-DT boot on my brownstone board on TTC dkb board.

It seems that you meet issue in icu_mux_irq_demux(). Could you give me
the detail which interrupt is running while you meet the error?

By the way, do you have the boot log?

Regards
Haojian

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Haojian Zhuang]

On Thu, May 31, 2012 at 3:38 AM, Chris Ball <cjb@laptop.org> wrote:
> Hi Haojian,
>

>
> Did you test non-DT boot with these changes?
>
I tested non-DT boot on my brownstone board on TTC dkb board.

It seems that you meet issue in icu_mux_irq_demux(). Could you give me
the detail which interrupt is running while you meet the error?

By the way, do you have the boot log?

Regards
Haojian

[PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi,

On Wed, May 30 2012, Haojian Zhuang wrote:
>> Did you test non-DT boot with these changes?
>>
> I tested non-DT boot on my brownstone board on TTC dkb board.

Thanks.  Do you know how/where cascade_irq gets set on that board?

> It seems that you meet issue in icu_mux_irq_demux(). Could you give me
> the detail which interrupt is running while you meet the error?

It was IRQ 17 (TWSI).

> By the way, do you have the boot log?

I'll send it tomorrow when I get back to work.

Thanks,

- Chris.
-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi,

On Wed, May 30 2012, Haojian Zhuang wrote:
>> Did you test non-DT boot with these changes?
>>
> I tested non-DT boot on my brownstone board on TTC dkb board.

Thanks.  Do you know how/where cascade_irq gets set on that board?

> It seems that you meet issue in icu_mux_irq_demux(). Could you give me
> the detail which interrupt is running while you meet the error?

It was IRQ 17 (TWSI).

> By the way, do you have the boot log?

I'll send it tomorrow when I get back to work.

Thanks,

- Chris.
-- 
Chris Ball   <cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org>   <http://printf.net/>
One Laptop Per Child

[PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi Haojian,

On Wed, May 30 2012, Haojian Zhuang wrote:
> I tested non-DT boot on my brownstone board on TTC dkb board.
>
> It seems that you meet issue in icu_mux_irq_demux(). Could you give me
> the detail which interrupt is running while you meet the error?
>
> By the way, do you have the boot log?

Here's the boot log -- you can see I added some more info to the
"Spurious IRQ" message.

Thanks,

- Chris.

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0e5c8...
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.4.0-44790-g83931a4-dirty (cjb at hydro) (gcc version 4.6.1 (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #27 PREEMPT Wed May 30 15:06:55 EDT 2012
[    0.000000] CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine: OLPC XO-1.75, model: 1B1
[    0.000000] cma: CMA: reserved 64 MiB at 1c000000
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] OLPC board revision 1B1 (EC api 4)
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
[    0.000000] Kernel command line: ttyS2  no_console_suspend console=ttyS2,115200 console=tty0 fbcon=font:SUN12x22
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 512MB = 512MB total
[    0.000000] Memory: 444016k/444016k available, 80272k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0498f98   (4676 kB)
[    0.000000]       .init : 0xc0499000 - 0xc04bd000   ( 144 kB)
[    0.000000]       .data : 0xc04be000 - 0xc04ed4b8   ( 190 kB)
[    0.000000]        .bss : 0xc04ed4dc - 0xc055eecc   ( 455 kB)
[    0.000000] NR_IRQS:16 nr_irqs:368 368
[    0.000000] sched_clock: 32 bits at 6MHz, resolution 153ns, wraps every 660764ms
[    0.000000] Console: colour dummy device 80x30
[    0.000000] console [tty0] enabled
[    0.040075] Calibrating delay loop... 795.44 BogoMIPS (lpj=3977216)
[    0.040135] pid_max: default: 32768 minimum: 301
[    0.040164] Mount-cache hash table entries: 512
[    0.042210] CPU: Testing write buffer coherency: ok
[    0.042372] Setting up static identity map for 0x3625a0 - 0x3625f8
[    0.044035] devtmpfs: initialized
[    0.044989] initlevel:0=early, 3 registered initcalls
[    0.044989] initlevel:1=core, 19 registered initcalls
[    0.050514] NET: Registered protocol family 16
[    0.050514] initlevel:2=postcore, 13 registered initcalls
[    0.058323] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.058323] Tauros2: Disabling L2 prefetch.
[    0.058384] Tauros2: L2 cache support initialised in ARMv7 mode.
[    0.058407] initlevel:3=arch, 3 registered initcalls
[    0.059230] pxa-gpio pxa-gpio: Failed to find gpio controller
[    0.060754] initlevel:4=subsys, 40 registered initcalls
[    0.063786] bio: create slab <bio-0> at 0
[    0.064405] SCSI subsystem initialized
[    0.064405] usbcore: registered new interface driver usbfs
[    0.064537] usbcore: registered new interface driver hub
[    0.064746] usbcore: registered new device driver usb
[    0.065034] i2c-gpio i2c-gpio.6: using pins 110 (SDA) and 161 (SCL)
[    0.065034] i2c-gpio i2c-gpio.7: using pins 109 (SDA) and 108 (SCL)
[    0.065486] I2C: i2c-3: PXA I2C adapter
[    0.065763] I2C: i2c-1: PXA I2C adapter
[    0.066026] I2C: i2c-0: PXA I2C adapter
[    0.066075] Linux video capture interface: v2.00
[    0.066075] Advanced Linux Sound Architecture Driver Version 1.0.25.
[    0.066928] cfg80211: Calling CRDA to update world regulatory domain
[    0.067233] initlevel:5=fs, 15 registered initcalls
[    0.067381] Switching to clocksource clocksource
[    0.074416] NET: Registered protocol family 2
[    0.074862] IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.074862] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    0.075290] TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
[    0.075541] TCP: Hash tables configured (established 16384 bind 16384)
[    0.075694] TCP: reno registered
[    0.075721] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.075743] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.075778] NET: Registered protocol family 1
[    0.075990] Trying to unpack rootfs image as initramfs...
[    0.126224] Freeing initrd memory: 4548K
[    0.126224] initlevel:6=device, 150 registered initcalls
[    0.128223] VFS: Disk quotas dquot_6.5.2
[    0.128351] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.129006] msgmni has been set to 1004
[    0.129679] io scheduler noop registered
[    0.129704] io scheduler deadline registered
[    0.129735] io scheduler cfq registered (default)
[    0.147410] Console: switching to colour frame buffer device 100x40
[    0.165729] pxa2xx-uart.2: ttyS2 at MMIO 0xd4018000 (irq = 24) is a UART3
[    0.604763] console [ttyS2] enabled
[    0.613511] brd: module loaded
[    0.613712] OLPC XO-1.75 Embedded Controller driver probed
[    0.622654] input: Power Button as /devices/platform/olpc-ec-1.75.0/input/input0
[    0.647411] input: OLPC OLS notify as /devices/platform/olpc-ols.0/input/input1
[    0.660453] OLPC Outdoor Light Sensor driver probed
[    0.670807] OLPC XO-1.75 lid and ebook switches
[    0.680812] input: OLPC lid switch as /devices/virtual/input/input2
[    0.692890] input: OLPC ebook switch as /devices/virtual/input/input3
[    0.705720] usbcore: registered new interface driver ipheth
[    0.717368] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.729787] pxau2o-ehci pxau2o-ehci.0: pxa9xx ehci
[    0.740594] pxau2o-ehci pxau2o-ehci.0: new USB bus registered, assigned bus number 1
[    0.756209] pxau2o-ehci pxau2o-ehci.0: irq 44, io mem 0xd4208000
[    0.787420] pxau2o-ehci pxau2o-ehci.0: USB 2.0 started, EHCI 1.00
[    0.799530] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    0.812178] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.825201] usb usb1: Product: pxa9xx ehci
[    0.834973] usb usb1: Manufacturer: Linux 3.4.0-44790-g83931a4-dirty ehci_hcd
[    0.847854] usb usb1: SerialNumber: pxau2o-ehci.0
[    0.858798] hub 1-0:1.0: USB hub found
[    0.868222] hub 1-0:1.0: 1 port detected
[    0.877770] Initializing USB Mass Storage driver...
[    0.888467] usbcore: registered new interface driver usb-storage
[    0.900160] USB Mass Storage support registered.
[    0.910406] usbcore: registered new interface driver libusual
[    0.921801] usbcore: registered new interface driver mdc800
[    0.932865] mdc800: v0.7.5 (30/10/2000):USB Driver for Mustek MDC800 Digital Camera
[    0.946314] usbcore: registered new interface driver usbserial
[    0.957782] usbcore: registered new interface driver usbserial_generic
[    0.969927] USB Serial support registered for generic
[    0.980620] usbserial: USB Serial Driver core
[    0.990928] OLPC SP keyboard/touchpad driver probed
[    1.052001] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[    1.111662] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[    1.162916] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[repeat forever]

-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

Re: [PATCH 3/9] ARM: mmp: support DT in irq

[Chris Ball]

Hi Haojian,

On Wed, May 30 2012, Haojian Zhuang wrote:
> I tested non-DT boot on my brownstone board on TTC dkb board.
>
> It seems that you meet issue in icu_mux_irq_demux(). Could you give me
> the detail which interrupt is running while you meet the error?
>
> By the way, do you have the boot log?

Here's the boot log -- you can see I added some more info to the
"Spurious IRQ" message.

Thanks,

- Chris.

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0e5c8...
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.4.0-44790-g83931a4-dirty (cjb@hydro) (gcc version 4.6.1 (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #27 PREEMPT Wed May 30 15:06:55 EDT 2012
[    0.000000] CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine: OLPC XO-1.75, model: 1B1
[    0.000000] cma: CMA: reserved 64 MiB at 1c000000
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] OLPC board revision 1B1 (EC api 4)
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
[    0.000000] Kernel command line: ttyS2  no_console_suspend console=ttyS2,115200 console=tty0 fbcon=font:SUN12x22
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 512MB = 512MB total
[    0.000000] Memory: 444016k/444016k available, 80272k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0498f98   (4676 kB)
[    0.000000]       .init : 0xc0499000 - 0xc04bd000   ( 144 kB)
[    0.000000]       .data : 0xc04be000 - 0xc04ed4b8   ( 190 kB)
[    0.000000]        .bss : 0xc04ed4dc - 0xc055eecc   ( 455 kB)
[    0.000000] NR_IRQS:16 nr_irqs:368 368
[    0.000000] sched_clock: 32 bits at 6MHz, resolution 153ns, wraps every 660764ms
[    0.000000] Console: colour dummy device 80x30
[    0.000000] console [tty0] enabled
[    0.040075] Calibrating delay loop... 795.44 BogoMIPS (lpj=3977216)
[    0.040135] pid_max: default: 32768 minimum: 301
[    0.040164] Mount-cache hash table entries: 512
[    0.042210] CPU: Testing write buffer coherency: ok
[    0.042372] Setting up static identity map for 0x3625a0 - 0x3625f8
[    0.044035] devtmpfs: initialized
[    0.044989] initlevel:0=early, 3 registered initcalls
[    0.044989] initlevel:1=core, 19 registered initcalls
[    0.050514] NET: Registered protocol family 16
[    0.050514] initlevel:2=postcore, 13 registered initcalls
[    0.058323] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.058323] Tauros2: Disabling L2 prefetch.
[    0.058384] Tauros2: L2 cache support initialised in ARMv7 mode.
[    0.058407] initlevel:3=arch, 3 registered initcalls
[    0.059230] pxa-gpio pxa-gpio: Failed to find gpio controller
[    0.060754] initlevel:4=subsys, 40 registered initcalls
[    0.063786] bio: create slab <bio-0> at 0
[    0.064405] SCSI subsystem initialized
[    0.064405] usbcore: registered new interface driver usbfs
[    0.064537] usbcore: registered new interface driver hub
[    0.064746] usbcore: registered new device driver usb
[    0.065034] i2c-gpio i2c-gpio.6: using pins 110 (SDA) and 161 (SCL)
[    0.065034] i2c-gpio i2c-gpio.7: using pins 109 (SDA) and 108 (SCL)
[    0.065486] I2C: i2c-3: PXA I2C adapter
[    0.065763] I2C: i2c-1: PXA I2C adapter
[    0.066026] I2C: i2c-0: PXA I2C adapter
[    0.066075] Linux video capture interface: v2.00
[    0.066075] Advanced Linux Sound Architecture Driver Version 1.0.25.
[    0.066928] cfg80211: Calling CRDA to update world regulatory domain
[    0.067233] initlevel:5=fs, 15 registered initcalls
[    0.067381] Switching to clocksource clocksource
[    0.074416] NET: Registered protocol family 2
[    0.074862] IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.074862] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    0.075290] TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
[    0.075541] TCP: Hash tables configured (established 16384 bind 16384)
[    0.075694] TCP: reno registered
[    0.075721] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.075743] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.075778] NET: Registered protocol family 1
[    0.075990] Trying to unpack rootfs image as initramfs...
[    0.126224] Freeing initrd memory: 4548K
[    0.126224] initlevel:6=device, 150 registered initcalls
[    0.128223] VFS: Disk quotas dquot_6.5.2
[    0.128351] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.129006] msgmni has been set to 1004
[    0.129679] io scheduler noop registered
[    0.129704] io scheduler deadline registered
[    0.129735] io scheduler cfq registered (default)
[    0.147410] Console: switching to colour frame buffer device 100x40
[    0.165729] pxa2xx-uart.2: ttyS2 at MMIO 0xd4018000 (irq = 24) is a UART3
[    0.604763] console [ttyS2] enabled
[    0.613511] brd: module loaded
[    0.613712] OLPC XO-1.75 Embedded Controller driver probed
[    0.622654] input: Power Button as /devices/platform/olpc-ec-1.75.0/input/input0
[    0.647411] input: OLPC OLS notify as /devices/platform/olpc-ols.0/input/input1
[    0.660453] OLPC Outdoor Light Sensor driver probed
[    0.670807] OLPC XO-1.75 lid and ebook switches
[    0.680812] input: OLPC lid switch as /devices/virtual/input/input2
[    0.692890] input: OLPC ebook switch as /devices/virtual/input/input3
[    0.705720] usbcore: registered new interface driver ipheth
[    0.717368] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.729787] pxau2o-ehci pxau2o-ehci.0: pxa9xx ehci
[    0.740594] pxau2o-ehci pxau2o-ehci.0: new USB bus registered, assigned bus number 1
[    0.756209] pxau2o-ehci pxau2o-ehci.0: irq 44, io mem 0xd4208000
[    0.787420] pxau2o-ehci pxau2o-ehci.0: USB 2.0 started, EHCI 1.00
[    0.799530] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    0.812178] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.825201] usb usb1: Product: pxa9xx ehci
[    0.834973] usb usb1: Manufacturer: Linux 3.4.0-44790-g83931a4-dirty ehci_hcd
[    0.847854] usb usb1: SerialNumber: pxau2o-ehci.0
[    0.858798] hub 1-0:1.0: USB hub found
[    0.868222] hub 1-0:1.0: 1 port detected
[    0.877770] Initializing USB Mass Storage driver...
[    0.888467] usbcore: registered new interface driver usb-storage
[    0.900160] USB Mass Storage support registered.
[    0.910406] usbcore: registered new interface driver libusual
[    0.921801] usbcore: registered new interface driver mdc800
[    0.932865] mdc800: v0.7.5 (30/10/2000):USB Driver for Mustek MDC800 Digital Camera
[    0.946314] usbcore: registered new interface driver usbserial
[    0.957782] usbcore: registered new interface driver usbserial_generic
[    0.969927] USB Serial support registered for generic
[    0.980620] usbserial: USB Serial Driver core
[    0.990928] OLPC SP keyboard/touchpad driver probed
[    1.052001] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[    1.111662] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[    1.162916] Spurious irq 17, i 8, max_icu_nr is 8, in MMP INTC
[repeat forever]

-- 
Chris Ball   <cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org>   <http://printf.net/>
One Laptop Per Child

[PATCH 4/9] ARM: mmp: support DT in timer

[Haojian Zhuang]

Parse timer from DTS file. Avoid to use hardcoding marco for register.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/mach-mmp/time.c |   81 ++++++++++++++++++++++++++++++++++------------
 1 files changed, 60 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 71fc4ee..936447c 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,6 +25,9 @@
 
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/sched_clock.h>
 #include <mach/addr-map.h>
@@ -41,6 +44,8 @@
 #define MAX_DELTA		(0xfffffffe)
 #define MIN_DELTA		(16)
 
+static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
+
 /*
  * FIXME: the timer needs some delay to stablize the counter capture
  */
@@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
 {
 	int delay = 100;
 
-	__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
+	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
 
 	while (delay--)
 		cpu_relax();
 
-	return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
+	return __raw_readl(mmp_timer_base + TMR_CVWR(1));
 }
 
 static u32 notrace mmp_read_sched_clock(void)
@@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 	/*
 	 * Clear pending interrupt status.
 	 */
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
 
 	/*
 	 * Disable timer 0.
 	 */
-	__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x02, mmp_timer_base + TMR_CER);
 
 	c->event_handler(c);
 
@@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
 	/*
 	 * Disable timer 0.
 	 */
-	__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x02, mmp_timer_base + TMR_CER);
 
 	/*
 	 * Clear and enable timer match 0 interrupt.
 	 */
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
 
 	/*
 	 * Setup new clockevent timer value.
 	 */
-	__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
+	__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
 
 	/*
 	 * Enable timer 0.
 	 */
-	__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x03, mmp_timer_base + TMR_CER);
 
 	local_irq_restore(flags);
 
@@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 		/* disable the matching interrupt */
-		__raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
+		__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
 		break;
 	case CLOCK_EVT_MODE_RESUME:
 	case CLOCK_EVT_MODE_PERIODIC:
@@ -157,27 +162,27 @@ static struct clocksource cksrc = {
 
 static void __init timer_config(void)
 {
-	uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
+	uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
 
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
+	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
 
 	ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 		(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
-	__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
+	__raw_writel(ccr, mmp_timer_base + TMR_CCR);
 
 	/* set timer 0 to periodic mode, and timer 1 to free-running mode */
-	__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
+	__raw_writel(0x2, mmp_timer_base + TMR_CMR);
 
-	__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
-	__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+	__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
+	__raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */
+	__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
 
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
-	__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
+	__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
+	__raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */
+	__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
 
 	/* enable timer 1 counter */
-	__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x2, mmp_timer_base + TMR_CER);
 }
 
 static struct irqaction timer_irq = {
@@ -203,3 +208,37 @@ void __init timer_init(int irq)
 	clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
 	clockevents_register_device(&ckevt);
 }
+
+#ifdef CONFIG_OF
+static struct of_device_id mmp_timer_dt_ids[] = {
+	{ .compatible = "mrvl,mmp-timer", },
+	{}
+};
+
+void __init mmp_dt_init_timer(void)
+{
+	struct device_node *np;
+	int irq, ret;
+
+	np = of_find_matching_node(NULL, mmp_timer_dt_ids);
+	if (!np) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		ret = -EINVAL;
+		goto out;
+	}
+	mmp_timer_base = of_iomap(np, 0);
+	if (!mmp_timer_base) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	timer_init(irq);
+	return;
+out:
+	pr_err("Failed to get timer from device tree with error:%d\n", ret);
+}
+#endif
-- 
1.7.5.4

[PATCH 4/9] ARM: mmp: support DT in timer

[Haojian Zhuang]

Parse timer from DTS file. Avoid to use hardcoding marco for register.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-mmp/time.c |   81 ++++++++++++++++++++++++++++++++++------------
 1 files changed, 60 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 71fc4ee..936447c 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,6 +25,9 @@
 
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/sched_clock.h>
 #include <mach/addr-map.h>
@@ -41,6 +44,8 @@
 #define MAX_DELTA		(0xfffffffe)
 #define MIN_DELTA		(16)
 
+static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
+
 /*
  * FIXME: the timer needs some delay to stablize the counter capture
  */
@@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
 {
 	int delay = 100;
 
-	__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
+	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
 
 	while (delay--)
 		cpu_relax();
 
-	return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
+	return __raw_readl(mmp_timer_base + TMR_CVWR(1));
 }
 
 static u32 notrace mmp_read_sched_clock(void)
@@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 	/*
 	 * Clear pending interrupt status.
 	 */
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
 
 	/*
 	 * Disable timer 0.
 	 */
-	__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x02, mmp_timer_base + TMR_CER);
 
 	c->event_handler(c);
 
@@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
 	/*
 	 * Disable timer 0.
 	 */
-	__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x02, mmp_timer_base + TMR_CER);
 
 	/*
 	 * Clear and enable timer match 0 interrupt.
 	 */
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
-	__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
+	__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
 
 	/*
 	 * Setup new clockevent timer value.
 	 */
-	__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
+	__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
 
 	/*
 	 * Enable timer 0.
 	 */
-	__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x03, mmp_timer_base + TMR_CER);
 
 	local_irq_restore(flags);
 
@@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 		/* disable the matching interrupt */
-		__raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
+		__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
 		break;
 	case CLOCK_EVT_MODE_RESUME:
 	case CLOCK_EVT_MODE_PERIODIC:
@@ -157,27 +162,27 @@ static struct clocksource cksrc = {
 
 static void __init timer_config(void)
 {
-	uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
+	uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
 
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
+	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
 
 	ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 		(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
-	__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
+	__raw_writel(ccr, mmp_timer_base + TMR_CCR);
 
 	/* set timer 0 to periodic mode, and timer 1 to free-running mode */
-	__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
+	__raw_writel(0x2, mmp_timer_base + TMR_CMR);
 
-	__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
-	__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+	__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
+	__raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */
+	__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
 
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
-	__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
-	__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
+	__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
+	__raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */
+	__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
 
 	/* enable timer 1 counter */
-	__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
+	__raw_writel(0x2, mmp_timer_base + TMR_CER);
 }
 
 static struct irqaction timer_irq = {
@@ -203,3 +208,37 @@ void __init timer_init(int irq)
 	clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
 	clockevents_register_device(&ckevt);
 }
+
+#ifdef CONFIG_OF
+static struct of_device_id mmp_timer_dt_ids[] = {
+	{ .compatible = "mrvl,mmp-timer", },
+	{}
+};
+
+void __init mmp_dt_init_timer(void)
+{
+	struct device_node *np;
+	int irq, ret;
+
+	np = of_find_matching_node(NULL, mmp_timer_dt_ids);
+	if (!np) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		ret = -EINVAL;
+		goto out;
+	}
+	mmp_timer_base = of_iomap(np, 0);
+	if (!mmp_timer_base) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	timer_init(irq);
+	return;
+out:
+	pr_err("Failed to get timer from device tree with error:%d\n", ret);
+}
+#endif
-- 
1.7.5.4

[PATCH 5/9] gpio: pxa: parse gpio from DTS file

[Haojian Zhuang]

Parse GPIO numbers from DTS file. Allocate interrupt according to
GPIO numbers.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 drivers/gpio/gpio-pxa.c |  116 +++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 98 insertions(+), 18 deletions(-)

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 5689ce6..1f5f1ac 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -11,13 +11,17 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
+#include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
@@ -56,6 +60,10 @@
 
 int pxa_last_gpio;
 
+#ifdef CONFIG_OF
+static struct irq_domain *domain;
+#endif
+
 struct pxa_gpio_chip {
 	struct gpio_chip chip;
 	void __iomem	*regbase;
@@ -80,7 +88,6 @@ enum {
 	PXA3XX_GPIO,
 	PXA93X_GPIO,
 	MMP_GPIO = 0x10,
-	MMP2_GPIO,
 };
 
 static DEFINE_SPINLOCK(gpio_lock);
@@ -460,21 +467,91 @@ static int pxa_gpio_nums(void)
 		gpio_type = MMP_GPIO;
 	} else if (cpu_is_mmp2()) {
 		count = 191;
-		gpio_type = MMP2_GPIO;
+		gpio_type = MMP_GPIO;
 	}
 #endif /* CONFIG_ARCH_MMP */
 	return count;
 }
 
+static struct of_device_id pxa_gpio_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-gpio" },
+	{ .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
+	{}
+};
+
+static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	return 0;
+}
+
+const struct irq_domain_ops pxa_irq_domain_ops = {
+	.map	= pxa_irq_domain_map,
+};
+
+#ifdef CONFIG_OF
+static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
+{
+	int ret, nr_banks, nr_gpios, irq_base;
+	struct device_node *prev, *next, *np = pdev->dev.of_node;
+	const struct of_device_id *of_id =
+				of_match_device(pxa_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -EFAULT;
+	}
+	gpio_type = (int)of_id->data;
+
+	next = of_get_next_child(np, NULL);
+	prev = next;
+	if (!next) {
+		dev_err(&pdev->dev, "Failed to find child gpio node\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	for (nr_banks = 1; ; nr_banks++) {
+		next = of_get_next_child(np, prev);
+		if (!next)
+			break;
+		prev = next;
+	}
+	of_node_put(prev);
+	nr_gpios = nr_banks << 5;
+	pxa_last_gpio = nr_gpios - 1;
+
+	irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
+	if (irq_base < 0) {
+		dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
+		goto err;
+	}
+	domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
+				       &pxa_irq_domain_ops, NULL);
+	return 0;
+err:
+	iounmap(gpio_reg_base);
+	return ret;
+}
+#else
+#define pxa_gpio_probe_dt(pdev)		(-1)
+#endif
+
 static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 {
 	struct pxa_gpio_chip *c;
 	struct resource *res;
 	struct clk *clk;
-	int gpio, irq, ret;
+	int gpio, irq, ret, use_of = 0;
 	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
-	pxa_last_gpio = pxa_gpio_nums();
+	ret = pxa_gpio_probe_dt(pdev);
+	if (ret < 0)
+		pxa_last_gpio = pxa_gpio_nums();
+	else
+		use_of = 1;
 	if (!pxa_last_gpio)
 		return -EINVAL;
 
@@ -528,25 +605,27 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
 	}
 
+	if (!use_of) {
 #ifdef CONFIG_ARCH_PXA
-	irq = gpio_to_irq(0);
-	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-				 handle_edge_irq);
-	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
-
-	irq = gpio_to_irq(1);
-	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-				 handle_edge_irq);
-	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
-#endif
+		irq = gpio_to_irq(0);
+		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+					 handle_edge_irq);
+		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
 
-	for (irq  = gpio_to_irq(gpio_offset);
-		irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+		irq = gpio_to_irq(1);
 		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
 					 handle_edge_irq);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
+#endif
+
+		for (irq  = gpio_to_irq(gpio_offset);
+			irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+			irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+						 handle_edge_irq);
+			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		}
 	}
 
 	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
@@ -557,6 +636,7 @@ static struct platform_driver pxa_gpio_driver = {
 	.probe		= pxa_gpio_probe,
 	.driver		= {
 		.name	= "pxa-gpio",
+		.of_match_table = pxa_gpio_dt_ids,
 	},
 };
 
-- 
1.7.5.4

[PATCH 5/9] gpio: pxa: parse gpio from DTS file

[Haojian Zhuang]

Parse GPIO numbers from DTS file. Allocate interrupt according to
GPIO numbers.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/gpio/gpio-pxa.c |  116 +++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 98 insertions(+), 18 deletions(-)

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 5689ce6..1f5f1ac 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -11,13 +11,17 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
+#include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
@@ -56,6 +60,10 @@
 
 int pxa_last_gpio;
 
+#ifdef CONFIG_OF
+static struct irq_domain *domain;
+#endif
+
 struct pxa_gpio_chip {
 	struct gpio_chip chip;
 	void __iomem	*regbase;
@@ -80,7 +88,6 @@ enum {
 	PXA3XX_GPIO,
 	PXA93X_GPIO,
 	MMP_GPIO = 0x10,
-	MMP2_GPIO,
 };
 
 static DEFINE_SPINLOCK(gpio_lock);
@@ -460,21 +467,91 @@ static int pxa_gpio_nums(void)
 		gpio_type = MMP_GPIO;
 	} else if (cpu_is_mmp2()) {
 		count = 191;
-		gpio_type = MMP2_GPIO;
+		gpio_type = MMP_GPIO;
 	}
 #endif /* CONFIG_ARCH_MMP */
 	return count;
 }
 
+static struct of_device_id pxa_gpio_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-gpio" },
+	{ .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
+	{}
+};
+
+static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	return 0;
+}
+
+const struct irq_domain_ops pxa_irq_domain_ops = {
+	.map	= pxa_irq_domain_map,
+};
+
+#ifdef CONFIG_OF
+static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
+{
+	int ret, nr_banks, nr_gpios, irq_base;
+	struct device_node *prev, *next, *np = pdev->dev.of_node;
+	const struct of_device_id *of_id =
+				of_match_device(pxa_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -EFAULT;
+	}
+	gpio_type = (int)of_id->data;
+
+	next = of_get_next_child(np, NULL);
+	prev = next;
+	if (!next) {
+		dev_err(&pdev->dev, "Failed to find child gpio node\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	for (nr_banks = 1; ; nr_banks++) {
+		next = of_get_next_child(np, prev);
+		if (!next)
+			break;
+		prev = next;
+	}
+	of_node_put(prev);
+	nr_gpios = nr_banks << 5;
+	pxa_last_gpio = nr_gpios - 1;
+
+	irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
+	if (irq_base < 0) {
+		dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
+		goto err;
+	}
+	domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
+				       &pxa_irq_domain_ops, NULL);
+	return 0;
+err:
+	iounmap(gpio_reg_base);
+	return ret;
+}
+#else
+#define pxa_gpio_probe_dt(pdev)		(-1)
+#endif
+
 static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 {
 	struct pxa_gpio_chip *c;
 	struct resource *res;
 	struct clk *clk;
-	int gpio, irq, ret;
+	int gpio, irq, ret, use_of = 0;
 	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
-	pxa_last_gpio = pxa_gpio_nums();
+	ret = pxa_gpio_probe_dt(pdev);
+	if (ret < 0)
+		pxa_last_gpio = pxa_gpio_nums();
+	else
+		use_of = 1;
 	if (!pxa_last_gpio)
 		return -EINVAL;
 
@@ -528,25 +605,27 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
 	}
 
+	if (!use_of) {
 #ifdef CONFIG_ARCH_PXA
-	irq = gpio_to_irq(0);
-	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-				 handle_edge_irq);
-	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
-
-	irq = gpio_to_irq(1);
-	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-				 handle_edge_irq);
-	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
-#endif
+		irq = gpio_to_irq(0);
+		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+					 handle_edge_irq);
+		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
 
-	for (irq  = gpio_to_irq(gpio_offset);
-		irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+		irq = gpio_to_irq(1);
 		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
 					 handle_edge_irq);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
+#endif
+
+		for (irq  = gpio_to_irq(gpio_offset);
+			irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+			irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+						 handle_edge_irq);
+			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		}
 	}
 
 	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
@@ -557,6 +636,7 @@ static struct platform_driver pxa_gpio_driver = {
 	.probe		= pxa_gpio_probe,
 	.driver		= {
 		.name	= "pxa-gpio",
+		.of_match_table = pxa_gpio_dt_ids,
 	},
 };
 
-- 
1.7.5.4

[PATCH 6/9] ARM: mmp: support mmp2 with device tree

[Haojian Zhuang]

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/mach-mmp/Makefile  |    1 +
 arch/arm/mach-mmp/mmp2-dt.c |   60 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mmp/mmp2-dt.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4e73a15..45c66f3 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o irq.o
+obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o irq.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
new file mode 100644
index 0000000..535a5ed
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -0,0 +1,60 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp2-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+
+#include "common.h"
+
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
+
+static struct sys_timer mmp_dt_timer = {
+	.init	= mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static void __init mmp2_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     mmp2_auxdata_lookup, NULL);
+}
+
+static const char *mmp2_dt_board_compat[] __initdata = {
+	"mrvl,mmp2-brownstone",
+	NULL,
+};
+
+DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= mmp2_dt_init,
+	.dt_compat	= mmp2_dt_board_compat,
+MACHINE_END
-- 
1.7.5.4

[PATCH 6/9] ARM: mmp: support mmp2 with device tree

[Haojian Zhuang]

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-mmp/Makefile  |    1 +
 arch/arm/mach-mmp/mmp2-dt.c |   60 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mmp/mmp2-dt.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4e73a15..45c66f3 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o irq.o
+obj-$(CONFIG_MACH_MMP2_DT)	+= mmp2-dt.o irq.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
new file mode 100644
index 0000000..535a5ed
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -0,0 +1,60 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp2-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+
+#include "common.h"
+
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
+
+static struct sys_timer mmp_dt_timer = {
+	.init	= mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static void __init mmp2_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     mmp2_auxdata_lookup, NULL);
+}
+
+static const char *mmp2_dt_board_compat[] __initdata = {
+	"mrvl,mmp2-brownstone",
+	NULL,
+};
+
+DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= mmp2_dt_init,
+	.dt_compat	= mmp2_dt_board_compat,
+MACHINE_END
-- 
1.7.5.4

[PATCH 7/9] ARM: mmp: support pxa910 with device tree

[Haojian Zhuang]

Suppot gpio/irq/timer in mmp-dt driver. Support PXA910 also in mmp-dt
driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/mach-mmp/mmp-dt.c |   50 +++++++++++++++++++++++++++++++++++--------
 1 files changed, 40 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index ca22e3c0..033cc31 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -14,14 +14,19 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <mach/irqs.h>
 
 #include "common.h"
 
-extern struct sys_timer pxa168_timer;
-extern void __init icu_init_irq(void);
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+static struct sys_timer mmp_dt_timer = {
+	.init	= mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
@@ -32,22 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
 	{}
 };
 
-static void __init mmp_dt_init(void)
+static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static void __init pxa168_dt_init(void)
 {
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     pxa168_auxdata_lookup, NULL);
+}
 
+static void __init pxa910_dt_init(void)
+{
 	of_platform_populate(NULL, of_default_bus_match_table,
-			     mmp_auxdata_lookup, NULL);
+			     pxa910_auxdata_lookup, NULL);
 }
 
-static const char *pxa168_dt_board_compat[] __initdata = {
+static const char *mmp_dt_board_compat[] __initdata = {
 	"mrvl,pxa168-aspenite",
+	"mrvl,pxa910-dkb",
 	NULL,
 };
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
 	.map_io		= mmp_map_io,
-	.init_irq	= icu_init_irq,
-	.timer		= &pxa168_timer,
-	.init_machine	= mmp_dt_init,
-	.dt_compat	= pxa168_dt_board_compat,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= pxa168_dt_init,
+	.dt_compat	= mmp_dt_board_compat,
+MACHINE_END
+
+DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= pxa910_dt_init,
+	.dt_compat	= mmp_dt_board_compat,
 MACHINE_END
-- 
1.7.5.4

[PATCH 7/9] ARM: mmp: support pxa910 with device tree

[Haojian Zhuang]

Suppot gpio/irq/timer in mmp-dt driver. Support PXA910 also in mmp-dt
driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-mmp/mmp-dt.c |   50 +++++++++++++++++++++++++++++++++++--------
 1 files changed, 40 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index ca22e3c0..033cc31 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -14,14 +14,19 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <mach/irqs.h>
 
 #include "common.h"
 
-extern struct sys_timer pxa168_timer;
-extern void __init icu_init_irq(void);
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+static struct sys_timer mmp_dt_timer = {
+	.init	= mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
 	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
@@ -32,22 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
 	{}
 };
 
-static void __init mmp_dt_init(void)
+static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static void __init pxa168_dt_init(void)
 {
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     pxa168_auxdata_lookup, NULL);
+}
 
+static void __init pxa910_dt_init(void)
+{
 	of_platform_populate(NULL, of_default_bus_match_table,
-			     mmp_auxdata_lookup, NULL);
+			     pxa910_auxdata_lookup, NULL);
 }
 
-static const char *pxa168_dt_board_compat[] __initdata = {
+static const char *mmp_dt_board_compat[] __initdata = {
 	"mrvl,pxa168-aspenite",
+	"mrvl,pxa910-dkb",
 	NULL,
 };
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
 	.map_io		= mmp_map_io,
-	.init_irq	= icu_init_irq,
-	.timer		= &pxa168_timer,
-	.init_machine	= mmp_dt_init,
-	.dt_compat	= pxa168_dt_board_compat,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= pxa168_dt_init,
+	.dt_compat	= mmp_dt_board_compat,
+MACHINE_END
+
+DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= mmp_dt_irq_init,
+	.timer		= &mmp_dt_timer,
+	.init_machine	= pxa910_dt_init,
+	.dt_compat	= mmp_dt_board_compat,
 MACHINE_END
-- 
1.7.5.4

[PATCH 8/9] ARM: dts: refresh dts file for arch mmp

[Haojian Zhuang]

Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq,
timer, gpio components.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 arch/arm/boot/dts/mmp2-brownstone.dts |   38 ++++++
 arch/arm/boot/dts/mmp2.dtsi           |  219 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/pxa168.dtsi         |   67 ++++++++---
 arch/arm/boot/dts/pxa910-dkb.dts      |   38 ++++++
 arch/arm/boot/dts/pxa910.dtsi         |  140 +++++++++++++++++++++
 5 files changed, 486 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/boot/dts/mmp2-brownstone.dts
 create mode 100644 arch/arm/boot/dts/mmp2.dtsi
 create mode 100644 arch/arm/boot/dts/pxa910-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa910.dtsi

diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 0000000..153a4b2
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "mmp2.dtsi"
+
+/ {
+	model = "Marvell MMP2 Aspenite Development Board";
+	compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
+
+	chosen {
+		bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x04000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart3: uart at d4018000 {
+				status = "okay";
+			};
+			twsi1: i2c at d4011000 {
+				status = "okay";
+			};
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 0000000..8c95538
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,219 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		axi at d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller at d4282000 {
+				compatible = "mrvl,mmp2-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+			intcmux4 at d4282150 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <4>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x150 0x4>, <0x168 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux5: interrupt-controller at d4282154 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <5>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x154 0x4>, <0x16c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux9: interrupt-controller at d4282180 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <9>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x180 0x4>, <0x17c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <3>;
+			};
+
+			intcmux17: interrupt-controller at d4282158 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <17>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x158 0x4>, <0x170 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <5>;
+			};
+
+			intcmux35: interrupt-controller at d428215c {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <35>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x15c 0x4>, <0x174 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <15>;
+			};
+
+			intcmux51: interrupt-controller at d4282160 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <51>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x160 0x4>, <0x178 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux55: interrupt-controller at d4282188 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <55>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x188 0x4>, <0x174 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+		};
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer at d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
+			uart1: uart at d4030000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4030000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <24>;
+				status = "disabled";
+			};
+
+			uart4: uart at d4016000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4016000 0x1000>;
+				interrupts = <46>;
+				status = "disabled";
+			};
+
+			gpio at d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio at d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio at d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio at d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio at d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+
+				gcb4: gpio at d4019104 {
+					reg = <0xd4019104 0x4>;
+				};
+
+				gcb5: gpio at d4019108 {
+					reg = <0xd4019108 0x4>;
+				};
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4025000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4025000 0x1000>;
+				interrupts = <58>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <1 0>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				interrupt-parent = <&intcmux5>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d512..31a7186 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
 		i2c1 = &twsi2;
 	};
 
-	intc: intc-interrupt-controller at d4282000 {
-		compatible = "mrvl,mmp-intc", "mrvl,intc";
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		reg = <0xd4282000 0x1000>;
-	};
-
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -32,6 +25,23 @@
 		interrupt-parent = <&intc>;
 		ranges;
 
+		axi at d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller at d4282000 {
+				compatible = "mrvl,mmp-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+		};
+
 		apb at d4000000 {	/* APB */
 			compatible = "mrvl,apb-bus", "simple-bus";
 			#address-cells = <1>;
@@ -39,40 +49,65 @@
 			reg = <0xd4000000 0x00200000>;
 			ranges;
 
+			timer0: timer at d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
 			uart1: uart at d4017000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4017000 0x1000>;
 				interrupts = <27>;
 				status = "disabled";
 			};
 
 			uart2: uart at d4018000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4018000 0x1000>;
 				interrupts = <28>;
 				status = "disabled";
 			};
 
 			uart3: uart at d4026000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4026000 0x1000>;
 				interrupts = <29>;
 				status = "disabled";
 			};
 
-			gpio: gpio at d4019000 {
-				compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+			gpio at d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
 				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
 				interrupts = <49>;
 				interrupt-names = "gpio_mux";
-				gpio-controller;
-				#gpio-cells = <1>;
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio at d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio at d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio at d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio at d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
 			};
 
 			twsi1: i2c at d4011000 {
-				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				compatible = "mrvl,mmp-twsi";
 				reg = <0xd4011000 0x1000>;
 				interrupts = <7>;
 				mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
 			};
 
 			twsi2: i2c at d4025000 {
-				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				compatible = "mrvl,mmp-twsi";
 				reg = <0xd4025000 0x1000>;
 				interrupts = <58>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 0000000..e92be5a
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa910.dtsi"
+
+/ {
+	model = "Marvell PXA910 DKB Development Board";
+	compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart1: uart at d4017000 {
+				status = "okay";
+			};
+			twsi1: i2c at d4011000 {
+				status = "okay";
+			};
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 0000000..aebf32d
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		axi at d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller at d4282000 {
+				compatible = "mrvl,mmp-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+		};
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer at d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
+			timer1: timer at d4016000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4016000 0x100>;
+				interrupts = <29>;
+				status = "disabled";
+			};
+
+			uart1: uart at d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4036000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4036000 0x1000>;
+				interrupts = <59>;
+				status = "disabled";
+			};
+
+			gpio at d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio at d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio at d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio at d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio at d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4037000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4037000 0x1000>;
+				interrupts = <54>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <5 6>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.5.4

[PATCH 8/9] ARM: dts: refresh dts file for arch mmp

[Haojian Zhuang]

Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq,
timer, gpio components.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/mmp2-brownstone.dts |   38 ++++++
 arch/arm/boot/dts/mmp2.dtsi           |  219 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/pxa168.dtsi         |   67 ++++++++---
 arch/arm/boot/dts/pxa910-dkb.dts      |   38 ++++++
 arch/arm/boot/dts/pxa910.dtsi         |  140 +++++++++++++++++++++
 5 files changed, 486 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/boot/dts/mmp2-brownstone.dts
 create mode 100644 arch/arm/boot/dts/mmp2.dtsi
 create mode 100644 arch/arm/boot/dts/pxa910-dkb.dts
 create mode 100644 arch/arm/boot/dts/pxa910.dtsi

diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 0000000..153a4b2
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "mmp2.dtsi"
+
+/ {
+	model = "Marvell MMP2 Aspenite Development Board";
+	compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
+
+	chosen {
+		bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x04000000>;
+	};
+
+	soc {
+		apb@d4000000 {
+			uart3: uart@d4018000 {
+				status = "okay";
+			};
+			twsi1: i2c@d4011000 {
+				status = "okay";
+			};
+			rtc: rtc@d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 0000000..8c95538
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,219 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		axi@d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller@d4282000 {
+				compatible = "mrvl,mmp2-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+			intcmux4@d4282150 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <4>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x150 0x4>, <0x168 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux5: interrupt-controller@d4282154 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <5>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x154 0x4>, <0x16c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux9: interrupt-controller@d4282180 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <9>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x180 0x4>, <0x17c 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <3>;
+			};
+
+			intcmux17: interrupt-controller@d4282158 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <17>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x158 0x4>, <0x170 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <5>;
+			};
+
+			intcmux35: interrupt-controller@d428215c {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <35>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x15c 0x4>, <0x174 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <15>;
+			};
+
+			intcmux51: interrupt-controller@d4282160 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <51>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x160 0x4>, <0x178 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+
+			intcmux55: interrupt-controller@d4282188 {
+				compatible = "mrvl,mmp2-mux-intc";
+				interrupts = <55>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x188 0x4>, <0x174 0x4>;
+				reg-names = "mux status", "mux mask";
+				mrvl,intc-nr-irqs = <2>;
+			};
+		};
+
+		apb@d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer@d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
+			uart1: uart@d4030000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4030000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart@d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart@d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <24>;
+				status = "disabled";
+			};
+
+			uart4: uart@d4016000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4016000 0x1000>;
+				interrupts = <46>;
+				status = "disabled";
+			};
+
+			gpio@d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio@d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio@d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio@d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio@d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+
+				gcb4: gpio@d4019104 {
+					reg = <0xd4019104 0x4>;
+				};
+
+				gcb5: gpio@d4019108 {
+					reg = <0xd4019108 0x4>;
+				};
+			};
+
+			twsi1: i2c@d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c@d4025000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4025000 0x1000>;
+				interrupts = <58>;
+				status = "disabled";
+			};
+
+			rtc: rtc@d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <1 0>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				interrupt-parent = <&intcmux5>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d512..31a7186 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
 		i2c1 = &twsi2;
 	};
 
-	intc: intc-interrupt-controller@d4282000 {
-		compatible = "mrvl,mmp-intc", "mrvl,intc";
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		reg = <0xd4282000 0x1000>;
-	};
-
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -32,6 +25,23 @@
 		interrupt-parent = <&intc>;
 		ranges;
 
+		axi@d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller@d4282000 {
+				compatible = "mrvl,mmp-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+		};
+
 		apb@d4000000 {	/* APB */
 			compatible = "mrvl,apb-bus", "simple-bus";
 			#address-cells = <1>;
@@ -39,40 +49,65 @@
 			reg = <0xd4000000 0x00200000>;
 			ranges;
 
+			timer0: timer@d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
 			uart1: uart@d4017000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4017000 0x1000>;
 				interrupts = <27>;
 				status = "disabled";
 			};
 
 			uart2: uart@d4018000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4018000 0x1000>;
 				interrupts = <28>;
 				status = "disabled";
 			};
 
 			uart3: uart@d4026000 {
-				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				compatible = "mrvl,mmp-uart";
 				reg = <0xd4026000 0x1000>;
 				interrupts = <29>;
 				status = "disabled";
 			};
 
-			gpio: gpio@d4019000 {
-				compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+			gpio@d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
 				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
 				interrupts = <49>;
 				interrupt-names = "gpio_mux";
-				gpio-controller;
-				#gpio-cells = <1>;
 				interrupt-controller;
 				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio@d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio@d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio@d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio@d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
 			};
 
 			twsi1: i2c@d4011000 {
-				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				compatible = "mrvl,mmp-twsi";
 				reg = <0xd4011000 0x1000>;
 				interrupts = <7>;
 				mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
 			};
 
 			twsi2: i2c@d4025000 {
-				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				compatible = "mrvl,mmp-twsi";
 				reg = <0xd4025000 0x1000>;
 				interrupts = <58>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 0000000..e92be5a
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa910.dtsi"
+
+/ {
+	model = "Marvell PXA910 DKB Development Board";
+	compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc {
+		apb@d4000000 {
+			uart1: uart@d4017000 {
+				status = "okay";
+			};
+			twsi1: i2c@d4011000 {
+				status = "okay";
+			};
+			rtc: rtc@d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 0000000..aebf32d
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		axi@d4200000 {	/* AXI */
+			compatible = "mrvl,axi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4200000 0x00200000>;
+			ranges;
+
+			intc: interrupt-controller@d4282000 {
+				compatible = "mrvl,mmp-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xd4282000 0x1000>;
+				mrvl,intc-nr-irqs = <64>;
+			};
+
+		};
+
+		apb@d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			timer0: timer@d4014000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4014000 0x100>;
+				interrupts = <13>;
+			};
+
+			timer1: timer@d4016000 {
+				compatible = "mrvl,mmp-timer";
+				reg = <0xd4016000 0x100>;
+				interrupts = <29>;
+				status = "disabled";
+			};
+
+			uart1: uart@d4017000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart@d4018000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart@d4036000 {
+				compatible = "mrvl,mmp-uart";
+				reg = <0xd4036000 0x1000>;
+				interrupts = <59>;
+				status = "disabled";
+			};
+
+			gpio@d4019000 {
+				compatible = "mrvl,mmp-gpio";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0xd4019000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				ranges;
+
+				gcb0: gpio@d4019000 {
+					reg = <0xd4019000 0x4>;
+				};
+
+				gcb1: gpio@d4019004 {
+					reg = <0xd4019004 0x4>;
+				};
+
+				gcb2: gpio@d4019008 {
+					reg = <0xd4019008 0x4>;
+				};
+
+				gcb3: gpio@d4019100 {
+					reg = <0xd4019100 0x4>;
+				};
+			};
+
+			twsi1: i2c@d4011000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c@d4037000 {
+				compatible = "mrvl,mmp-twsi";
+				reg = <0xd4037000 0x1000>;
+				interrupts = <54>;
+				status = "disabled";
+			};
+
+			rtc: rtc@d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <5 6>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.5.4

[PATCH 9/9] Documentation: update docs for mmp dt

[Haojian Zhuang]

Append interrupt controller and timer document for mmp. Updates
documents for gpio and i2c.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 ---
 .../devicetree/bindings/arm/mrvl/intc.txt          |   38 ++++++++++++++++++++
 .../devicetree/bindings/arm/mrvl/mrvl.txt          |   14 +++++++
 .../devicetree/bindings/arm/mrvl/timer.txt         |   13 +++++++
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   18 ++++++---
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   15 +++-----
 6 files changed, 83 insertions(+), 21 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/timer.txt

diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl.txt
deleted file mode 100644
index d8de933..0000000
--- a/Documentation/devicetree/bindings/arm/mrvl.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Marvell Platforms Device Tree Bindings
-----------------------------------------------------
-
-PXA168 Aspenite Board
-Required root node properties:
-	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
new file mode 100644
index 0000000..b81e396
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
@@ -0,0 +1,38 @@
+* Marvell MMP Interrupt controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
+  "mrvl,mmp2-mux-intc"
+- reg : Address and length of the register set of the interrupt controller.
+  If the interrupt controller is intc, address and length means the range
+  of the whold interrupt controller. If the interrupt controller is mux-intc,
+  address and length means one register. Since address of mux-intc is in the
+  range of intc. mux-intc is secondary interrupt controller.
+- reg-names : Name of the register set of the interrupt controller. It's
+  only required in mux-intc interrupt controller.
+- interrupts : Should be the port interrupt shared by mux interrupts. It's
+  only required in mux-intc interrupt controller.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.
+- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
+  controller.
+
+Example:
+	intc: interrupt-controller at d4282000 {
+		compatible = "mrvl,mmp2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xd4282000 0x1000>;
+		mrvl,intc-nr-irqs = <64>;
+	};
+
+	intcmux4 at d4282150 {
+		compatible = "mrvl,mmp2-mux-intc";
+		interrupts = <4>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x150 0x4>, <0x168 0x4>;
+		reg-names = "mux status", "mux mask";
+		mrvl,intc-nr-irqs = <2>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
new file mode 100644
index 0000000..117d741
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
@@ -0,0 +1,14 @@
+Marvell Platforms Device Tree Bindings
+----------------------------------------------------
+
+PXA168 Aspenite Board
+Required root node properties:
+	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+PXA910 DKB Board
+Required root node properties:
+	- compatible = "mrvl,pxa910-dkb";
+
+MMP2 Brownstone Board
+Required root node properties:
+	- compatible = "mrvl,mmp2-brownstone";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
new file mode 100644
index 0000000..9a6e251
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
@@ -0,0 +1,13 @@
+* Marvell MMP Timer controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-timer".
+- reg : Address and length of the register set of timer controller.
+- interrupts : Should be the interrupt number.
+
+Example:
+	timer0: timer at d4014000 {
+		compatible = "mrvl,mmp-timer";
+		reg = <0xd4014000 0x100>;
+		interrupts = <13>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 1e34cfe..05428f3 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -3,19 +3,25 @@
 Required properties:
 - compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
 - reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all gpio pins, if
-- interrupt-name : Should be the name of irq resource.
-  one number.
+- interrupts : Should be the port interrupt shared by all gpio pins.
+  There're three gpio interrupts in arch-pxa, and they're gpio0,
+  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
+  gpio_mux.
+- interrupt-name : Should be the name of irq resource. Each interrupt
+  binds its interrupt-name.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source.
 - gpio-controller : Marks the device node as a gpio controller.
 - #gpio-cells : Should be one.  It is the pin number.
 
 Example:
 
 	gpio: gpio at d4019000 {
-		compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+		compatible = "mrvl,mmp-gpio";
 		reg = <0xd4019000 0x1000>;
-		interrupts = <49>, <17>, <18>;
-		interrupt-name = "gpio_mux", "gpio0", "gpio1";
+		interrupts = <49>;
+		interrupt-name = "gpio_mux";
 		gpio-controller;
 		#gpio-cells = <1>;
 		interrupt-controller;
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
index 071eb3c..b891ee2 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -3,34 +3,31 @@
 Required properties :
 
  - reg : Offset and length of the register set for the device
- - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+ - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
    compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
    For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
    as shown in the example below.
 
 Recommended properties :
 
- - interrupts : <a b> where a is the interrupt number and b is a
-   field that represents an encoding of the sense and level
-   information for the interrupt.  This should be encoded based on
-   the information in section 2) depending on the type of interrupt
-   controller you have.
+ - interrupts : the interrupt number
  - interrupt-parent : the phandle for the interrupt controller that
-   services interrupts for this device.
+   services interrupts for this device. If the parent is the default
+   interrupt controller in device tree, it could be ignored.
  - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
    status register of i2c controller instead.
  - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
 
 Examples:
 	twsi1: i2c at d4011000 {
-		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		compatible = "mrvl,mmp-twsi";
 		reg = <0xd4011000 0x1000>;
 		interrupts = <7>;
 		mrvl,i2c-fast-mode;
 	};
 	
 	twsi2: i2c at d4025000 {
-		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		compatible = "mrvl,mmp-twsi";
 		reg = <0xd4025000 0x1000>;
 		interrupts = <58>;
 	};
-- 
1.7.5.4

[PATCH 9/9] Documentation: update docs for mmp dt

[Haojian Zhuang]

Append interrupt controller and timer document for mmp. Updates
documents for gpio and i2c.

Signed-off-by: Haojian Zhuang <haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 ---
 .../devicetree/bindings/arm/mrvl/intc.txt          |   38 ++++++++++++++++++++
 .../devicetree/bindings/arm/mrvl/mrvl.txt          |   14 +++++++
 .../devicetree/bindings/arm/mrvl/timer.txt         |   13 +++++++
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   18 ++++++---
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   15 +++-----
 6 files changed, 83 insertions(+), 21 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/timer.txt

diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl.txt
deleted file mode 100644
index d8de933..0000000
--- a/Documentation/devicetree/bindings/arm/mrvl.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Marvell Platforms Device Tree Bindings
-----------------------------------------------------
-
-PXA168 Aspenite Board
-Required root node properties:
-	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
new file mode 100644
index 0000000..b81e396
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
@@ -0,0 +1,38 @@
+* Marvell MMP Interrupt controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
+  "mrvl,mmp2-mux-intc"
+- reg : Address and length of the register set of the interrupt controller.
+  If the interrupt controller is intc, address and length means the range
+  of the whold interrupt controller. If the interrupt controller is mux-intc,
+  address and length means one register. Since address of mux-intc is in the
+  range of intc. mux-intc is secondary interrupt controller.
+- reg-names : Name of the register set of the interrupt controller. It's
+  only required in mux-intc interrupt controller.
+- interrupts : Should be the port interrupt shared by mux interrupts. It's
+  only required in mux-intc interrupt controller.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.
+- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
+  controller.
+
+Example:
+	intc: interrupt-controller@d4282000 {
+		compatible = "mrvl,mmp2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xd4282000 0x1000>;
+		mrvl,intc-nr-irqs = <64>;
+	};
+
+	intcmux4@d4282150 {
+		compatible = "mrvl,mmp2-mux-intc";
+		interrupts = <4>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x150 0x4>, <0x168 0x4>;
+		reg-names = "mux status", "mux mask";
+		mrvl,intc-nr-irqs = <2>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
new file mode 100644
index 0000000..117d741
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
@@ -0,0 +1,14 @@
+Marvell Platforms Device Tree Bindings
+----------------------------------------------------
+
+PXA168 Aspenite Board
+Required root node properties:
+	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+PXA910 DKB Board
+Required root node properties:
+	- compatible = "mrvl,pxa910-dkb";
+
+MMP2 Brownstone Board
+Required root node properties:
+	- compatible = "mrvl,mmp2-brownstone";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
new file mode 100644
index 0000000..9a6e251
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
@@ -0,0 +1,13 @@
+* Marvell MMP Timer controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-timer".
+- reg : Address and length of the register set of timer controller.
+- interrupts : Should be the interrupt number.
+
+Example:
+	timer0: timer@d4014000 {
+		compatible = "mrvl,mmp-timer";
+		reg = <0xd4014000 0x100>;
+		interrupts = <13>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 1e34cfe..05428f3 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -3,19 +3,25 @@
 Required properties:
 - compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
 - reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all gpio pins, if
-- interrupt-name : Should be the name of irq resource.
-  one number.
+- interrupts : Should be the port interrupt shared by all gpio pins.
+  There're three gpio interrupts in arch-pxa, and they're gpio0,
+  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
+  gpio_mux.
+- interrupt-name : Should be the name of irq resource. Each interrupt
+  binds its interrupt-name.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source.
 - gpio-controller : Marks the device node as a gpio controller.
 - #gpio-cells : Should be one.  It is the pin number.
 
 Example:
 
 	gpio: gpio@d4019000 {
-		compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+		compatible = "mrvl,mmp-gpio";
 		reg = <0xd4019000 0x1000>;
-		interrupts = <49>, <17>, <18>;
-		interrupt-name = "gpio_mux", "gpio0", "gpio1";
+		interrupts = <49>;
+		interrupt-name = "gpio_mux";
 		gpio-controller;
 		#gpio-cells = <1>;
 		interrupt-controller;
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
index 071eb3c..b891ee2 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -3,34 +3,31 @@
 Required properties :
 
  - reg : Offset and length of the register set for the device
- - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+ - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
    compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
    For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
    as shown in the example below.
 
 Recommended properties :
 
- - interrupts : <a b> where a is the interrupt number and b is a
-   field that represents an encoding of the sense and level
-   information for the interrupt.  This should be encoded based on
-   the information in section 2) depending on the type of interrupt
-   controller you have.
+ - interrupts : the interrupt number
  - interrupt-parent : the phandle for the interrupt controller that
-   services interrupts for this device.
+   services interrupts for this device. If the parent is the default
+   interrupt controller in device tree, it could be ignored.
  - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
    status register of i2c controller instead.
  - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
 
 Examples:
 	twsi1: i2c@d4011000 {
-		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		compatible = "mrvl,mmp-twsi";
 		reg = <0xd4011000 0x1000>;
 		interrupts = <7>;
 		mrvl,i2c-fast-mode;
 	};
 	
 	twsi2: i2c@d4025000 {
-		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		compatible = "mrvl,mmp-twsi";
 		reg = <0xd4025000 0x1000>;
 		interrupts = <58>;
 	};
-- 
1.7.5.4