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* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-25 12:25 Nemesa Garg
  2024-09-25 13:09 ` Jani Nikula
                   ` (9 more replies)
  0 siblings, 10 replies; 49+ messages in thread
From: Nemesa Garg @ 2024-09-25 12:25 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..dfe795b8e917 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,16 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format == DRM_FORMAT_NV12
+		    && src_w % 2 == 0)
+			return -EINVAL;
+
+		hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-30 11:23 Nemesa Garg
  2024-10-15  9:02 ` Kandpal, Suraj
                   ` (2 more replies)
  0 siblings, 3 replies; 49+ messages in thread
From: Nemesa Garg @ 2024-09-30 11:23 UTC (permalink / raw)
  To: intel-gfx; +Cc: Nemesa Garg

Disable the support for odd x pan for even xsize for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

v5: Replace IS_LUNARLAKE with display version.
    Resolve nitpicks[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..e3401a4f7992 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+		/*
+		 *  Wa_16023981245 for display version 20.
+		 *  Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12 &&
+		    src_x % 2 != 0 && src_w % 2 == 0)
+			return -EINVAL;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-30 11:21 Nemesa Garg
  2024-10-16  7:24 ` Nemesa Garg
  0 siblings, 1 reply; 49+ messages in thread
From: Nemesa Garg @ 2024-09-30 11:21 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for even xsize for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

v5: Replace IS_LUNARLAKE with display version.
    Resolve nitpicks[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..e3401a4f7992 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+		/*
+		 *  Wa_16023981245 for display version 20.
+		 *  Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12 &&
+		    src_x % 2 != 0 && src_w % 2 == 0)
+			return -EINVAL;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-25 12:23 Nemesa Garg
  0 siblings, 0 replies; 49+ messages in thread
From: Nemesa Garg @ 2024-09-25 12:23 UTC (permalink / raw)
  To: intel-gfx; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

v4: Modify the condition for hsub [Sai Teja]
    Initialize hsub in else path [Dan]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..dfe795b8e917 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,16 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for even xsize for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format == DRM_FORMAT_NV12
+		    && src_w % 2 == 0)
+			return -EINVAL;
+
+		hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* Re: [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-15  8:15 kernel test robot
  0 siblings, 0 replies; 49+ messages in thread
From: kernel test robot @ 2024-09-15  8:15 UTC (permalink / raw)
  To: oe-kbuild; +Cc: lkp, Dan Carpenter

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20240910143619.143514-1-nemesa.garg@intel.com>
References: <20240910143619.143514-1-nemesa.garg@intel.com>
TO: Nemesa Garg <nemesa.garg@intel.com>
TO: intel-gfx@lists.freedesktop.org
CC: Nemesa Garg <nemesa.garg@intel.com>

Hi Nemesa,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.11-rc7 next-20240913]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Nemesa-Garg/drm-i915-display-Workaround-for-odd-panning-for-planar-yuv/20240910-223820
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20240910143619.143514-1-nemesa.garg%40intel.com
patch subject: [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
:::::: branch date: 5 days ago
:::::: commit date: 5 days ago
config: x86_64-randconfig-161-20240915 (https://download.01.org/0day-ci/archive/20240915/202409151558.ETIW5UMU-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202409151558.ETIW5UMU-lkp@intel.com/

New smatch warnings:
drivers/gpu/drm/i915/display/intel_atomic_plane.c:1045 intel_plane_check_src_coordinates() error: uninitialized symbol 'hsub'.

Old smatch warnings:
drivers/gpu/drm/i915/display/intel_atomic_plane.c:660 intel_plane_atomic_check_with_state() error: we previously assumed 'fb' could be null (see line 648)
drivers/gpu/drm/i915/display/intel_atomic_plane.c:1047 intel_plane_check_src_coordinates() error: uninitialized symbol 'hsub'.

vim +/hsub +1045 drivers/gpu/drm/i915/display/intel_atomic_plane.c

9f05a7c0adb9ee Maarten Lankhorst   2020-11-17   990  
0ec2a5b291af32 Ville Syrjälä       2023-03-14   991  int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
0ec2a5b291af32 Ville Syrjälä       2023-03-14   992  {
0ec2a5b291af32 Ville Syrjälä       2023-03-14   993  	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
0ec2a5b291af32 Ville Syrjälä       2023-03-14   994  	const struct drm_framebuffer *fb = plane_state->hw.fb;
0ec2a5b291af32 Ville Syrjälä       2023-03-14   995  	struct drm_rect *src = &plane_state->uapi.src;
0ec2a5b291af32 Ville Syrjälä       2023-03-14   996  	u32 src_x, src_y, src_w, src_h, hsub, vsub;
0ec2a5b291af32 Ville Syrjälä       2023-03-14   997  	bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
0ec2a5b291af32 Ville Syrjälä       2023-03-14   998  
0ec2a5b291af32 Ville Syrjälä       2023-03-14   999  	/*
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1000  	 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1001  	 * abuses hsub/vsub so we can't use them here. But as they
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1002  	 * are limited to 32bpp RGB formats we don't actually need
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1003  	 * to check anything.
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1004  	 */
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1005  	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1006  	    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1007  		return 0;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1008  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1009  	/*
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1010  	 * Hardware doesn't handle subpixel coordinates.
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1011  	 * Adjust to (macro)pixel boundary, but be careful not to
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1012  	 * increase the source viewport size, because that could
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1013  	 * push the downscaling factor out of bounds.
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1014  	 */
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1015  	src_x = src->x1 >> 16;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1016  	src_w = drm_rect_width(src) >> 16;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1017  	src_y = src->y1 >> 16;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1018  	src_h = drm_rect_height(src) >> 16;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1019  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1020  	drm_rect_init(src, src_x << 16, src_y << 16,
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1021  		      src_w << 16, src_h << 16);
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1022  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1023  	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1024  		hsub = 2;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1025  		vsub = 2;
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1026  	} else if (DISPLAY_VER(i915) >= 20 &&
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1027  		   intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1028  		/*
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1029  		 * This allows NV12 and P0xx formats to have odd size and/or odd
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1030  		 * source coordinates on DISPLAY_VER(i915) >= 20
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1031  		 */
533a7836d39f1a Juha-Pekka Heikkilä 2023-09-19  1032  		vsub = 1;
68f459ad919373 Nemesa Garg         2024-09-10  1033  		/*
68f459ad919373 Nemesa Garg         2024-09-10  1034  		 * Wa_16023981245 for display version 20.
68f459ad919373 Nemesa Garg         2024-09-10  1035  		 * Do not support odd x-panning for NV12.
68f459ad919373 Nemesa Garg         2024-09-10  1036  		 */
68f459ad919373 Nemesa Garg         2024-09-10  1037  		if (IS_LUNARLAKE(i915) && fb->format->format != DRM_FORMAT_NV12)
68f459ad919373 Nemesa Garg         2024-09-10  1038  			hsub = 1;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1039  	} else {
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1040  		hsub = fb->format->hsub;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1041  		vsub = fb->format->vsub;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1042  	}
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1043  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1044  	if (rotated)
0ec2a5b291af32 Ville Syrjälä       2023-03-14 @1045  		hsub = vsub = max(hsub, vsub);
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1046  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1047  	if (src_x % hsub || src_w % hsub) {
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1048  		drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1049  			    src_x, src_w, hsub, str_yes_no(rotated));
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1050  		return -EINVAL;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1051  	}
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1052  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1053  	if (src_y % vsub || src_h % vsub) {
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1054  		drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1055  			    src_y, src_h, vsub, str_yes_no(rotated));
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1056  		return -EINVAL;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1057  	}
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1058  
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1059  	return 0;
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1060  }
0ec2a5b291af32 Ville Syrjälä       2023-03-14  1061  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-10 14:37 Nemesa Garg
  2024-09-10 16:36 ` Pottumuttu, Sai Teja
  0 siblings, 1 reply; 49+ messages in thread
From: Nemesa Garg @ 2024-09-10 14:37 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..4afe808f128c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,13 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format != DRM_FORMAT_NV12)
+			hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-10 14:36 Nemesa Garg
  2024-09-15 12:20 ` Dan Carpenter
  0 siblings, 1 reply; 49+ messages in thread
From: Nemesa Garg @ 2024-09-10 14:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

v2: Replace HSD with WA in commit message [Suraj]
    Modified the condition for handling odd panning

v3: Simplified the condition for checking hsub
    Using older framework for wa as rev1[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..4afe808f128c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,8 +1029,13 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
 		vsub = 1;
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (IS_LUNARLAKE(i915) && fb->format->format != DRM_FORMAT_NV12)
+			hsub = 1;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-06  7:01 Nemesa Garg
  2024-09-06  8:51 ` Jani Nikula
  0 siblings, 1 reply; 49+ messages in thread
From: Nemesa Garg @ 2024-09-06  7:01 UTC (permalink / raw)
  To: intel-xe; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    | 16 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display_wa.h  |  2 ++
 drivers/gpu/drm/xe/display/xe_display_wa.c       |  5 +++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..9b17321f3477 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -47,11 +47,13 @@
 #include "intel_display_rps.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_fb.h"
 #include "intel_fb_pin.h"
 #include "skl_scaler.h"
 #include "skl_watermark.h"
 
+
 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
 				    struct intel_plane *plane)
 {
@@ -1029,8 +1031,18 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
-		vsub = 1;
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (intel_display_needs_wa_16023981245(i915) &&
+		    fb->format->format == DRM_FORMAT_NV12) {
+			vsub = 1;
+		} else {
+			hsub = 1;
+			vsub = 1;
+		}
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index be644ab6ae00..9be35a751503 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -14,8 +14,10 @@ void intel_display_wa_apply(struct drm_i915_private *i915);
 
 #ifdef I915
 static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; }
+static inline bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915) { return false; }
 #else
 bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915);
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915);
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c
index 68e3d1959ad6..fde4e09589a3 100644
--- a/drivers/gpu/drm/xe/display/xe_display_wa.c
+++ b/drivers/gpu/drm/xe/display/xe_display_wa.c
@@ -14,3 +14,8 @@ bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915)
 {
 	return XE_WA(xe_root_mmio_gt(i915), 16023588340);
 }
+
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915)
+{
+	return XE_WA(xe_root_mmio_gt(i915), 22019338487_display);
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-09-06  7:00 Nemesa Garg
  0 siblings, 0 replies; 49+ messages in thread
From: Nemesa Garg @ 2024-09-06  7:00 UTC (permalink / raw)
  To: intel-gfx; +Cc: Nemesa Garg

Disable the support for odd x pan for NV12 format as underrun
issue is seen.

WA: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    | 16 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display_wa.h  |  2 ++
 drivers/gpu/drm/xe/display/xe_display_wa.c       |  5 +++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..9b17321f3477 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -47,11 +47,13 @@
 #include "intel_display_rps.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_fb.h"
 #include "intel_fb_pin.h"
 #include "skl_scaler.h"
 #include "skl_watermark.h"
 
+
 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
 				    struct intel_plane *plane)
 {
@@ -1029,8 +1031,18 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
-		hsub = 1;
-		vsub = 1;
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Do not support odd x-panning for NV12.
+		 */
+		if (intel_display_needs_wa_16023981245(i915) &&
+		    fb->format->format == DRM_FORMAT_NV12) {
+			vsub = 1;
+		} else {
+			hsub = 1;
+			vsub = 1;
+		}
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index be644ab6ae00..9be35a751503 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -14,8 +14,10 @@ void intel_display_wa_apply(struct drm_i915_private *i915);
 
 #ifdef I915
 static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; }
+static inline bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915) { return false; }
 #else
 bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915);
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915);
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c
index 68e3d1959ad6..fde4e09589a3 100644
--- a/drivers/gpu/drm/xe/display/xe_display_wa.c
+++ b/drivers/gpu/drm/xe/display/xe_display_wa.c
@@ -14,3 +14,8 @@ bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915)
 {
 	return XE_WA(xe_root_mmio_gt(i915), 16023588340);
 }
+
+bool intel_display_needs_wa_16023981245(struct drm_i915_private *i915)
+{
+	return XE_WA(xe_root_mmio_gt(i915), 22019338487_display);
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-07-24 13:06 Nemesa Garg
  2024-07-24 17:01 ` Kandpal, Suraj
  0 siblings, 1 reply; 49+ messages in thread
From: Nemesa Garg @ 2024-07-24 13:06 UTC (permalink / raw)
  To: intel-xe; +Cc: juha-pekka.heikkila, uma.shankar, Nemesa Garg

Underrun/corruption issue is seen for NV12 format
for odd panning on LNL due to hardware bug.
Disable the format.

HSD: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..f927e6a0b28b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Disable odd pan for NV12 format.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12)
+			return 0;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
* [PATCH] drm/i915/display: Workaround for odd panning for planar yuv
@ 2024-07-24 11:30 Nemesa Garg
  0 siblings, 0 replies; 49+ messages in thread
From: Nemesa Garg @ 2024-07-24 11:30 UTC (permalink / raw)
  To: intel-gfx; +Cc: juha-pekka.heikkila, uma.shankar, Nemesa Garg

Underrun/corruption issue is seen for NV12 format
for odd panning on LNL due to hardware bug.
Disable the format.

HSD: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..f927e6a0b28b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Disable odd pan for NV12 format.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12)
+			return 0;
+
 		hsub = 1;
 		vsub = 1;
 	} else {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 49+ messages in thread
end of thread, other threads:[~2024-10-18 17:36 UTC | newest]

Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-25 12:25 [PATCH] drm/i915/display: Workaround for odd panning for planar yuv Nemesa Garg
2024-09-25 13:09 ` Jani Nikula
2024-09-25 13:57 ` Pottumuttu, Sai Teja
2024-09-26 13:34 ` ✓ CI.Patch_applied: success for drm/i915/display: Workaround for odd panning for planar yuv (rev4) Patchwork
2024-09-26 13:34 ` ✗ CI.checkpatch: warning " Patchwork
2024-09-26 13:36 ` ✓ CI.KUnit: success " Patchwork
2024-09-26 13:53 ` ✓ CI.Build: " Patchwork
2024-09-26 13:55 ` ✓ CI.Hooks: " Patchwork
2024-09-26 13:56 ` ✗ CI.checksparse: warning " Patchwork
2024-09-26 14:38 ` ✗ CI.BAT: failure " Patchwork
2024-09-27  9:59 ` ✗ CI.FULL: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-09-30 11:23 [PATCH] drm/i915/display: Workaround for odd panning for planar yuv Nemesa Garg
2024-10-15  9:02 ` Kandpal, Suraj
2024-10-15 13:21   ` Garg, Nemesa
2024-10-15 14:53     ` Kandpal, Suraj
2024-10-15 16:23       ` Garg, Nemesa
2024-10-16  4:25         ` Kandpal, Suraj
2024-10-16  6:26           ` Garg, Nemesa
2024-10-15  9:25 ` Kandpal, Suraj
2024-10-15 13:23   ` Garg, Nemesa
2024-10-15 14:47     ` Kandpal, Suraj
2024-10-16  7:22 ` Nemesa Garg
2024-09-30 11:21 Nemesa Garg
2024-10-16  7:24 ` Nemesa Garg
2024-10-17  8:05   ` Kandpal, Suraj
2024-10-17 16:53     ` Pottumuttu, Sai Teja
2024-10-18  5:04       ` Garg, Nemesa
2024-10-18  5:05         ` Garg, Nemesa
2024-10-18  5:44         ` Chauhan, Shekhar
2024-10-18 17:36           ` Matt Roper
2024-09-25 12:23 Nemesa Garg
2024-09-15  8:15 kernel test robot
2024-09-10 14:37 Nemesa Garg
2024-09-10 16:36 ` Pottumuttu, Sai Teja
2024-09-25  7:49   ` Garg, Nemesa
2024-09-10 14:36 Nemesa Garg
2024-09-15 12:20 ` Dan Carpenter
2024-09-06  7:01 Nemesa Garg
2024-09-06  8:51 ` Jani Nikula
2024-09-06  9:07   ` Jani Nikula
2024-09-06 13:51   ` Lucas De Marchi
2024-09-06 14:18     ` Jani Nikula
2024-09-06 15:33       ` Rodrigo Vivi
2024-09-06  7:00 Nemesa Garg
2024-07-24 13:06 Nemesa Garg
2024-07-24 17:01 ` Kandpal, Suraj
2024-07-25  2:59   ` Kandpal, Suraj
2024-08-12  5:18     ` Garg, Nemesa
2024-07-24 11:30 Nemesa Garg

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