From: Jani Nikula <jani.nikula@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: uma.shankar@intel.com
Subject: Re: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers
Date: Mon, 13 May 2024 14:53:45 +0300 [thread overview]
Message-ID: <874jb2exme.fsf@intel.com> (raw)
In-Reply-To: <20240509075833.1858363-2-mitulkumar.ajitkumar.golani@intel.com>
On Thu, 09 May 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add register definitions for Transcoder Fixed Average
> Vtotal mode/CMRR function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending
> Adaptive refresh rate capabilities.
>
> --v2:
> - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
> - Fix indent and order based on register offset. [Jani]
How does this match with...
>
> +#define _TRANS_CMRR_M_LO_A 0x604F0
> +#define _TRANS_CMRR_M_HI_A 0x604F4
> +#define _TRANS_CMRR_N_LO_A 0x604F8
> +#define _TRANS_CMRR_N_HI_A 0x604FC
> +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
> +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
> +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
> +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
> +
...this?
Please read the comment at the top of i915_reg.h
BR,
Jani.
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-05-13 11:53 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 7:58 [PATCH v8 0/7] Implement CMRR Support Mitul Golani
2024-05-09 7:58 ` [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-05-13 6:59 ` Murthy, Arun R
2024-05-13 11:54 ` Jani Nikula
2024-05-13 11:53 ` Jani Nikula [this message]
2024-05-09 7:58 ` [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
2024-05-13 11:20 ` Murthy, Arun R
2024-05-09 7:58 ` [PATCH v8 3/7] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-05-11 0:46 ` kernel test robot
2024-05-17 10:38 ` Murthy, Arun R
2024-05-23 11:21 ` Nautiyal, Ankit K
2024-05-09 7:58 ` [PATCH v8 4/7] Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-05-20 3:27 ` Murthy, Arun R
2024-05-09 7:58 ` [PATCH v8 5/7] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-05-23 11:31 ` Nautiyal, Ankit K
2024-05-09 7:58 ` [PATCH v8 6/7] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-05-09 7:58 ` [PATCH v8 7/7] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-05-23 11:38 ` Nautiyal, Ankit K
2024-05-09 8:31 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev8) Patchwork
2024-05-09 8:32 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-09 8:38 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-09 19:42 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-10 7:36 ` Patchwork
2024-05-10 8:05 ` ✓ Fi.CI.IGT: success " Patchwork
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