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From: Thomas Gleixner <tglx@linutronix.de>
To: Xu Lu <luxu.kernel@bytedance.com>, Atish Patra <atishp@atishpatra.org>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, maz@kernel.org, anup@brainfault.org,
	dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
	sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
	lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Clément Léger" <cleger@rivosinc.com>
Subject: Re: [External] Re: [RFC 00/12] riscv: Introduce Pseudo NMI
Date: Fri, 27 Oct 2023 09:55:19 +0200	[thread overview]
Message-ID: <874jic4hzs.ffs@tglx> (raw)
In-Reply-To: <CAPYmKFuNr18_jJYZ6X4Rrty=bU0cXiuHpAqSt2+YqDWV6rAveg@mail.gmail.com>

On Thu, Oct 26 2023 at 21:56, Xu Lu wrote:
> On Thu, Oct 26, 2023 at 7:02 AM Atish Patra <atishp@atishpatra.org> wrote:
> First, please allow me to explain that CSR_IE Pseudo NMI actually can support
> more than PMU profiling. For example, if we choose to make external major
> interrupt as NMI and use ithreshold or eithreshold in AIA to control which minor
> external interrupts can be sent to CPU, then we actually can support multiple
> minor interrupts as NMI while keeping the other minor interrupts still
> normal irqs.

What is the use case for these NMIs? Anything else than profiling is not
really possible in NMI context at all.

Thanks,

        tglx

_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Xu Lu <luxu.kernel@bytedance.com>, Atish Patra <atishp@atishpatra.org>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, maz@kernel.org, anup@brainfault.org,
	dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
	sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
	lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Clément Léger" <cleger@rivosinc.com>
Subject: Re: [External] Re: [RFC 00/12] riscv: Introduce Pseudo NMI
Date: Fri, 27 Oct 2023 09:55:19 +0200	[thread overview]
Message-ID: <874jic4hzs.ffs@tglx> (raw)
In-Reply-To: <CAPYmKFuNr18_jJYZ6X4Rrty=bU0cXiuHpAqSt2+YqDWV6rAveg@mail.gmail.com>

On Thu, Oct 26 2023 at 21:56, Xu Lu wrote:
> On Thu, Oct 26, 2023 at 7:02 AM Atish Patra <atishp@atishpatra.org> wrote:
> First, please allow me to explain that CSR_IE Pseudo NMI actually can support
> more than PMU profiling. For example, if we choose to make external major
> interrupt as NMI and use ithreshold or eithreshold in AIA to control which minor
> external interrupts can be sent to CPU, then we actually can support multiple
> minor interrupts as NMI while keeping the other minor interrupts still
> normal irqs.

What is the use case for these NMIs? Anything else than profiling is not
really possible in NMI context at all.

Thanks,

        tglx

  parent reply	other threads:[~2023-10-27  7:55 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23  8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23  8:28 ` Xu Lu
2023-10-23  8:29 ` [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 09/12] riscv: Enable NMIs during exceptions Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 10/12] riscv: Enable NMIs during interrupt handling Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-23  8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-23  8:29   ` Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-25 23:01   ` Atish Patra
2023-10-26 13:56   ` [External] " Xu Lu
2023-10-26 13:56     ` Xu Lu
2023-10-26 19:41     ` Atish Patra
2023-10-26 19:41       ` Atish Patra
2023-10-27  7:33       ` Xu Lu
2023-10-27  7:33         ` Xu Lu
2023-10-27  7:55     ` Thomas Gleixner [this message]
2023-10-27  7:55       ` Thomas Gleixner

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