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From: Marc Zyngier <maz@kernel.org>
To: Yicong Yang <yangyicong@huawei.com>
Cc: <mark.rutland@arm.com>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <daniel.lezcano@linaro.org>,
	<tglx@linutronix.de>, <jonathan.cameron@huawei.com>,
	<prime.zeng@huawei.com>, <wanghuiqiang@huawei.com>,
	<wangwudi@hisilicon.com>, <guohanjun@huawei.com>,
	<yangyicong@hisilicon.com>, <linuxarm@huawei.com>
Subject: Re: [RFC PATCH 0/3] Add HiSilicon system timer driver
Date: Tue, 10 Oct 2023 17:36:50 +0100	[thread overview]
Message-ID: <874jiymo2l.wl-maz@kernel.org> (raw)
In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com>

On Tue, 10 Oct 2023 13:30:30 +0100,
Yicong Yang <yangyicong@huawei.com> wrote:
> 
> From: Yicong Yang <yangyicong@hisilicon.com>
> 
> HiSilicon system timer is a memory mapped platform timer compatible with
> the arm's generic timer specification. The timer supports both SPI and
> LPI interrupt and can be enumerated through ACPI DSDT table. Since the
> timer is fully compatible with the spec, it can reuse most codes of the
> arm_arch_timer driver. However since the arm_arch_timer driver only
> supports GTDT and SPI interrupt, this series support the HiSilicon system
> timer by:
> 
> - refactor some of the arm_arch_timer codes and export the function to
>   register a arch memory timer by other drivers
> - retrieve the IO memory and interrupt resource through DSDT in a separate
>   driver, then setup and register the clockevent device reuse the arm_arch_timer
>   function
> 
> Using LPI for the timer is mentioned in BSA Spec section 3.8.1 (DEN0094C 1.0C).

This strikes me as pretty odd. LPIs are, by definition, *edge*
triggered. The timer interrupt must be *level* triggered. So there
must be some bridge in the middle that is going to regenerate edges on
EOI, and that cannot be architectural.

What am I missing?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Yicong Yang <yangyicong@huawei.com>
Cc: <mark.rutland@arm.com>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <daniel.lezcano@linaro.org>,
	<tglx@linutronix.de>, <jonathan.cameron@huawei.com>,
	<prime.zeng@huawei.com>, <wanghuiqiang@huawei.com>,
	<wangwudi@hisilicon.com>, <guohanjun@huawei.com>,
	<yangyicong@hisilicon.com>, <linuxarm@huawei.com>
Subject: Re: [RFC PATCH 0/3] Add HiSilicon system timer driver
Date: Tue, 10 Oct 2023 17:36:50 +0100	[thread overview]
Message-ID: <874jiymo2l.wl-maz@kernel.org> (raw)
In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com>

On Tue, 10 Oct 2023 13:30:30 +0100,
Yicong Yang <yangyicong@huawei.com> wrote:
> 
> From: Yicong Yang <yangyicong@hisilicon.com>
> 
> HiSilicon system timer is a memory mapped platform timer compatible with
> the arm's generic timer specification. The timer supports both SPI and
> LPI interrupt and can be enumerated through ACPI DSDT table. Since the
> timer is fully compatible with the spec, it can reuse most codes of the
> arm_arch_timer driver. However since the arm_arch_timer driver only
> supports GTDT and SPI interrupt, this series support the HiSilicon system
> timer by:
> 
> - refactor some of the arm_arch_timer codes and export the function to
>   register a arch memory timer by other drivers
> - retrieve the IO memory and interrupt resource through DSDT in a separate
>   driver, then setup and register the clockevent device reuse the arm_arch_timer
>   function
> 
> Using LPI for the timer is mentioned in BSA Spec section 3.8.1 (DEN0094C 1.0C).

This strikes me as pretty odd. LPIs are, by definition, *edge*
triggered. The timer interrupt must be *level* triggered. So there
must be some bridge in the middle that is going to regenerate edges on
EOI, and that cannot be architectural.

What am I missing?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

  parent reply	other threads:[~2023-10-10 16:37 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10 12:30 [RFC PATCH 0/3] Add HiSilicon system timer driver Yicong Yang
2023-10-10 12:30 ` Yicong Yang
2023-10-10 12:30 ` [RFC PATCH 1/3] clocksource/drivers/arm_arch_timer: Split the function of __arch_timer_setup() Yicong Yang
2023-10-10 12:30   ` Yicong Yang
2023-10-10 12:30 ` [RFC PATCH 2/3] clocksource/drivers/arm_arch_timer: Extend and export arch_timer_mem_register() Yicong Yang
2023-10-10 12:30   ` Yicong Yang
2023-10-10 12:30 ` [RFC PATCH 3/3] clocksource/drivers: Add HiSilicon system timer driver Yicong Yang
2023-10-10 12:30   ` Yicong Yang
2023-10-10 15:43 ` [RFC PATCH 0/3] " Mark Rutland
2023-10-10 15:43   ` Mark Rutland
2023-10-11  2:07   ` Yicong Yang
2023-10-11  2:07     ` Yicong Yang
2023-10-10 16:36 ` Marc Zyngier [this message]
2023-10-10 16:36   ` Marc Zyngier
2023-10-11  2:10   ` Yicong Yang
2023-10-11  2:10     ` Yicong Yang
2023-10-11 10:38     ` Mark Rutland
2023-10-11 10:38       ` Mark Rutland
2023-10-11 13:10       ` Yicong Yang
2023-10-11 13:10         ` Yicong Yang
2024-01-23  9:35         ` Yicong Yang
2024-01-23  9:35           ` Yicong Yang

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