From: "Keith Packard" <keithp@keithp.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm <qemu-arm@nongnu.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *
Date: Wed, 11 Nov 2020 14:55:11 -0800 [thread overview]
Message-ID: <874klvh5bk.fsf@keithp.com> (raw)
In-Reply-To: <CAKmqyKP5JpriojRqDNy=SqqkXtg=y39P5xNoMrSsoWhfz8xeaw@mail.gmail.com>
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Alistair Francis <alistair23@gmail.com> writes:
> I'm not sure common is the right name here, as it is really just ARM
> and RISC-V, but I don't have a better name to use.
We've already seen some interest for other architectures; Benjamin
Herrenschmidt was looking at using this for PPC, for instance. He got
stuck at the same point -- attempting to split out this
architecture-neutral code.
In any case, naming is hard, and if anyone has suggestions ...
--
-keith
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WARNING: multiple messages have this Message-ID (diff)
From: "Keith Packard" via <qemu-devel@nongnu.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm <qemu-arm@nongnu.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *
Date: Wed, 11 Nov 2020 14:55:11 -0800 [thread overview]
Message-ID: <874klvh5bk.fsf@keithp.com> (raw)
In-Reply-To: <CAKmqyKP5JpriojRqDNy=SqqkXtg=y39P5xNoMrSsoWhfz8xeaw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 484 bytes --]
Alistair Francis <alistair23@gmail.com> writes:
> I'm not sure common is the right name here, as it is really just ARM
> and RISC-V, but I don't have a better name to use.
We've already seen some interest for other architectures; Benjamin
Herrenschmidt was looking at using this for PPC, for instance. He got
stuck at the same point -- attempting to split out this
architecture-neutral code.
In any case, naming is hard, and if anyone has suggestions ...
--
-keith
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
next prev parent reply other threads:[~2020-11-11 22:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 18:57 [PATCH 0/4] Add RISC-V semihosting support Keith Packard
2020-10-28 18:57 ` Keith Packard via
2020-10-28 18:57 ` [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories [v3] Keith Packard
2020-10-28 18:57 ` Keith Packard via
2020-11-09 23:17 ` Alistair Francis
2020-11-09 23:17 ` Alistair Francis
2020-11-10 5:25 ` Keith Packard
2020-11-10 5:25 ` Keith Packard via
2020-10-28 18:57 ` [PATCH 2/4] semihosting: Change common-semi API to be architecture-independent Keith Packard
2020-10-28 18:57 ` Keith Packard via
2020-11-11 22:08 ` Alistair Francis
2020-11-11 22:08 ` Alistair Francis
2020-10-28 18:57 ` [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState * Keith Packard
2020-10-28 18:57 ` Keith Packard via
2020-11-11 22:29 ` Alistair Francis
2020-11-11 22:29 ` Alistair Francis
2020-11-11 22:55 ` Keith Packard [this message]
2020-11-11 22:55 ` Keith Packard via
2020-10-28 18:57 ` [PATCH 4/4] riscv: Add semihosting support [v11] Keith Packard
2020-10-28 18:57 ` Keith Packard via
2020-11-11 22:19 ` Alistair Francis
2020-11-11 22:19 ` Alistair Francis
2020-11-11 22:49 ` Keith Packard
2020-11-11 22:49 ` Keith Packard via
2020-10-28 19:09 ` [PATCH 0/4] Add RISC-V semihosting support no-reply
2020-10-28 19:09 ` no-reply
-- strict thread matches above, loose matches on Subject: below --
2020-10-26 21:28 [PATCH 0/4] riscv: Add semihosting support [v10] Keith Packard
2020-10-26 21:28 ` [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState * Keith Packard
2020-10-26 21:28 ` Keith Packard via
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