[PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

[PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.

Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 618a93bad0a8..6b75d2a91cd9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	u32 divider;
 	int div;
 
+	bxt_de_pll_readout(dev_priv, cdclk_state);
+
 	if (INTEL_GEN(dev_priv) >= 12)
 		cdclk_state->bypass = cdclk_state->ref / 2;
 	else if (INTEL_GEN(dev_priv) >= 11)
@@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	else
 		cdclk_state->bypass = cdclk_state->ref;
 
-	bxt_de_pll_readout(dev_priv, cdclk_state);
 	if (cdclk_state->vco == 0) {
 		cdclk_state->cdclk = cdclk_state->bypass;
 		goto out;
-- 
2.21.0

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[PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're forgetting to mask off all three pipe select bits from the
CDCLK_CTL value on icl+ which may lead to the extra bit being
left in. That will cause us to consider the current hardware
cdclk state as invalid, and we proceed to sanitize it even
though the hardware may have active pipes and whatnot.

Fix up the mask so we get rid of all three pipe select bits
and thus hopefully no longer sanitize cdclk when it's already
correctly programmed.

Cc: Matt Roper <matthew.d.roper@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 42 ++++++++++++----------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6b75d2a91cd9..f59a6f775177 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
 	dev_priv->cdclk.hw.vco = vco;
 }
 
+static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	if (INTEL_GEN(dev_priv) >= 12) {
+		if (pipe == INVALID_PIPE)
+			return TGL_CDCLK_CD2X_PIPE_NONE;
+		else
+			return TGL_CDCLK_CD2X_PIPE(pipe);
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		if (pipe == INVALID_PIPE)
+			return ICL_CDCLK_CD2X_PIPE_NONE;
+		else
+			return ICL_CDCLK_CD2X_PIPE(pipe);
+	} else {
+		if (pipe == INVALID_PIPE)
+			return BXT_CDCLK_CD2X_PIPE_NONE;
+		else
+			return BXT_CDCLK_CD2X_PIPE(pipe);
+	}
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_state *cdclk_state,
 			  enum pipe pipe)
@@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			bxt_de_pll_enable(dev_priv, vco);
 	}
 
-	val = divider | skl_cdclk_decimal(cdclk);
-
-	if (INTEL_GEN(dev_priv) >= 12) {
-		if (pipe == INVALID_PIPE)
-			val |= TGL_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= TGL_CDCLK_CD2X_PIPE(pipe);
-	} else if (INTEL_GEN(dev_priv) >= 11) {
-		if (pipe == INVALID_PIPE)
-			val |= ICL_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= ICL_CDCLK_CD2X_PIPE(pipe);
-	} else {
-		if (pipe == INVALID_PIPE)
-			val |= BXT_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= BXT_CDCLK_CD2X_PIPE(pipe);
-	}
+	val = divider | skl_cdclk_decimal(cdclk) |
+		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
 
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	 * dividers both synching to an active pipe, or asynchronously
 	 * (PIPE_NONE).
 	 */
-	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
+	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
 
 	/* Make sure this is a legal cdclk value for the platform */
 	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
-- 
2.21.0

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Re: [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Matt Roper]

On Wed, Sep 11, 2019 at 04:31:27PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We're forgetting to mask off all three pipe select bits from the
> CDCLK_CTL value on icl+ which may lead to the extra bit being
> left in. That will cause us to consider the current hardware
> cdclk state as invalid, and we proceed to sanitize it even
> though the hardware may have active pipes and whatnot.
> 
> Fix up the mask so we get rid of all three pipe select bits
> and thus hopefully no longer sanitize cdclk when it's already
> correctly programmed.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
> Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

I'm confused why pre-merge CI flagged the results as a success if TGL
was hitting this?


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 42 ++++++++++++----------
>  1 file changed, 23 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6b75d2a91cd9..f59a6f775177 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  	dev_priv->cdclk.hw.vco = vco;
>  }
>  
> +static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		if (pipe == INVALID_PIPE)
> +			return TGL_CDCLK_CD2X_PIPE_NONE;
> +		else
> +			return TGL_CDCLK_CD2X_PIPE(pipe);
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		if (pipe == INVALID_PIPE)
> +			return ICL_CDCLK_CD2X_PIPE_NONE;
> +		else
> +			return ICL_CDCLK_CD2X_PIPE(pipe);
> +	} else {
> +		if (pipe == INVALID_PIPE)
> +			return BXT_CDCLK_CD2X_PIPE_NONE;
> +		else
> +			return BXT_CDCLK_CD2X_PIPE(pipe);
> +	}
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_state *cdclk_state,
>  			  enum pipe pipe)
> @@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			bxt_de_pll_enable(dev_priv, vco);
>  	}
>  
> -	val = divider | skl_cdclk_decimal(cdclk);
> -
> -	if (INTEL_GEN(dev_priv) >= 12) {
> -		if (pipe == INVALID_PIPE)
> -			val |= TGL_CDCLK_CD2X_PIPE_NONE;
> -		else
> -			val |= TGL_CDCLK_CD2X_PIPE(pipe);
> -	} else if (INTEL_GEN(dev_priv) >= 11) {
> -		if (pipe == INVALID_PIPE)
> -			val |= ICL_CDCLK_CD2X_PIPE_NONE;
> -		else
> -			val |= ICL_CDCLK_CD2X_PIPE(pipe);
> -	} else {
> -		if (pipe == INVALID_PIPE)
> -			val |= BXT_CDCLK_CD2X_PIPE_NONE;
> -		else
> -			val |= BXT_CDCLK_CD2X_PIPE(pipe);
> -	}
> +	val = divider | skl_cdclk_decimal(cdclk) |
> +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>  
>  	/*
>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	 * dividers both synching to an active pipe, or asynchronously
>  	 * (PIPE_NONE).
>  	 */
> -	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> +	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
>  
>  	/* Make sure this is a legal cdclk value for the platform */
>  	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Chris Wilson]

Quoting Matt Roper (2019-09-11 16:00:44)
> I'm confused why pre-merge CI flagged the results as a success if TGL
> was hitting this?

We've only just (Fri) got CI's Tigerlake surviving boot, so a second
failure during boot would have been missed. For the summary report,
Tigerlake is currently suppressed as it is not yet proven itself as
being a stable result. (Which is a bit of a nuisance as you have to
remind yourself to actually check the details.)
-Chris
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Re: [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Saarinen, Jani]

HI, 

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Chris
> Wilson
> Sent: keskiviikko 11. syyskuuta 2019 18.09
> To: Roper, Matthew D <matthew.d.roper@intel.com>; Ville Syrjala
> <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during
> cdclk sanitation
> 
> Quoting Matt Roper (2019-09-11 16:00:44)
> > I'm confused why pre-merge CI flagged the results as a success if TGL
> > was hitting this?
> 
> We've only just (Fri) got CI's Tigerlake surviving boot, so a second failure during boot
> would have been missed. For the summary report, Tigerlake is currently suppressed
> as it is not yet proven itself as being a stable result. (Which is a bit of a nuisance as
> you have to remind yourself to actually check the details.) -Chris
Exactly. 

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Jani Nikula]

On Wed, 11 Sep 2019, Matt Roper <matthew.d.roper@intel.com> wrote:
> I'm confused why pre-merge CI flagged the results as a success if TGL
> was hitting this?

I didn't check the specifics, but the full set of IGT tests is only run
on a limited number of platforms, and TGL is not yet one of them. You
get the narrow range of tests on a wide range of platforms and the wide
range of tests on a narrow range of platforms.

BR,
Jani.

-- 
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Re: [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation

[Saarinen, Jani]

HI, 

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Matt
> Roper
> Sent: keskiviikko 11. syyskuuta 2019 18.01
> To: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during
> cdclk sanitation
> 
> On Wed, Sep 11, 2019 at 04:31:27PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We're forgetting to mask off all three pipe select bits from the
> > CDCLK_CTL value on icl+ which may lead to the extra bit being left in.
> > That will cause us to consider the current hardware cdclk state as
> > invalid, and we proceed to sanitize it even though the hardware may
> > have active pipes and whatnot.
> >
> > Fix up the mask so we get rid of all three pipe select bits and thus
> > hopefully no longer sanitize cdclk when it's already correctly
> > programmed.
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
> > Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> I'm confused why pre-merge CI flagged the results as a success if TGL was hitting
> this?
It died also on CI: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/?
Martin, Tomi can you explain? 

> 
> 
> Matt
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 42
> > ++++++++++++----------
> >  1 file changed, 23 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 6b75d2a91cd9..f59a6f775177 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> >  	dev_priv->cdclk.hw.vco = vco;
> >  }
> >
> > +static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv,
> > +enum pipe pipe) {
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		if (pipe == INVALID_PIPE)
> > +			return TGL_CDCLK_CD2X_PIPE_NONE;
> > +		else
> > +			return TGL_CDCLK_CD2X_PIPE(pipe);
> > +	} else if (INTEL_GEN(dev_priv) >= 11) {
> > +		if (pipe == INVALID_PIPE)
> > +			return ICL_CDCLK_CD2X_PIPE_NONE;
> > +		else
> > +			return ICL_CDCLK_CD2X_PIPE(pipe);
> > +	} else {
> > +		if (pipe == INVALID_PIPE)
> > +			return BXT_CDCLK_CD2X_PIPE_NONE;
> > +		else
> > +			return BXT_CDCLK_CD2X_PIPE(pipe);
> > +	}
> > +}
> > +
> >  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >  			  const struct intel_cdclk_state *cdclk_state,
> >  			  enum pipe pipe)
> > @@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> >  			bxt_de_pll_enable(dev_priv, vco);
> >  	}
> >
> > -	val = divider | skl_cdclk_decimal(cdclk);
> > -
> > -	if (INTEL_GEN(dev_priv) >= 12) {
> > -		if (pipe == INVALID_PIPE)
> > -			val |= TGL_CDCLK_CD2X_PIPE_NONE;
> > -		else
> > -			val |= TGL_CDCLK_CD2X_PIPE(pipe);
> > -	} else if (INTEL_GEN(dev_priv) >= 11) {
> > -		if (pipe == INVALID_PIPE)
> > -			val |= ICL_CDCLK_CD2X_PIPE_NONE;
> > -		else
> > -			val |= ICL_CDCLK_CD2X_PIPE(pipe);
> > -	} else {
> > -		if (pipe == INVALID_PIPE)
> > -			val |= BXT_CDCLK_CD2X_PIPE_NONE;
> > -		else
> > -			val |= BXT_CDCLK_CD2X_PIPE(pipe);
> > -	}
> > +	val = divider | skl_cdclk_decimal(cdclk) |
> > +		bxt_cdclk_cd2x_pipe(dev_priv, pipe);
> >
> >  	/*
> >  	 * Disable SSA Precharge when CD clock frequency < 500 MHz, @@
> > -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> >  	 * dividers both synching to an active pipe, or asynchronously
> >  	 * (PIPE_NONE).
> >  	 */
> > -	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> > +	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
> >
> >  	/* Make sure this is a legal cdclk value for the platform */
> >  	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
> > --
> > 2.21.0
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
copy.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++--------------------
 1 file changed, 2 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f59a6f775177..f5a99eb77efa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2227,39 +2227,6 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
-	state->cdclk.logical.vco = vco;
-	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		max(cnl_calc_voltage_level(cdclk),
-		    cnl_compute_min_voltage_level(state));
-
-	if (!state->active_pipes) {
-		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
-		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
-		state->cdclk.actual.vco = vco;
-		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			cnl_calc_voltage_level(cdclk);
-	} else {
-		state->cdclk.actual = state->cdclk.logical;
-	}
-
-	return 0;
-}
-
-static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	int min_cdclk, cdclk, vco;
-
-	min_cdclk = intel_compute_min_cdclk(state);
-	if (min_cdclk < 0)
-		return min_cdclk;
-
-	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
-	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
 	state->cdclk.logical.voltage_level =
@@ -2499,12 +2466,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ELKHARTLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
-- 
2.21.0

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Re: [PATCH 3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+

[Matt Roper]

On Wed, Sep 11, 2019 at 04:31:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
> copy.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++--------------------
>  1 file changed, 2 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f59a6f775177..f5a99eb77efa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2227,39 +2227,6 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
>  	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
> -	state->cdclk.logical.vco = vco;
> -	state->cdclk.logical.cdclk = cdclk;
> -	state->cdclk.logical.voltage_level =
> -		max(cnl_calc_voltage_level(cdclk),
> -		    cnl_compute_min_voltage_level(state));
> -
> -	if (!state->active_pipes) {
> -		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> -		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> -		state->cdclk.actual.vco = vco;
> -		state->cdclk.actual.cdclk = cdclk;
> -		state->cdclk.actual.voltage_level =
> -			cnl_calc_voltage_level(cdclk);
> -	} else {
> -		state->cdclk.actual = state->cdclk.logical;
> -	}
> -
> -	return 0;
> -}
> -
> -static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	int min_cdclk, cdclk, vco;
> -
> -	min_cdclk = intel_compute_min_cdclk(state);
> -	if (min_cdclk < 0)
> -		return min_cdclk;
> -
> -	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> -	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
>  	state->cdclk.logical.voltage_level =
> @@ -2499,12 +2466,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ELKHARTLAKE(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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[PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reuse the same .modeset_calc_cdclk() function for all bxt+.

The only difference in between the cnl/icl and the bxt variants
is the call to cnl_compute_min_voltage_level(). We can do that call
just fine on older platforms since they leave min_voltage_level[]
zeroed. Let's rename the function to bxt_compute_min_voltage_level()
just so it stays consistent with the rest of the naming scheme.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +++++-----------------
 1 file changed, 9 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f5a99eb77efa..b8b3814ba116 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
 }
 
 /*
+ * Account for port clock min voltage level requirements.
+ * This only really does something on CNL+ but can be
+ * called on earlier platforms as well.
+ *
  * Note that this functions assumes that 0 is
  * the lowest voltage value, and higher values
  * correspond to increasingly higher voltages.
@@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
  * future platforms this code will need to be
  * adjusted.
  */
-static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
+static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc *crtc;
@@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
-	state->cdclk.logical.vco = vco;
-	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk);
-
-	if (!state->active_pipes) {
-		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
-		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
-		state->cdclk.actual.vco = vco;
-		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			dev_priv->display.calc_voltage_level(cdclk);
-	} else {
-		state->cdclk.actual = state->cdclk.logical;
-	}
-
-	return 0;
-}
-
-static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	int min_cdclk, cdclk, vco;
-
-	min_cdclk = intel_compute_min_cdclk(state);
-	if (min_cdclk < 0)
-		return min_cdclk;
-
-	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
-	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
 	state->cdclk.logical.voltage_level =
 		max(dev_priv->display.calc_voltage_level(cdclk),
-		    cnl_compute_min_voltage_level(state));
+		    bxt_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ELKHARTLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
 		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
-- 
2.21.0

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Re: [PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs

[Matt Roper]

On Wed, Sep 11, 2019 at 04:31:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reuse the same .modeset_calc_cdclk() function for all bxt+.
> 
> The only difference in between the cnl/icl and the bxt variants
> is the call to cnl_compute_min_voltage_level(). We can do that call
> just fine on older platforms since they leave min_voltage_level[]
> zeroed. Let's rename the function to bxt_compute_min_voltage_level()
> just so it stays consistent with the rest of the naming scheme.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +++++-----------------
>  1 file changed, 9 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f5a99eb77efa..b8b3814ba116 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>  }
>  
>  /*
> + * Account for port clock min voltage level requirements.
> + * This only really does something on CNL+ but can be
> + * called on earlier platforms as well.
> + *
>   * Note that this functions assumes that 0 is
>   * the lowest voltage value, and higher values
>   * correspond to increasingly higher voltages.
> @@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>   * future platforms this code will need to be
>   * adjusted.
>   */
> -static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
> +static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_crtc *crtc;
> @@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
>  	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
> -	state->cdclk.logical.vco = vco;
> -	state->cdclk.logical.cdclk = cdclk;
> -	state->cdclk.logical.voltage_level =
> -		dev_priv->display.calc_voltage_level(cdclk);
> -
> -	if (!state->active_pipes) {
> -		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> -		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> -		state->cdclk.actual.vco = vco;
> -		state->cdclk.actual.cdclk = cdclk;
> -		state->cdclk.actual.voltage_level =
> -			dev_priv->display.calc_voltage_level(cdclk);
> -	} else {
> -		state->cdclk.actual = state->cdclk.logical;
> -	}
> -
> -	return 0;
> -}
> -
> -static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	int min_cdclk, cdclk, vco;
> -
> -	min_cdclk = intel_compute_min_cdclk(state);
> -	if (min_cdclk < 0)
> -		return min_cdclk;
> -
> -	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> -	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
>  	state->cdclk.logical.voltage_level =
>  		max(dev_priv->display.calc_voltage_level(cdclk),
> -		    cnl_compute_min_voltage_level(state));
> +		    bxt_compute_min_voltage_level(state));
>  
>  	if (!state->active_pipes) {
>  		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> @@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ELKHARTLAKE(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
>  		dev_priv->cdclk.table = cnl_cdclk_table;
>  	} else if (IS_GEN9_LP(dev_priv)) {
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

[Matt Roper]

On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
> reference clock. So let's read out the ref clock before we
> try to compute the bypass clock.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a93bad0a8..6b75d2a91cd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	u32 divider;
>  	int div;
>  
> +	bxt_de_pll_readout(dev_priv, cdclk_state);
> +
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		cdclk_state->bypass = cdclk_state->ref / 2;
>  	else if (INTEL_GEN(dev_priv) >= 11)
> @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		cdclk_state->bypass = cdclk_state->ref;
>  
> -	bxt_de_pll_readout(dev_priv, cdclk_state);
>  	if (cdclk_state->vco == 0) {
>  		cdclk_state->cdclk = cdclk_state->bypass;
>  		goto out;
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
URL   : https://patchwork.freedesktop.org/series/66537/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6871 -> Patchwork_14361
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14361:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_close_race@basic-threads:
    - {fi-tgl-u}:         NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-tgl-u/igt@gem_close_race@basic-threads.html

  
Known issues
------------

  Here are the changes found in Patchwork_14361 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
    - fi-icl-u3:          [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [PASS][4] -> [INCOMPLETE][5] ([fdo#107718])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - {fi-icl-guc}:       [INCOMPLETE][6] ([fdo#107713] / [fdo#109100]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-guc/igt@gem_ctx_create@basic-files.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-guc/igt@gem_ctx_create@basic-files.html

  * igt@gem_flink_basic@flink-lifetime:
    - fi-icl-u3:          [DMESG-WARN][8] ([fdo#107724]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][10] ([fdo#111407]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - {fi-icl-u4}:        [FAIL][12] ([fdo#103167]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
    - fi-icl-u2:          [FAIL][14] ([fdo#103167]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (53 -> 47)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6871 -> Patchwork_14361

  CI-20190529: 20190529
  CI_DRM_6871: f58f61f8f8a1137f3b4e2bf4af02d5f7694a0b2e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14361: 0e9dbe16b22854f6ff1450049b10a87581dfe2a7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0e9dbe16b228 drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
0edf73272516 drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+
746de6f08d3f drm/i915: Fix CD2X pipe select masking during cdclk sanitation
7c74fe5c2ef8 drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
URL   : https://patchwork.freedesktop.org/series/66537/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6871_full -> Patchwork_14361_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14361_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl8/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_eio@unwedge-stress:
    - shard-apl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl1/igt@gem_eio@unwedge-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#111325]) +4 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-iclb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#107713] / [fdo#109507])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109276]) +19 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][19] ([fdo#110854]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@gem_exec_balancer@smoke.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb1/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][21] ([fdo#111325]) -> [PASS][22] +9 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl5/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][27] ([fdo#104873]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][29] ([fdo#103167]) -> [PASS][30] +4 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [FAIL][31] ([fdo#103166]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][33] ([fdo#109441]) -> [PASS][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][35] ([fdo#109276]) -> [PASS][36] +21 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb3/igt@prime_busy@hang-bsd2.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb2/igt@prime_busy@hang-bsd2.html

  * igt@tools_test@tools_test:
    - shard-apl:          [SKIP][37] ([fdo#109271]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl8/igt@tools_test@tools_test.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl8/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][39] ([fdo#111329]) -> [SKIP][40] ([fdo#109276])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][41] ([fdo#109276]) -> [FAIL][42] ([fdo#111330]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][43] ([fdo#111330]) -> [SKIP][44] ([fdo#109276])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb8/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6871 -> Patchwork_14361

  CI-20190529: 20190529
  CI_DRM_6871: f58f61f8f8a1137f3b4e2bf4af02d5f7694a0b2e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14361: 0e9dbe16b22854f6ff1450049b10a87581dfe2a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)
URL   : https://patchwork.freedesktop.org/series/66537/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6875 -> Patchwork_14374
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/

Known issues
------------

  Here are the changes found in Patchwork_14374 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@double-flink:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-icl-u3/igt@gem_flink_basic@double-flink.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-icl-u3/igt@gem_flink_basic@double-flink.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - fi-icl-u3:          [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724] / [fdo#111214]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-icl-u3/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_hangcheck:
    - {fi-icl-guc}:       [DMESG-WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-icl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_addfb_basic@size-max:
    - {fi-icl-dsi}:       [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-icl-dsi/igt@kms_addfb_basic@size-max.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-icl-dsi/igt@kms_addfb_basic@size-max.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#111096])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 47)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6875 -> Patchwork_14374

  CI-20190529: 20190529
  CI_DRM_6875: 05b5eaaa5a67dd8db91fb994ece984cbce420127 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14374: 3c0cda0dd71dda2b011aa549763fa6156ce946a6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3c0cda0dd71d drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
0ee99cf92f5f drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+
75c19d49b4b0 drm/i915: Fix CD2X pipe select masking during cdclk sanitation
5cb2fe56b076 drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)

[Chris Wilson]

Quoting Patchwork (2019-09-12 10:36:49)
> == Series Details ==
> 
> Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)
> URL   : https://patchwork.freedesktop.org/series/66537/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6875 -> Patchwork_14374
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/

Ignorance is bliss. Pushed, so the onus falls back onto the GEM
failures. Thanks for the fixes,
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)
URL   : https://patchwork.freedesktop.org/series/66537/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6875_full -> Patchwork_14374_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14374_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@unwedge-stress:
    - shard-apl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl5/igt@gem_eio@unwedge-stress.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_schedule@in-order-bsd2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276]) +13 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@gem_exec_schedule@in-order-bsd2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb6/igt@gem_exec_schedule@in-order-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl3/igt@gem_tiled_swapping@non-threaded.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl2/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([fdo#103167]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103166])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
    - shard-skl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#106885])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl1/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl7/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] +6 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_eio@reset-stress:
    - shard-glk:          [FAIL][19] ([fdo#109661]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-glk3/igt@gem_eio@reset-stress.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-glk3/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@fifo-bsd:
    - shard-iclb:         [SKIP][21] ([fdo#111325]) -> [PASS][22] +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@gem_exec_schedule@fifo-bsd.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb6/igt@gem_exec_schedule@fifo-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [SKIP][23] ([fdo#109276]) -> [PASS][24] +11 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@kms_atomic_transition@2x-modeset-transitions:
    - shard-hsw:          [SKIP][25] ([fdo#109271]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-hsw4/igt@kms_atomic_transition@2x-modeset-transitions.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-hsw2/igt@kms_atomic_transition@2x-modeset-transitions.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-skl:          [INCOMPLETE][27] ([fdo#110741]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][29] ([fdo#105363]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][31] ([fdo#103167]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         [INCOMPLETE][33] ([fdo#106978] / [fdo#107713]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][35] ([fdo#108145]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][39] ([fdo#104108]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@perf_pmu@most-busy-idle-check-all-vecs0:
    - shard-apl:          [INCOMPLETE][41] ([fdo#103927]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl3/igt@perf_pmu@most-busy-idle-check-all-vecs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl7/igt@perf_pmu@most-busy-idle-check-all-vecs0.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [SKIP][43] ([fdo#109276]) -> [FAIL][44] ([fdo#111330])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][45] ([fdo#107724]) -> [SKIP][46] ([fdo#109349])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6875 -> Patchwork_14374

  CI-20190529: 20190529
  CI_DRM_6875: 05b5eaaa5a67dd8db91fb994ece984cbce420127 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14374: 3c0cda0dd71dda2b011aa549763fa6156ce946a6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/
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