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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Xiong Zhang <xiong.y.zhang@intel.com>, intel-gfx@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: Re: [PATCH 2/2] drm/i915/skl: Adding DDI_E power well domain
Date: Mon, 31 Aug 2015 18:48:55 +0300	[thread overview]
Message-ID: <874mjfxxug.fsf@intel.com> (raw)
In-Reply-To: <1439460012-17545-2-git-send-email-xiong.y.zhang@intel.com>

On Thu, 13 Aug 2015, Xiong Zhang <xiong.y.zhang@intel.com> wrote:
> From B spec, DDI_E port belong to PowerWell 2, but
> DDI_E share the powerwell_req/staus register bit with
> DDI_A which belong to DDI_A_E_POWER_WELL.
>
> In order to communicate with the connector on DDI-E, both
> DDI_A_E_POWER_WELL and POWER_WELL_2 must be enabled.
>
> Currently intel_dp_power_get(DDI_E) only enable
> DDI_A_E_POWER_WELL, this patch will not only enable
> DDI_a_E_POWER_WELL but also enable POWER_WELL_2.
>
> This patch also fix the DDI-E hotplug function.
>
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>

Pushed to drm-intel-next-fixes.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c     | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h         | 1 +
>  drivers/gpu/drm/i915/intel_display.c    | 3 ++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
>  4 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 86734be..5523b6e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2564,6 +2564,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
>  		return "PORT_DDI_D_2_LANES";
>  	case POWER_DOMAIN_PORT_DDI_D_4_LANES:
>  		return "PORT_DDI_D_4_LANES";
> +	case POWER_DOMAIN_PORT_DDI_E_2_LANES:
> +		return "PORT_DDI_E_2_LANES";
>  	case POWER_DOMAIN_PORT_DSI:
>  		return "PORT_DSI";
>  	case POWER_DOMAIN_PORT_CRT:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b157865..ee71f90 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -182,6 +182,7 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_PORT_DDI_C_4_LANES,
>  	POWER_DOMAIN_PORT_DDI_D_2_LANES,
>  	POWER_DOMAIN_PORT_DDI_D_4_LANES,
> +	POWER_DOMAIN_PORT_DDI_E_2_LANES,
>  	POWER_DOMAIN_PORT_DSI,
>  	POWER_DOMAIN_PORT_CRT,
>  	POWER_DOMAIN_PORT_OTHER,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 801187c..ccd3f0b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5150,7 +5150,6 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
>  {
>  	switch (port) {
>  	case PORT_A:
> -	case PORT_E:
>  		return POWER_DOMAIN_PORT_DDI_A_4_LANES;
>  	case PORT_B:
>  		return POWER_DOMAIN_PORT_DDI_B_4_LANES;
> @@ -5158,6 +5157,8 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
>  		return POWER_DOMAIN_PORT_DDI_C_4_LANES;
>  	case PORT_D:
>  		return POWER_DOMAIN_PORT_DDI_D_4_LANES;
> +	case PORT_E:
> +		return POWER_DOMAIN_PORT_DDI_E_2_LANES;
>  	default:
>  		WARN_ON_ONCE(1);
>  		return POWER_DOMAIN_PORT_OTHER;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 821644d..af7fdb3 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -297,6 +297,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |		\
>  	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |		\
>  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |		\
>  	BIT(POWER_DOMAIN_AUX_B) |                       \
>  	BIT(POWER_DOMAIN_AUX_C) |			\
>  	BIT(POWER_DOMAIN_AUX_D) |			\
> @@ -316,6 +317,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (		\
>  	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\
>  	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |		\
>  	BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (		\
>  	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |		\
> -- 
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2015-08-31 15:48 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-13 10:00 [PATCH 1/2] drm/i915: Adding break for one case Xiong Zhang
2015-08-13 10:00 ` [PATCH 2/2] drm/i915/skl: Adding DDI_E power well domain Xiong Zhang
2015-08-14 22:22   ` Rodrigo Vivi
2015-08-17  1:50     ` Zhang, Xiong Y
2015-08-24 23:59       ` Vivi, Rodrigo
2015-08-31 15:48   ` Jani Nikula [this message]
2015-08-13 10:36 ` [PATCH 1/2] drm/i915: Adding break for one case Timo Aaltonen
2015-08-13 10:37   ` Timo Aaltonen
2015-08-14  9:25     ` Daniel Vetter
2015-08-14 10:41       ` Zhang, Xiong Y
2015-08-14  7:12 ` Jani Nikula

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