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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Hui-Ping Chen <hpchen0nvt@gmail.com>
Cc: richard@nod.at,  vigneshr@ti.com,  robh@kernel.org,
	 krzk+dt@kernel.org, conor+dt@kernel.org,
	 nikita.shubin@maquefel.me,  arnd@arndb.de, vkoul@kernel.org,
	 esben@geanix.com, linux-arm-kernel@lists.infradead.org,
	 linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Date: Mon, 02 Dec 2024 18:12:22 +0100	[thread overview]
Message-ID: <875xo257rd.fsf@bootlin.com> (raw)
In-Reply-To: <20241125052524.135362-3-hpchen0nvt@gmail.com> (Hui-Ping Chen's message of "Mon, 25 Nov 2024 05:25:24 +0000")

Hello,

> +static int ma35_nand_attach_chip(struct nand_chip *chip)
> +{
> +	struct ma35_nand_info *nand = nand_get_controller_data(chip);
> +	struct mtd_info *mtd = nand_to_mtd(chip);
> +	struct device *dev = mtd->dev.parent;
> +	u32 reg;
> +
> +	if (chip->options & NAND_BUSWIDTH_16) {
> +		dev_err(dev, "16 bits bus width not supported");
> +		return -EINVAL;
> +	}
> +
> +	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK);
> +	if (mtd->writesize == 2048)
> +		writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);
> +	else if (mtd->writesize == 4096)
> +		writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);
> +	else if (mtd->writesize == 8192)
> +		writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);

You should error out if the writesize is not supported.

Thanks,
Miquèl


WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Hui-Ping Chen <hpchen0nvt@gmail.com>
Cc: richard@nod.at,  vigneshr@ti.com,  robh@kernel.org,
	 krzk+dt@kernel.org, conor+dt@kernel.org,
	 nikita.shubin@maquefel.me,  arnd@arndb.de, vkoul@kernel.org,
	 esben@geanix.com, linux-arm-kernel@lists.infradead.org,
	 linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Date: Mon, 02 Dec 2024 18:12:22 +0100	[thread overview]
Message-ID: <875xo257rd.fsf@bootlin.com> (raw)
In-Reply-To: <20241125052524.135362-3-hpchen0nvt@gmail.com> (Hui-Ping Chen's message of "Mon, 25 Nov 2024 05:25:24 +0000")

Hello,

> +static int ma35_nand_attach_chip(struct nand_chip *chip)
> +{
> +	struct ma35_nand_info *nand = nand_get_controller_data(chip);
> +	struct mtd_info *mtd = nand_to_mtd(chip);
> +	struct device *dev = mtd->dev.parent;
> +	u32 reg;
> +
> +	if (chip->options & NAND_BUSWIDTH_16) {
> +		dev_err(dev, "16 bits bus width not supported");
> +		return -EINVAL;
> +	}
> +
> +	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK);
> +	if (mtd->writesize == 2048)
> +		writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);
> +	else if (mtd->writesize == 4096)
> +		writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);
> +	else if (mtd->writesize == 8192)
> +		writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);

You should error out if the writesize is not supported.

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2024-12-02 17:13 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-25  5:25 [PATCH v9 0/2] Add support for nuvoton ma35 nand controller Hui-Ping Chen
2024-11-25  5:25 ` Hui-Ping Chen
2024-11-25  5:25 ` [PATCH v9 1/2] dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings Hui-Ping Chen
2024-11-25  5:25   ` Hui-Ping Chen
2024-11-25  5:25 ` [PATCH v9 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC Hui-Ping Chen
2024-11-25  5:25   ` Hui-Ping Chen
2024-12-02 17:12   ` Miquel Raynal [this message]
2024-12-02 17:12     ` Miquel Raynal
2024-12-03  0:27     ` Hui-Ping Chen
2024-12-03  0:27       ` Hui-Ping Chen

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