From: Jani Nikula <jani.nikula@intel.com>
To: Maxime Ripard <maxime@cerno.tech>
Cc: intel-gfx@lists.freedesktop.org,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/dp: add helpers to read link training delays
Date: Tue, 19 Oct 2021 15:39:20 +0300 [thread overview]
Message-ID: <875yttqjd3.fsf@intel.com> (raw)
In-Reply-To: <20211018084147.iuexgyykyrrx2ykw@gilmour>
On Mon, 18 Oct 2021, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi Jani,
>
> On Fri, Oct 15, 2021 at 06:21:35PM +0300, Jani Nikula wrote:
>> On Thu, 14 Oct 2021, Jani Nikula <jani.nikula@intel.com> wrote:
>> > The link training delays are different and/or available in different
>> > DPCD offsets depending on:
>> >
>> > - Clock recovery vs. channel equalization
>> > - DPRX vs. LTTPR
>> > - 128b/132b vs. 8b/10b
>> > - DPCD 1.4+ vs. earlier
>> >
>> > Add helpers to get the correct delays in us, reading DPCD if
>> > necessary. This is more straightforward than trying to retrofit the
>> > existing helpers to take 128b/132b into account.
>> >
>> > Having to pass in the DPCD receiver cap field seems unavoidable, because
>> > reading it involves checking the revision and reading extended receiver
>> > cap. So unfortunately the interface is mixed cached and read as needed.
>> >
>> > v2: Remove delay_us < 0 check and the whole local var (Ville)
>> >
>> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>
>> Maarten, Maxime, Thomas -
>>
>> Ack on the first two patches in this series?
>>
>> Should we merge them via a topic branch to both drm-misc-next and
>> drm-intel-next, or is it fine to merge them all via drm-intel-next? We
>> might be at a point in the development cycle that it takes a while to
>> get the branches in sync again.
>
> I guess the easiest would be to send a PR so that we can merge it in the
> two branches then.
Sent.
https://lore.kernel.org/r/878ryps5b6.fsf@intel.com
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com>
To: Maxime Ripard <maxime@cerno.tech>
Cc: intel-gfx@lists.freedesktop.org,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 1/3] drm/dp: add helpers to read link training delays
Date: Tue, 19 Oct 2021 15:39:20 +0300 [thread overview]
Message-ID: <875yttqjd3.fsf@intel.com> (raw)
In-Reply-To: <20211018084147.iuexgyykyrrx2ykw@gilmour>
On Mon, 18 Oct 2021, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi Jani,
>
> On Fri, Oct 15, 2021 at 06:21:35PM +0300, Jani Nikula wrote:
>> On Thu, 14 Oct 2021, Jani Nikula <jani.nikula@intel.com> wrote:
>> > The link training delays are different and/or available in different
>> > DPCD offsets depending on:
>> >
>> > - Clock recovery vs. channel equalization
>> > - DPRX vs. LTTPR
>> > - 128b/132b vs. 8b/10b
>> > - DPCD 1.4+ vs. earlier
>> >
>> > Add helpers to get the correct delays in us, reading DPCD if
>> > necessary. This is more straightforward than trying to retrofit the
>> > existing helpers to take 128b/132b into account.
>> >
>> > Having to pass in the DPCD receiver cap field seems unavoidable, because
>> > reading it involves checking the revision and reading extended receiver
>> > cap. So unfortunately the interface is mixed cached and read as needed.
>> >
>> > v2: Remove delay_us < 0 check and the whole local var (Ville)
>> >
>> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>
>> Maarten, Maxime, Thomas -
>>
>> Ack on the first two patches in this series?
>>
>> Should we merge them via a topic branch to both drm-misc-next and
>> drm-intel-next, or is it fine to merge them all via drm-intel-next? We
>> might be at a point in the development cycle that it takes a while to
>> get the branches in sync again.
>
> I guess the easiest would be to send a PR so that we can merge it in the
> two branches then.
Sent.
https://lore.kernel.org/r/878ryps5b6.fsf@intel.com
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2021-10-19 12:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 15:00 [Intel-gfx] [PATCH 1/3] drm/dp: add helpers to read link training delays Jani Nikula
2021-10-14 15:00 ` Jani Nikula
2021-10-14 15:00 ` [Intel-gfx] [PATCH 2/3] drm/dp: reuse the 8b/10b link training delay helpers Jani Nikula
2021-10-14 15:00 ` Jani Nikula
2021-10-14 15:43 ` [Intel-gfx] " Ville Syrjälä
2021-10-14 15:43 ` Ville Syrjälä
2021-10-14 15:00 ` [Intel-gfx] [PATCH 3/3] drm/i915/dp: use new " Jani Nikula
2021-10-14 15:00 ` Jani Nikula
2021-10-19 15:38 ` [Intel-gfx] " Jani Nikula
2021-10-19 15:38 ` Jani Nikula
2021-10-14 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/dp: add helpers to read link training delays Patchwork
2021-10-14 23:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-15 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-15 15:21 ` [Intel-gfx] [PATCH 1/3] " Jani Nikula
2021-10-15 15:21 ` Jani Nikula
2021-10-18 8:41 ` [Intel-gfx] " Maxime Ripard
2021-10-18 8:41 ` Maxime Ripard
2021-10-19 12:39 ` Jani Nikula [this message]
2021-10-19 12:39 ` Jani Nikula
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