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From: Marc Zyngier <maz@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: catalin.marinas@arm.com, broonie@kernel.org, will@kernel.org,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: Do not trap PMSNEVFR_EL1
Date: Thu, 26 Aug 2021 09:51:05 +0100	[thread overview]
Message-ID: <875yvspp1i.wl-maz@kernel.org> (raw)
In-Reply-To: <20210824154523.906270-1-alexandru.elisei@arm.com>

On Tue, 24 Aug 2021 16:45:23 +0100,
Alexandru Elisei <alexandru.elisei@arm.com> wrote:
> 
> Commit 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") zeroed
> the fine grained trap registers to prevent unwanted register traps from
> occuring. However, for the PMSNEVFR_EL1 register, the corresponding
> HDFG{R,W}TR_EL2.nPMSNEVFR_EL1 fields must be 1 to disable trapping. Set
> both fields to 1 if FEAT_SPEv1p2 is detected to disable read and write
> traps.
> 
> Fixes: 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot")
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
> Based on v5.14-rc7. Tested on the model, using boot-wrapper built from
> commit 5cd6238ec4ef ("aarch32: fix .globl replacement"). Without this
> patch, in NVHE mode, the model freezes when I try to access PMSNEVFR_EL1.
> With this patch, the model doesn't hang anymore.
> 
> Changes since v1:
> 
> * Set the corresponding bit in HDFGWRTR_EL2 to also disable write traps. My
>   thanks to Mark for pointing it out.
> 
>  arch/arm64/include/asm/el2_setup.h | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index b83fb24954b7..3198acb2aad8 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -149,8 +149,17 @@
>  	ubfx	x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
>  	cbz	x1, .Lskip_fgt_\@
>  
> -	msr_s	SYS_HDFGRTR_EL2, xzr
> -	msr_s	SYS_HDFGWTR_EL2, xzr
> +	mov	x0, xzr
> +	mrs	x1, id_aa64dfr0_el1
> +	ubfx	x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
> +	cmp	x1, #3
> +	b.lt	.Lset_fgt_\@
> +	/* Disable PMSNEVFR_EL1 read and write traps */
> +	orr	x0, x0, #(1 << 62)
> +
> +.Lset_fgt_\@:
> +	msr_s	SYS_HDFGRTR_EL2, x0
> +	msr_s	SYS_HDFGWTR_EL2, x0
>  	msr_s	SYS_HFGRTR_EL2, xzr
>  	msr_s	SYS_HFGWTR_EL2, xzr
>  	msr_s	SYS_HFGITR_EL2, xzr

The beauty of negative trap bits... Thankfully this seems to be the
only one.

Acked-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com,
	suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, broonie@kernel.org
Subject: Re: [PATCH v2] arm64: Do not trap PMSNEVFR_EL1
Date: Thu, 26 Aug 2021 09:51:05 +0100	[thread overview]
Message-ID: <875yvspp1i.wl-maz@kernel.org> (raw)
In-Reply-To: <20210824154523.906270-1-alexandru.elisei@arm.com>

On Tue, 24 Aug 2021 16:45:23 +0100,
Alexandru Elisei <alexandru.elisei@arm.com> wrote:
> 
> Commit 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") zeroed
> the fine grained trap registers to prevent unwanted register traps from
> occuring. However, for the PMSNEVFR_EL1 register, the corresponding
> HDFG{R,W}TR_EL2.nPMSNEVFR_EL1 fields must be 1 to disable trapping. Set
> both fields to 1 if FEAT_SPEv1p2 is detected to disable read and write
> traps.
> 
> Fixes: 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot")
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
> Based on v5.14-rc7. Tested on the model, using boot-wrapper built from
> commit 5cd6238ec4ef ("aarch32: fix .globl replacement"). Without this
> patch, in NVHE mode, the model freezes when I try to access PMSNEVFR_EL1.
> With this patch, the model doesn't hang anymore.
> 
> Changes since v1:
> 
> * Set the corresponding bit in HDFGWRTR_EL2 to also disable write traps. My
>   thanks to Mark for pointing it out.
> 
>  arch/arm64/include/asm/el2_setup.h | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index b83fb24954b7..3198acb2aad8 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -149,8 +149,17 @@
>  	ubfx	x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
>  	cbz	x1, .Lskip_fgt_\@
>  
> -	msr_s	SYS_HDFGRTR_EL2, xzr
> -	msr_s	SYS_HDFGWTR_EL2, xzr
> +	mov	x0, xzr
> +	mrs	x1, id_aa64dfr0_el1
> +	ubfx	x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
> +	cmp	x1, #3
> +	b.lt	.Lset_fgt_\@
> +	/* Disable PMSNEVFR_EL1 read and write traps */
> +	orr	x0, x0, #(1 << 62)
> +
> +.Lset_fgt_\@:
> +	msr_s	SYS_HDFGRTR_EL2, x0
> +	msr_s	SYS_HDFGWTR_EL2, x0
>  	msr_s	SYS_HFGRTR_EL2, xzr
>  	msr_s	SYS_HFGWTR_EL2, xzr
>  	msr_s	SYS_HFGITR_EL2, xzr

The beauty of negative trap bits... Thankfully this seems to be the
only one.

Acked-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-08-26  8:51 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-24 15:45 [PATCH v2] arm64: Do not trap PMSNEVFR_EL1 Alexandru Elisei
2021-08-24 15:45 ` Alexandru Elisei
2021-08-24 15:53 ` Mark Brown
2021-08-24 15:53   ` Mark Brown
2021-08-26  8:51 ` Marc Zyngier [this message]
2021-08-26  8:51   ` Marc Zyngier
2021-08-26 11:07 ` Catalin Marinas
2021-08-26 11:07   ` Catalin Marinas

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