[PATCH] Revert "drm/i915/color: Extract icl_read_luts()"

[PATCH] Revert "drm/i915/color: Extract icl_read_luts()"

[Swati Sharma]

This reverts commit 84af7649188194a74cdd6437235a5e3c86108f0f.

This is causing problems with the display, displays are all
bright colors.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 126 +++------------------
 drivers/gpu/drm/i915/i915_reg.h            |   6 -
 2 files changed, 15 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 402151128e1f..9ab34902663e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1420,9 +1420,6 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
 
 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->gamma_enable)
-		return 0;
-
 	switch (crtc_state->gamma_mode) {
 	case GAMMA_MODE_MODE_8BIT:
 		return 8;
@@ -1436,9 +1433,6 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->gamma_enable)
-		return 0;
-
 	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
 		return 0;
 
@@ -1455,9 +1449,6 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->gamma_enable)
-		return 0;
-
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
 		return 10;
 	else
@@ -1466,9 +1457,6 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->gamma_enable)
-		return 0;
-
 	switch (crtc_state->gamma_mode) {
 	case GAMMA_MODE_MODE_8BIT:
 		return 8;
@@ -1480,39 +1468,21 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
-{
-	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
-		return 0;
-
-	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
-	case GAMMA_MODE_MODE_8BIT:
-		return 8;
-	case GAMMA_MODE_MODE_10BIT:
-		return 10;
-	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
-		return 16;
-	default:
-		MISSING_CASE(crtc_state->gamma_mode);
-		return 0;
-	}
-
-}
-
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
+	if (!crtc_state->gamma_enable)
+		return 0;
+
 	if (HAS_GMCH(dev_priv)) {
 		if (IS_CHERRYVIEW(dev_priv))
 			return chv_gamma_precision(crtc_state);
 		else
 			return i9xx_gamma_precision(crtc_state);
 	} else {
-		if (INTEL_GEN(dev_priv) >= 11)
-			return icl_gamma_precision(crtc_state);
-		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			return glk_gamma_precision(crtc_state);
 		else if (IS_IRONLAKE(dev_priv))
 			return ilk_gamma_precision(crtc_state);
@@ -1543,20 +1513,6 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
 	return true;
 }
 
-static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
-					      struct drm_color_lut *lut2,
-					      int lut_size, u32 err)
-{
-	int i;
-
-	for (i = 0; i < 9; i++) {
-		if (!err_check(&lut1[i], &lut2[i], err))
-			return false;
-	}
-
-	return true;
-}
-
 bool intel_color_lut_equal(struct drm_property_blob *blob1,
 			   struct drm_property_blob *blob2,
 			   u32 gamma_mode, u32 bit_precision)
@@ -1575,8 +1531,16 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	lut_size2 = drm_color_lut_size(blob2);
 
 	/* check sw and hw lut size */
-	if (lut_size1 != lut_size2)
-		return false;
+	switch (gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+	case GAMMA_MODE_MODE_10BIT:
+		if (lut_size1 != lut_size2)
+			return false;
+		break;
+	default:
+		MISSING_CASE(gamma_mode);
+			return false;
+	}
 
 	lut1 = blob1->data;
 	lut2 = blob2->data;
@@ -1584,18 +1548,13 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	err = 0xffff >> bit_precision;
 
 	/* check sw and hw lut entry to be equal */
-	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
+	switch (gamma_mode) {
 	case GAMMA_MODE_MODE_8BIT:
 	case GAMMA_MODE_MODE_10BIT:
 		if (!intel_color_lut_entry_equal(lut1, lut2,
 						 lut_size2, err))
 			return false;
 		break;
-	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
-		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
-						       lut_size2, err))
-			return false;
-		break;
 	default:
 		MISSING_CASE(gamma_mode);
 			return false;
@@ -1835,60 +1794,6 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
 
-static struct drm_property_blob *
-icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
-	enum pipe pipe = crtc->pipe;
-	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
-	u32 i, val1, val2;
-
-	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * lut_size,
-					NULL);
-	if (IS_ERR(blob))
-		return NULL;
-
-	blob_data = blob->data;
-
-	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
-
-	for (i = 0; i < 9; i++) {
-		val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
-		val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
-
-		blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
-				   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
-		blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
-				     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
-		blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
-				    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
-	}
-
-	/*
-	 * FIXME readouts from PAL_PREC_DATA register aren't giving correct values
-	 * in the case of fine and coarse segments. Restricting readouts only for
-	 * super fine segment as of now.
-	 */
-
-	return blob;
-}
-
-static void icl_read_luts(struct intel_crtc_state *crtc_state)
-{
-	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
-	    GAMMA_MODE_MODE_8BIT)
-		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
-	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
-		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
-		crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
-	else
-		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
-}
-
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1932,7 +1837,6 @@ void intel_color_init(struct intel_crtc *crtc)
 
 		if (INTEL_GEN(dev_priv) >= 11) {
 			dev_priv->display.load_luts = icl_load_luts;
-			dev_priv->display.read_luts = icl_read_luts;
 		} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
 			dev_priv->display.load_luts = glk_load_luts;
 			dev_priv->display.read_luts = glk_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a69c19aae5bb..661cbe4c933a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10574,12 +10574,6 @@ enum skl_power_gate {
 
 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
-#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
-#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
-#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
-#define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
-#define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
-#define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
 
 #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
 					_PAL_PREC_MULTI_SEG_INDEX_A, \
-- 
2.23.0

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✓ Fi.CI.BAT: success for Revert "drm/i915/color: Extract icl_read_luts()"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/color: Extract icl_read_luts()"
URL   : https://patchwork.freedesktop.org/series/67174/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6948 -> Patchwork_14517
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/

Known issues
------------

  Here are the changes found in Patchwork_14517 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#111407])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735


Participating hosts (52 -> 43)
------------------------------

  Missing    (9): fi-ilk-m540 fi-cml-h fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6948 -> Patchwork_14517

  CI-20190529: 20190529
  CI_DRM_6948: 485ca160d8ffac7ffb5be5e76fa12ad46a7e5a19 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5201: 3c1633abec14679300d52eeaf9fb7b63e435e51e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14517: e44f42fed6415029bba2f88e3b23c985a85ed670 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e44f42fed641 Revert "drm/i915/color: Extract icl_read_luts()"

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/index.html
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Re: [PATCH] Revert "drm/i915/color: Extract icl_read_luts()"

[Saarinen, Jani]

Hi, 

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Swati
> Sharma
> Sent: tiistai 24. syyskuuta 2019 16.58
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; daniel.vetter@ffwll.ch; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [Intel-gfx] [PATCH] Revert "drm/i915/color: Extract icl_read_luts()"
> 
> This reverts commit 84af7649188194a74cdd6437235a5e3c86108f0f.
> 
> This is causing problems with the display, displays are all bright colors.

Tested-by: Jani Saarinen <jani.saarinen@intel.com>
Bugzilla:  https://bugs.freedesktop.org/show_bug.cgi?id=111809

> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 126 +++------------------
>  drivers/gpu/drm/i915/i915_reg.h            |   6 -
>  2 files changed, 15 insertions(+), 117 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 402151128e1f..9ab34902663e 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1420,9 +1420,6 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
> 
>  static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1436,9 +1433,6 @@ static int i9xx_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> 
>  static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
>  		return 0;
> 
> @@ -1455,9 +1449,6 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> 
>  static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>  		return 10;
>  	else
> @@ -1466,9 +1457,6 @@ static int chv_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> 
>  static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1480,39 +1468,21 @@ static int glk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>  	}
>  }
> 
> -static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) -{
> -	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> -		return 0;
> -
> -	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> -	case GAMMA_MODE_MODE_8BIT:
> -		return 8;
> -	case GAMMA_MODE_MODE_10BIT:
> -		return 10;
> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> -		return 16;
> -	default:
> -		MISSING_CASE(crtc_state->gamma_mode);
> -		return 0;
> -	}
> -
> -}
> -
>  int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +
>  	if (HAS_GMCH(dev_priv)) {
>  		if (IS_CHERRYVIEW(dev_priv))
>  			return
> chv_gamma_precision(crtc_state);
>  		else
>  			return
> i9xx_gamma_precision(crtc_state);
>  	} else {
> -		if (INTEL_GEN(dev_priv) >= 11)
> -			return
> icl_gamma_precision(crtc_state);
> -		else if (IS_CANNONLAKE(dev_priv) ||
> IS_GEMINILAKE(dev_priv))
> +		if (IS_CANNONLAKE(dev_priv) ||
> IS_GEMINILAKE(dev_priv))
>  			return
> glk_gamma_precision(crtc_state);
>  		else if (IS_IRONLAKE(dev_priv))
>  			return
> ilk_gamma_precision(crtc_state); @@ -1543,20 +1513,6 @@ static bool
> intel_color_lut_entry_equal(struct drm_color_lut *lut1,
>  	return true;
>  }
> 
> -static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> -					      struct
> drm_color_lut *lut2,
> -					      int
> lut_size, u32 err)
> -{
> -	int i;
> -
> -	for (i = 0; i < 9; i++) {
> -		if (!err_check(&lut1[i], &lut2[i], err))
> -			return false;
> -	}
> -
> -	return true;
> -}
> -
>  bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  			   struct drm_property_blob *blob2,
>  			   u32 gamma_mode, u32 bit_precision)
> @@ -1575,8 +1531,16 @@ bool intel_color_lut_equal(struct drm_property_blob
> *blob1,
>  	lut_size2 = drm_color_lut_size(blob2);
> 
>  	/* check sw and hw lut size */
> -	if (lut_size1 != lut_size2)
> -		return false;
> +	switch (gamma_mode) {
> +	case GAMMA_MODE_MODE_8BIT:
> +	case GAMMA_MODE_MODE_10BIT:
> +		if (lut_size1 != lut_size2)
> +			return false;
> +		break;
> +	default:
> +		MISSING_CASE(gamma_mode);
> +			return false;
> +	}
> 
>  	lut1 = blob1->data;
>  	lut2 = blob2->data;
> @@ -1584,18 +1548,13 @@ bool intel_color_lut_equal(struct drm_property_blob
> *blob1,
>  	err = 0xffff >> bit_precision;
> 
>  	/* check sw and hw lut entry to be equal */
> -	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
> +	switch (gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  	case GAMMA_MODE_MODE_10BIT:
>  		if (!intel_color_lut_entry_equal(lut1, lut2,
> 
> 	 lut_size2, err))
>  			return false;
>  		break;
> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> -		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> -
> 	       lut_size2, err))
> -			return false;
> -		break;
>  	default:
>  		MISSING_CASE(gamma_mode);
>  			return false;
> @@ -1835,60 +1794,6 @@ static void glk_read_luts(struct intel_crtc_state
> *crtc_state)
>  		crtc_state->base.gamma_lut =
> glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));  }
> 
> -static struct drm_property_blob *
> -icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> -	enum pipe pipe = crtc->pipe;
> -	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> -	u32 i, val1, val2;
> -
> -	blob = drm_property_create_blob(&dev_priv->drm,
> -
> 	sizeof(struct drm_color_lut) * lut_size,
> -					NULL);
> -	if (IS_ERR(blob))
> -		return NULL;
> -
> -	blob_data = blob->data;
> -
> -	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe),
> PAL_PREC_AUTO_INCREMENT);
> -
> -	for (i = 0; i < 9; i++) {
> -		val1 =
> I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> -		val2 =
> I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> -
> -		blob_data[i].red =
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> -
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> -		blob_data[i].green =
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> -
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> -		blob_data[i].blue =
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> -
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> -	}
> -
> -	/*
> -	 * FIXME readouts from PAL_PREC_DATA register aren't giving correct
> values
> -	 * in the case of fine and coarse segments. Restricting readouts only
> for
> -	 * super fine segment as of now.
> -	 */
> -
> -	return blob;
> -}
> -
> -static void icl_read_luts(struct intel_crtc_state *crtc_state) -{
> -	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> -	    GAMMA_MODE_MODE_8BIT)
> -		crtc_state->base.gamma_lut =
> i9xx_read_lut_8(crtc_state);
> -	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK)
> ==
> -		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> -		crtc_state->base.gamma_lut =
> icl_read_lut_multi_segment(crtc_state);
> -	else
> -		crtc_state->base.gamma_lut =
> glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> -}
> -
>  void intel_color_init(struct intel_crtc *crtc)  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
> 1932,7 +1837,6 @@ void intel_color_init(struct intel_crtc *crtc)
> 
>  		if (INTEL_GEN(dev_priv) >= 11) {
>  			dev_priv->display.load_luts =
> icl_load_luts;
> -			dev_priv->display.read_luts =
> icl_read_luts;
>  		} else if (IS_CANNONLAKE(dev_priv) ||
> IS_GEMINILAKE(dev_priv)) {
>  			dev_priv->display.load_luts =
> glk_load_luts;
>  			dev_priv->display.read_luts =
> glk_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index a69c19aae5bb..661cbe4c933a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10574,12 +10574,6 @@ enum skl_power_gate {
> 
>  #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
>  #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
> -#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
> -#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
> -#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) -
> #define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) -
> #define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4) -#define
> PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
> 
>  #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
> 
> 	_PAL_PREC_MULTI_SEG_INDEX_A, \
> --
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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✓ Fi.CI.IGT: success for Revert "drm/i915/color: Extract icl_read_luts()"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/color: Extract icl_read_luts()"
URL   : https://patchwork.freedesktop.org/series/67174/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6948_full -> Patchwork_14517_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14517_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#110854])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb2/igt@gem_exec_balancer@smoke.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb6/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#111325]) +5 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb5/igt@gem_exec_schedule@in-order-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +11 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_mmap_gtt@hang:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([fdo#109677])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb6/igt@gem_mmap_gtt@hang.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb7/igt@gem_mmap_gtt@hang.html

  * igt@i915_pm_rps@waitboost:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([fdo#102250])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-glk3/igt@i915_pm_rps@waitboost.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-glk8/igt@i915_pm_rps@waitboost.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-apl:          [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#105363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#107713])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +4 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-apl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][23] -> [INCOMPLETE][24] ([fdo#103665])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-skl:          [INCOMPLETE][27] ([fdo#104108]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl9/igt@gem_ctx_isolation@vecs0-s3.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl3/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_ctx_switch@rcs0-heavy-queue:
    - shard-iclb:         [INCOMPLETE][29] ([fdo#107713]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb7/igt@gem_ctx_switch@rcs0-heavy-queue.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb7/igt@gem_ctx_switch@rcs0-heavy-queue.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [FAIL][31] ([fdo#109661]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-snb1/igt@gem_eio@reset-stress.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-snb4/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][33] ([fdo#109276]) -> [PASS][34] +14 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][35] ([fdo#111325]) -> [PASS][36] +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-apl:          [INCOMPLETE][37] ([fdo#103927]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-apl6/igt@gem_pipe_control_store_loop@reused-buffer.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-apl8/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [DMESG-WARN][39] ([fdo#108686]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-apl5/igt@gem_tiled_swapping@non-threaded.html

  * {igt@i915_pm_dc@dc5-dpms}:
    - shard-iclb:         [FAIL][41] ([fdo#111795 ]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [INCOMPLETE][43] ([fdo#103540]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-hsw5/igt@kms_flip@flip-vs-suspend-interruptible.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-iclb:         [FAIL][45] ([fdo#103167]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - shard-iclb:         [INCOMPLETE][47] ([fdo#106978] / [fdo#107713]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][49] ([fdo#108145] / [fdo#110403]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][51] ([fdo#108145]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-iclb4/igt@kms_psr2_su@frontbuffer.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][55] ([fdo#99912]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-kbl7/igt@kms_setmode@basic.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-kbl:          [INCOMPLETE][57] ([fdo#103665]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf@blocking:
    - shard-skl:          [FAIL][59] ([fdo#110728]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl6/igt@perf@blocking.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl5/igt@perf@blocking.html

  * igt@perf@short-reads:
    - shard-skl:          [FAIL][61] ([fdo#103183]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6948/shard-skl9/igt@perf@short-reads.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/shard-skl10/igt@perf@short-reads.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#109677]: https://bugs.freedesktop.org/show_bug.cgi?id=109677
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6948 -> Patchwork_14517

  CI-20190529: 20190529
  CI_DRM_6948: 485ca160d8ffac7ffb5be5e76fa12ad46a7e5a19 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5201: 3c1633abec14679300d52eeaf9fb7b63e435e51e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14517: e44f42fed6415029bba2f88e3b23c985a85ed670 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14517/
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Re: [PATCH] Revert "drm/i915/color: Extract icl_read_luts()"

[Jani Nikula]

On Tue, 24 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> This reverts commit 84af7649188194a74cdd6437235a5e3c86108f0f.
>
> This is causing problems with the display, displays are all
> bright colors.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>

Pushed, thanks for the patch.

Now we do need to figure out how to do at least something useful and
non-regressing with icl/tgl readouts.

Could we add the legacy gamma checks first?

Also one other note inline below.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 126 +++------------------
>  drivers/gpu/drm/i915/i915_reg.h            |   6 -
>  2 files changed, 15 insertions(+), 117 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 402151128e1f..9ab34902663e 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1420,9 +1420,6 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>  
>  static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1436,9 +1433,6 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
>  		return 0;
>  
> @@ -1455,9 +1449,6 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>  		return 10;
>  	else
> @@ -1466,9 +1457,6 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -
>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1480,39 +1468,21 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> -{
> -	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> -		return 0;
> -
> -	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> -	case GAMMA_MODE_MODE_8BIT:
> -		return 8;
> -	case GAMMA_MODE_MODE_10BIT:
> -		return 10;
> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> -		return 16;
> -	default:
> -		MISSING_CASE(crtc_state->gamma_mode);
> -		return 0;
> -	}
> -
> -}
> -
>  int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +
>  	if (HAS_GMCH(dev_priv)) {
>  		if (IS_CHERRYVIEW(dev_priv))
>  			return chv_gamma_precision(crtc_state);
>  		else
>  			return i9xx_gamma_precision(crtc_state);
>  	} else {
> -		if (INTEL_GEN(dev_priv) >= 11)
> -			return icl_gamma_precision(crtc_state);
> -		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>  			return glk_gamma_precision(crtc_state);
>  		else if (IS_IRONLAKE(dev_priv))
>  			return ilk_gamma_precision(crtc_state);
> @@ -1543,20 +1513,6 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
>  	return true;
>  }
>  
> -static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> -					      struct drm_color_lut *lut2,
> -					      int lut_size, u32 err)
> -{
> -	int i;
> -
> -	for (i = 0; i < 9; i++) {
> -		if (!err_check(&lut1[i], &lut2[i], err))
> -			return false;
> -	}
> -
> -	return true;
> -}
> -
>  bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  			   struct drm_property_blob *blob2,
>  			   u32 gamma_mode, u32 bit_precision)
> @@ -1575,8 +1531,16 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  	lut_size2 = drm_color_lut_size(blob2);
>  
>  	/* check sw and hw lut size */
> -	if (lut_size1 != lut_size2)
> -		return false;
> +	switch (gamma_mode) {
> +	case GAMMA_MODE_MODE_8BIT:
> +	case GAMMA_MODE_MODE_10BIT:
> +		if (lut_size1 != lut_size2)
> +			return false;
> +		break;
> +	default:
> +		MISSING_CASE(gamma_mode);
> +			return false;
> +	}
>  
>  	lut1 = blob1->data;
>  	lut2 = blob2->data;
> @@ -1584,18 +1548,13 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  	err = 0xffff >> bit_precision;
>  
>  	/* check sw and hw lut entry to be equal */
> -	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
> +	switch (gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  	case GAMMA_MODE_MODE_10BIT:
>  		if (!intel_color_lut_entry_equal(lut1, lut2,
>  						 lut_size2, err))
>  			return false;
>  		break;
> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> -		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> -						       lut_size2, err))
> -			return false;
> -		break;
>  	default:
>  		MISSING_CASE(gamma_mode);
>  			return false;
> @@ -1835,60 +1794,6 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
>  		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
>  }
>  
> -static struct drm_property_blob *
> -icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> -	enum pipe pipe = crtc->pipe;
> -	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> -	u32 i, val1, val2;
> -
> -	blob = drm_property_create_blob(&dev_priv->drm,
> -					sizeof(struct drm_color_lut) * lut_size,
> -					NULL);
> -	if (IS_ERR(blob))
> -		return NULL;
> -
> -	blob_data = blob->data;
> -
> -	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> -
> -	for (i = 0; i < 9; i++) {
> -		val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> -		val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> -
> -		blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> -				   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> -		blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> -				     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> -		blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> -				    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> -	}
> -
> -	/*
> -	 * FIXME readouts from PAL_PREC_DATA register aren't giving correct values
> -	 * in the case of fine and coarse segments. Restricting readouts only for
> -	 * super fine segment as of now.
> -	 */
> -
> -	return blob;
> -}
> -
> -static void icl_read_luts(struct intel_crtc_state *crtc_state)
> -{
> -	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> -	    GAMMA_MODE_MODE_8BIT)
> -		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> -	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> -		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> -		crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
> -	else
> -		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> -}
> -
>  void intel_color_init(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1932,7 +1837,6 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>  		if (INTEL_GEN(dev_priv) >= 11) {
>  			dev_priv->display.load_luts = icl_load_luts;
> -			dev_priv->display.read_luts = icl_read_luts;
>  		} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>  			dev_priv->display.load_luts = glk_load_luts;
>  			dev_priv->display.read_luts = glk_read_luts;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a69c19aae5bb..661cbe4c933a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10574,12 +10574,6 @@ enum skl_power_gate {
>  
>  #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
>  #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
> -#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
> -#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
> -#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
> -#define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
> -#define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
> -#define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)

A patch adding just the register definitions could be merged as well.

>  
>  #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
>  					_PAL_PREC_MULTI_SEG_INDEX_A, \

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH] Revert "drm/i915/color: Extract icl_read_luts()"

[Jani Nikula]

On Wed, 25 Sep 2019, "Saarinen, Jani" <jani.saarinen@intel.com> wrote:
> Hi, 
>
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Swati
>> Sharma
>> Sent: tiistai 24. syyskuuta 2019 16.58
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; daniel.vetter@ffwll.ch; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>
>> Subject: [Intel-gfx] [PATCH] Revert "drm/i915/color: Extract icl_read_luts()"
>> 
>> This reverts commit 84af7649188194a74cdd6437235a5e3c86108f0f.
>> 
>> This is causing problems with the display, displays are all bright colors.
>
> Tested-by: Jani Saarinen <jani.saarinen@intel.com>
> Bugzilla:  https://bugs.freedesktop.org/show_bug.cgi?id=111809

Apologies, missed these before pushing. :(

BR,
Jani.

>
>> 
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_color.c | 126 +++------------------
>>  drivers/gpu/drm/i915/i915_reg.h            |   6 -
>>  2 files changed, 15 insertions(+), 117 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
>> b/drivers/gpu/drm/i915/display/intel_color.c
>> index 402151128e1f..9ab34902663e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -1420,9 +1420,6 @@ static int icl_color_check(struct intel_crtc_state
>> *crtc_state)
>> 
>>  static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)  {
>> -	if (!crtc_state->gamma_enable)
>> -		return 0;
>> -
>>  	switch (crtc_state->gamma_mode) {
>>  	case GAMMA_MODE_MODE_8BIT:
>>  		return 8;
>> @@ -1436,9 +1433,6 @@ static int i9xx_gamma_precision(const struct
>> intel_crtc_state *crtc_state)
>> 
>>  static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)  {
>> -	if (!crtc_state->gamma_enable)
>> -		return 0;
>> -
>>  	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
>>  		return 0;
>> 
>> @@ -1455,9 +1449,6 @@ static int ilk_gamma_precision(const struct
>> intel_crtc_state *crtc_state)
>> 
>>  static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)  {
>> -	if (!crtc_state->gamma_enable)
>> -		return 0;
>> -
>>  	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>>  		return 10;
>>  	else
>> @@ -1466,9 +1457,6 @@ static int chv_gamma_precision(const struct
>> intel_crtc_state *crtc_state)
>> 
>>  static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)  {
>> -	if (!crtc_state->gamma_enable)
>> -		return 0;
>> -
>>  	switch (crtc_state->gamma_mode) {
>>  	case GAMMA_MODE_MODE_8BIT:
>>  		return 8;
>> @@ -1480,39 +1468,21 @@ static int glk_gamma_precision(const struct
>> intel_crtc_state *crtc_state)
>>  	}
>>  }
>> 
>> -static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) -{
>> -	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
>> -		return 0;
>> -
>> -	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
>> -	case GAMMA_MODE_MODE_8BIT:
>> -		return 8;
>> -	case GAMMA_MODE_MODE_10BIT:
>> -		return 10;
>> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
>> -		return 16;
>> -	default:
>> -		MISSING_CASE(crtc_state->gamma_mode);
>> -		return 0;
>> -	}
>> -
>> -}
>> -
>>  int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
>> {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> 
>> +	if (!crtc_state->gamma_enable)
>> +		return 0;
>> +
>>  	if (HAS_GMCH(dev_priv)) {
>>  		if (IS_CHERRYVIEW(dev_priv))
>>  			return
>> chv_gamma_precision(crtc_state);
>>  		else
>>  			return
>> i9xx_gamma_precision(crtc_state);
>>  	} else {
>> -		if (INTEL_GEN(dev_priv) >= 11)
>> -			return
>> icl_gamma_precision(crtc_state);
>> -		else if (IS_CANNONLAKE(dev_priv) ||
>> IS_GEMINILAKE(dev_priv))
>> +		if (IS_CANNONLAKE(dev_priv) ||
>> IS_GEMINILAKE(dev_priv))
>>  			return
>> glk_gamma_precision(crtc_state);
>>  		else if (IS_IRONLAKE(dev_priv))
>>  			return
>> ilk_gamma_precision(crtc_state); @@ -1543,20 +1513,6 @@ static bool
>> intel_color_lut_entry_equal(struct drm_color_lut *lut1,
>>  	return true;
>>  }
>> 
>> -static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
>> -					      struct
>> drm_color_lut *lut2,
>> -					      int
>> lut_size, u32 err)
>> -{
>> -	int i;
>> -
>> -	for (i = 0; i < 9; i++) {
>> -		if (!err_check(&lut1[i], &lut2[i], err))
>> -			return false;
>> -	}
>> -
>> -	return true;
>> -}
>> -
>>  bool intel_color_lut_equal(struct drm_property_blob *blob1,
>>  			   struct drm_property_blob *blob2,
>>  			   u32 gamma_mode, u32 bit_precision)
>> @@ -1575,8 +1531,16 @@ bool intel_color_lut_equal(struct drm_property_blob
>> *blob1,
>>  	lut_size2 = drm_color_lut_size(blob2);
>> 
>>  	/* check sw and hw lut size */
>> -	if (lut_size1 != lut_size2)
>> -		return false;
>> +	switch (gamma_mode) {
>> +	case GAMMA_MODE_MODE_8BIT:
>> +	case GAMMA_MODE_MODE_10BIT:
>> +		if (lut_size1 != lut_size2)
>> +			return false;
>> +		break;
>> +	default:
>> +		MISSING_CASE(gamma_mode);
>> +			return false;
>> +	}
>> 
>>  	lut1 = blob1->data;
>>  	lut2 = blob2->data;
>> @@ -1584,18 +1548,13 @@ bool intel_color_lut_equal(struct drm_property_blob
>> *blob1,
>>  	err = 0xffff >> bit_precision;
>> 
>>  	/* check sw and hw lut entry to be equal */
>> -	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
>> +	switch (gamma_mode) {
>>  	case GAMMA_MODE_MODE_8BIT:
>>  	case GAMMA_MODE_MODE_10BIT:
>>  		if (!intel_color_lut_entry_equal(lut1, lut2,
>> 
>> 	 lut_size2, err))
>>  			return false;
>>  		break;
>> -	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
>> -		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
>> -
>> 	       lut_size2, err))
>> -			return false;
>> -		break;
>>  	default:
>>  		MISSING_CASE(gamma_mode);
>>  			return false;
>> @@ -1835,60 +1794,6 @@ static void glk_read_luts(struct intel_crtc_state
>> *crtc_state)
>>  		crtc_state->base.gamma_lut =
>> glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));  }
>> 
>> -static struct drm_property_blob *
>> -icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) -{
>> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> -	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> -	enum pipe pipe = crtc->pipe;
>> -	struct drm_property_blob *blob;
>> -	struct drm_color_lut *blob_data;
>> -	u32 i, val1, val2;
>> -
>> -	blob = drm_property_create_blob(&dev_priv->drm,
>> -
>> 	sizeof(struct drm_color_lut) * lut_size,
>> -					NULL);
>> -	if (IS_ERR(blob))
>> -		return NULL;
>> -
>> -	blob_data = blob->data;
>> -
>> -	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe),
>> PAL_PREC_AUTO_INCREMENT);
>> -
>> -	for (i = 0; i < 9; i++) {
>> -		val1 =
>> I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
>> -		val2 =
>> I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
>> -
>> -		blob_data[i].red =
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
>> -
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
>> -		blob_data[i].green =
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
>> -
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
>> -		blob_data[i].blue =
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
>> -
>> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
>> -	}
>> -
>> -	/*
>> -	 * FIXME readouts from PAL_PREC_DATA register aren't giving correct
>> values
>> -	 * in the case of fine and coarse segments. Restricting readouts only
>> for
>> -	 * super fine segment as of now.
>> -	 */
>> -
>> -	return blob;
>> -}
>> -
>> -static void icl_read_luts(struct intel_crtc_state *crtc_state) -{
>> -	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
>> -	    GAMMA_MODE_MODE_8BIT)
>> -		crtc_state->base.gamma_lut =
>> i9xx_read_lut_8(crtc_state);
>> -	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK)
>> ==
>> -		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
>> -		crtc_state->base.gamma_lut =
>> icl_read_lut_multi_segment(crtc_state);
>> -	else
>> -		crtc_state->base.gamma_lut =
>> glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
>> -}
>> -
>>  void intel_color_init(struct intel_crtc *crtc)  {
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
>> 1932,7 +1837,6 @@ void intel_color_init(struct intel_crtc *crtc)
>> 
>>  		if (INTEL_GEN(dev_priv) >= 11) {
>>  			dev_priv->display.load_luts =
>> icl_load_luts;
>> -			dev_priv->display.read_luts =
>> icl_read_luts;
>>  		} else if (IS_CANNONLAKE(dev_priv) ||
>> IS_GEMINILAKE(dev_priv)) {
>>  			dev_priv->display.load_luts =
>> glk_load_luts;
>>  			dev_priv->display.read_luts =
>> glk_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index a69c19aae5bb..661cbe4c933a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10574,12 +10574,6 @@ enum skl_power_gate {
>> 
>>  #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
>>  #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
>> -#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
>> -#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
>> -#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) -
>> #define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) -
>> #define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4) -#define
>> PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
>> 
>>  #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
>> 
>> 	_PAL_PREC_MULTI_SEG_INDEX_A, \
>> --
>> 2.23.0
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
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