[v2][PATCH 0/3] adding gamma state checker for icl+ platforms

[v2][PATCH 0/3] adding gamma state checker for icl+ platforms

[Swati Sharma]

In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.

Swati Sharma (3):
  drm/i915/display: Fix formatting issues
  drm/i915/display: Extract icl_read_luts()
  FOR_TESTING_ONLY: Print rgb values of hw and sw blobs

 drivers/gpu/drm/i915/display/intel_color.c | 260 +++++++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h            |   7 +
 2 files changed, 238 insertions(+), 29 deletions(-)

-- 
1.9.1

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[v2][PATCH 1/3] drm/i915/display: Fix formatting issues

[Swati Sharma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 318308d..b1f0f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	u32 i;
 
 	/*
-	 * Every entry in the multi-segment LUT is corresponding to a superfine
-	 * segment step which is 1/(8 * 128 * 256).
+	 * Program Super Fine segment (let's call it seg1)...
 	 *
-	 * Superfine segment has 9 entries, corresponding to values
-	 * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
+	 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
+	 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
+	 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 	 */
 	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 
@@ -837,10 +837,9 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	u32 i;
 
 	/*
-	 *
 	 * Program Fine segment (let's call it seg2)...
 	 *
-	 * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256),  2/(128*256)
+	 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256),  2/(128*256)
 	 * ... 256/(128*256). So in order to program fine segment of LUT we
 	 * need to pick every 8'th entry in LUT, and program 256 indexes.
 	 *
@@ -858,7 +857,7 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 	 * Program Coarse segment (let's call it seg3)...
 	 *
 	 * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
-	 * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
+	 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 	 * above, we need to pick every (8 * 128)th entry in LUT, and
 	 * program 256 of those.
 	 *
@@ -890,12 +889,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_8BIT:
 		i9xx_load_luts(crtc_state);
 		break;
-
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
 		icl_program_gamma_multi_segment(crtc_state);
 		break;
-
 	default:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);
-- 
1.9.1

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Re: [v2][PATCH 1/3] drm/i915/display: Fix formatting issues

[Jani Nikula]

Subject prefix "drm/i915/display" is a fairly broad
statement. "drm/i915/color" perhaps.

Please add a commit message. See git log. We don't approve of empty
commit messages.

On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 318308d..b1f0f7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	u32 i;
>  
>  	/*
> -	 * Every entry in the multi-segment LUT is corresponding to a superfine
> -	 * segment step which is 1/(8 * 128 * 256).
> +	 * Program Super Fine segment (let's call it seg1)...
>  	 *
> -	 * Superfine segment has 9 entries, corresponding to values
> -	 * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
> +	 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
> +	 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
> +	 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
>  	 */
>  	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
>  
> @@ -837,10 +837,9 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	u32 i;
>  
>  	/*
> -	 *
>  	 * Program Fine segment (let's call it seg2)...
>  	 *
> -	 * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256),  2/(128*256)
> +	 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256),  2/(128*256)
	                                                            ^
Since you're cleaning this up... extra space there. And some of the
items have (128 * 256) and others (128*256).

I wouldn't care otherwise, but why fix some punctuation and leave this
behind.

>  	 * ... 256/(128*256). So in order to program fine segment of LUT we
>  	 * need to pick every 8'th entry in LUT, and program 256 indexes.
>  	 *
> @@ -858,7 +857,7 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
>  	 * Program Coarse segment (let's call it seg3)...
>  	 *
>  	 * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
> -	 * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
> +	 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
>  	 * above, we need to pick every (8 * 128)th entry in LUT, and
>  	 * program 256 of those.
>  	 *
> @@ -890,12 +889,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>  	case GAMMA_MODE_MODE_8BIT:
>  		i9xx_load_luts(crtc_state);
>  		break;
> -
>  	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
>  		icl_program_gamma_superfine_segment(crtc_state);
>  		icl_program_gamma_multi_segment(crtc_state);
>  		break;
> -
>  	default:
>  		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
>  		ivb_load_lut_ext_max(crtc);

-- 
Jani Nikula, Intel Open Source Graphics Center
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[v2][PATCH 2/3] drm/i915/display: Extract icl_read_luts()

[Swati Sharma]

For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode, add hw lut creation for this mode.

This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl feature.

v2: -readout code for multisegmented gamma has to come
     up with some intermediate entries that aren't preserved
     in hardware (Jani N)
    -linear interpolation (Ville)
    -moved common code to check gamma_enable to specific funcs,
     since icl doesn't support that

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 243 ++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h            |   7 +
 2 files changed, 230 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index b1f0f7e..0008011 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1370,6 +1370,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
 
 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+	if (!crtc_state->gamma_enable)
+		return 0;
+
 	switch (crtc_state->gamma_mode) {
 	case GAMMA_MODE_MODE_8BIT:
 		return 8;
@@ -1383,6 +1386,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+	if (!crtc_state->gamma_enable)
+		return 0;
+
 	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
 		return 0;
 
@@ -1399,6 +1405,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+	if (!crtc_state->gamma_enable)
+		return 0;
+
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
 		return 10;
 	else
@@ -1407,6 +1416,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+	if (!crtc_state->gamma_enable)
+		return 0;
+
 	switch (crtc_state->gamma_mode) {
 	case GAMMA_MODE_MODE_8BIT:
 		return 8;
@@ -1418,21 +1430,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+		return 0;
+
+	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+	case GAMMA_MODE_MODE_8BIT:
+		return 8;
+	case GAMMA_MODE_MODE_10BIT:
+		return 10;
+	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+		return 16;  
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		return 0;
+	}
+
+}
+
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (!crtc_state->gamma_enable)
-		return 0;
-
 	if (HAS_GMCH(dev_priv)) {
 		if (IS_CHERRYVIEW(dev_priv))
 			return chv_gamma_precision(crtc_state);
 		else
 			return i9xx_gamma_precision(crtc_state);
 	} else {
-		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 11)
+			return icl_gamma_precision(crtc_state);
+		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			return glk_gamma_precision(crtc_state);
 		else if (IS_IRONLAKE(dev_priv))
 			return ilk_gamma_precision(crtc_state);
@@ -1463,6 +1493,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
 	return true;
 }
 
+static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
+					      struct drm_color_lut *lut2,
+					      int lut_size, u32 err)
+{
+	int i;
+
+	for (i = 0; i < 9; i++) {
+		if (!err_check(&lut1[i], &lut2[i], err))
+			return false;
+	}
+
+	for (i = 1; i <  257; i++) {
+		if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
+			return false;
+	}
+
+	for (i = 0; i < 256; i++) {
+		if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
+			return false;
+	}
+
+	return true;
+}
+
 bool intel_color_lut_equal(struct drm_property_blob *blob1,
 			   struct drm_property_blob *blob2,
 			   u32 gamma_mode, u32 bit_precision)
@@ -1481,16 +1535,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	lut_size2 = drm_color_lut_size(blob2);
 
 	/* check sw and hw lut size */
-	switch (gamma_mode) {
-	case GAMMA_MODE_MODE_8BIT:
-	case GAMMA_MODE_MODE_10BIT:
-		if (lut_size1 != lut_size2)
-			return false;
-		break;
-	default:
-		MISSING_CASE(gamma_mode);
-			return false;
-	}
+	if (lut_size1 != lut_size2)
+		return false;
 
 	lut1 = blob1->data;
 	lut2 = blob2->data;
@@ -1498,13 +1544,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	err = 0xffff >> bit_precision;
 
 	/* check sw and hw lut entry to be equal */
-	switch (gamma_mode) {
+	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
 	case GAMMA_MODE_MODE_8BIT:
 	case GAMMA_MODE_MODE_10BIT:
 		if (!intel_color_lut_entry_equal(lut1, lut2,
 						 lut_size2, err))
 			return false;
 		break;
+	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
+						       lut_size2, err))
+			return false;
+		break;
 	default:
 		MISSING_CASE(gamma_mode);
 			return false;
@@ -1744,6 +1795,157 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
 
+static struct drm_color_lut *
+icl_compute_interpolated_gamma_blob(struct drm_color_lut *tmp_lut,
+				    struct drm_color_lut *lut, u32 lut_size)
+{
+	__u16 a_red, b_red, a_green, b_green, a_blue, b_blue;
+	__u16 red_step, green_step, blue_step;
+	int i, j, k, m, n;
+
+	for (i = 0, k = 0; k < 9; i++, k++) {
+		lut[i].red = tmp_lut[k].red;
+		lut[i].green = tmp_lut[k].green;
+		lut[i].blue = tmp_lut[k].blue;
+	}
+
+	for (k = 9; k < 264; k++) {
+		a_red = tmp_lut[k].red;
+		b_red = tmp_lut[k + 1].red;
+		red_step = (b_red - a_red) / 8;
+
+		a_green = tmp_lut[k].green;
+		b_green = tmp_lut[k + 1].green;
+		green_step = (b_green - a_green) / 8;
+
+		a_blue = tmp_lut[k].blue;
+		b_blue = tmp_lut[k + 1].blue;
+		blue_step = (b_blue - a_blue) / 8;
+
+		for (j = 0; j < 8; j++) {
+			lut[i].red = lut[i - 1].red + red_step;
+			lut[i].green = lut[i - 1].green + green_step;
+			lut[i].blue = lut[i - 1].blue + blue_step;
+
+			i++;
+		}
+	}
+
+	for (k = 265; k < 521; k++) {
+		a_red = tmp_lut[k].red;
+		b_red = tmp_lut[k + 1].red;
+		red_step = ((b_red - a_red) / 127) / 8;
+
+		a_green = tmp_lut[k].green;
+		b_green = tmp_lut[k + 1].green;
+		green_step = ((b_green - a_green) / 127) / 8;
+
+		a_blue = tmp_lut[k].blue;
+		b_blue = tmp_lut[k + 1].blue;
+		blue_step = ((b_blue - a_blue) / 127) / 8;
+
+		for (m = 0; m < 127; m++) {
+			for (n = 0; n < 8; n++) {
+				lut[i].red = lut[i - 1].red + red_step;
+				lut[i].green = lut[i - 1].green + green_step;
+				lut[i].blue = lut[i - 1].blue + blue_step;
+
+				i++;
+			}
+		}
+	}
+
+	return lut;
+}
+
+static struct drm_property_blob *
+icl_read_lut_multi_seg(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int tmp_lut_size = 522;
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob, *tmp_blob;
+	struct drm_color_lut *blob_data, *tmp_blob_data;
+	u32 i, val1, val2;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * lut_size,
+					NULL);
+	tmp_blob = drm_property_create_blob(&dev_priv->drm,
+					    sizeof(struct drm_color_lut) * tmp_lut_size,
+					    NULL);
+	if (IS_ERR(blob) || IS_ERR(tmp_blob))
+		return NULL;
+
+	blob_data = blob->data;
+	tmp_blob_data = tmp_blob->data;
+
+	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+	for (i = 0; i < 9; i++) {
+		val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+		val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+
+		tmp_blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+				       REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+		tmp_blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+					 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+		tmp_blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+					REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+	}
+
+	I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+	for (i = 1; i < 257; i++) {
+		val1 = I915_READ(PREC_PAL_DATA(pipe));
+		val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+		tmp_blob_data[i + 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+					   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+		tmp_blob_data[i + 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+					     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+		tmp_blob_data[i + 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+					    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+	}
+
+	for (i = 0; i < 256; i++) {
+		val1 = I915_READ(PREC_PAL_DATA(pipe));
+		val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+		tmp_blob_data[i + 265].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+					     REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+		tmp_blob_data[i + 265].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+					       REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+		tmp_blob_data[i + 265].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+					      REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+	}
+
+	tmp_blob_data[521].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+					       I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
+	tmp_blob_data[521].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+						 I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
+	tmp_blob_data[521].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+						I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
+
+	blob_data = icl_compute_interpolated_gamma_blob(tmp_blob_data, blob_data, lut_size);
+
+	return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+	    GAMMA_MODE_MODE_8BIT)
+		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+		crtc_state->base.gamma_lut = icl_read_lut_multi_seg(crtc_state);
+	else
+		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1785,16 +1987,17 @@ void intel_color_init(struct intel_crtc *crtc)
 		else
 			dev_priv->display.color_commit = ilk_color_commit;
 
-		if (INTEL_GEN(dev_priv) >= 11)
+		if (INTEL_GEN(dev_priv) >= 11) {
 			dev_priv->display.load_luts = icl_load_luts;
-		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+			dev_priv->display.read_luts = icl_read_luts;
+		} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
 			dev_priv->display.load_luts = glk_load_luts;
 			dev_priv->display.read_luts = glk_read_luts;
-		} else if (INTEL_GEN(dev_priv) >= 8)
+		} else if (INTEL_GEN(dev_priv) >= 8) {
 			dev_priv->display.load_luts = bdw_load_luts;
-		else if (INTEL_GEN(dev_priv) >= 7)
+		} else if (INTEL_GEN(dev_priv) >= 7) {
 			dev_priv->display.load_luts = ivb_load_luts;
-		else {
+		} else {
 			dev_priv->display.load_luts = ilk_load_luts;
 			dev_priv->display.read_luts = ilk_read_luts;
 		}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ece..844dd62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10378,6 +10378,7 @@ enum skl_power_gate {
 
 #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
 #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
+#define PREC_PAL_GC_MAX_RGB_MASK	 REG_GENMASK(15, 0)
 #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
 #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
 #define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
@@ -10401,6 +10402,12 @@ enum skl_power_gate {
 
 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
+#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
+#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
+#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
+#define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
 
 #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
 					_PAL_PREC_MULTI_SEG_INDEX_A, \
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
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Re: [v2][PATCH 2/3] drm/i915/display: Extract icl_read_luts()

[Jani Nikula]

On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl feature.
>
> v2: -readout code for multisegmented gamma has to come
>      up with some intermediate entries that aren't preserved
>      in hardware (Jani N)
>     -linear interpolation (Ville)
>     -moved common code to check gamma_enable to specific funcs,
>      since icl doesn't support that
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 243 ++++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h            |   7 +
>  2 files changed, 230 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index b1f0f7e..0008011 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1370,6 +1370,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>  
>  static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +

Why are you moving these checks back to the individual functions?

>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1383,6 +1386,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +
>  	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
>  		return 0;
>  
> @@ -1399,6 +1405,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +
>  	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
>  		return 10;
>  	else
> @@ -1407,6 +1416,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  {
> +	if (!crtc_state->gamma_enable)
> +		return 0;
> +
>  	switch (crtc_state->gamma_mode) {
>  	case GAMMA_MODE_MODE_8BIT:
>  		return 8;
> @@ -1418,21 +1430,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> +	if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> +		return 0;
> +
> +	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> +	case GAMMA_MODE_MODE_8BIT:
> +		return 8;
> +	case GAMMA_MODE_MODE_10BIT:
> +		return 10;
> +	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> +		return 16;  
> +	default:
> +		MISSING_CASE(crtc_state->gamma_mode);
> +		return 0;
> +	}
> +
> +}
> +
>  int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (!crtc_state->gamma_enable)
> -		return 0;
> -

Why?

>  	if (HAS_GMCH(dev_priv)) {
>  		if (IS_CHERRYVIEW(dev_priv))
>  			return chv_gamma_precision(crtc_state);
>  		else
>  			return i9xx_gamma_precision(crtc_state);
>  	} else {
> -		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> +		if (INTEL_GEN(dev_priv) >= 11)
> +			return icl_gamma_precision(crtc_state);
> +		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>  			return glk_gamma_precision(crtc_state);
>  		else if (IS_IRONLAKE(dev_priv))
>  			return ilk_gamma_precision(crtc_state);
> @@ -1463,6 +1493,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
>  	return true;
>  }
>  
> +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> +					      struct drm_color_lut *lut2,
> +					      int lut_size, u32 err)
> +{
> +	int i;
> +
> +	for (i = 0; i < 9; i++) {
> +		if (!err_check(&lut1[i], &lut2[i], err))
> +			return false;
> +	}
> +
> +	for (i = 1; i <  257; i++) {
                       ^
                       extra space

> +		if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
> +			return false;
> +	}

i == 8 will be checked twice.

> +
> +	for (i = 0; i < 256; i++) {
> +		if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
> +			return false;
> +	}

i == 0 will be checked twice.

I note that these indices match the programming part, so maybe better to
keep them as they are here. No harm done I guess.

> +
> +	return true;
> +}
> +
>  bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  			   struct drm_property_blob *blob2,
>  			   u32 gamma_mode, u32 bit_precision)
> @@ -1481,16 +1535,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  	lut_size2 = drm_color_lut_size(blob2);
>  
>  	/* check sw and hw lut size */
> -	switch (gamma_mode) {
> -	case GAMMA_MODE_MODE_8BIT:
> -	case GAMMA_MODE_MODE_10BIT:
> -		if (lut_size1 != lut_size2)
> -			return false;
> -		break;
> -	default:
> -		MISSING_CASE(gamma_mode);
> -			return false;
> -	}
> +	if (lut_size1 != lut_size2)
> +		return false;
>  
>  	lut1 = blob1->data;
>  	lut2 = blob2->data;
> @@ -1498,13 +1544,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>  	err = 0xffff >> bit_precision;
>  
>  	/* check sw and hw lut entry to be equal */
> -	switch (gamma_mode) {
> +	switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
>  	case GAMMA_MODE_MODE_8BIT:
>  	case GAMMA_MODE_MODE_10BIT:
>  		if (!intel_color_lut_entry_equal(lut1, lut2,
>  						 lut_size2, err))
>  			return false;
>  		break;
> +	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> +		if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> +						       lut_size2, err))
> +			return false;
> +		break;
>  	default:
>  		MISSING_CASE(gamma_mode);
>  			return false;
> @@ -1744,6 +1795,157 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
>  		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
>  }
>  
> +static struct drm_color_lut *
> +icl_compute_interpolated_gamma_blob(struct drm_color_lut *tmp_lut,
> +				    struct drm_color_lut *lut, u32 lut_size)
> +{

I think you should just pass in the the actual lut, and not use a temp
lut at all. See my comments below for icl_read_lut_multi_seg() function.

> +	__u16 a_red, b_red, a_green, b_green, a_blue, b_blue;
> +	__u16 red_step, green_step, blue_step;

u16, not __u16.

> +	int i, j, k, m, n;
> +
> +	for (i = 0, k = 0; k < 9; i++, k++) {
> +		lut[i].red = tmp_lut[k].red;
> +		lut[i].green = tmp_lut[k].green;
> +		lut[i].blue = tmp_lut[k].blue;
> +	}

With a single lut, you can skip this.

> +
> +	for (k = 9; k < 264; k++) {
> +		a_red = tmp_lut[k].red;
> +		b_red = tmp_lut[k + 1].red;
> +		red_step = (b_red - a_red) / 8;
> +
> +		a_green = tmp_lut[k].green;
> +		b_green = tmp_lut[k + 1].green;
> +		green_step = (b_green - a_green) / 8;
> +
> +		a_blue = tmp_lut[k].blue;
> +		b_blue = tmp_lut[k + 1].blue;
> +		blue_step = (b_blue - a_blue) / 8;
> +
> +		for (j = 0; j < 8; j++) {
> +			lut[i].red = lut[i - 1].red + red_step;
> +			lut[i].green = lut[i - 1].green + green_step;
> +			lut[i].blue = lut[i - 1].blue + blue_step;
> +
> +			i++;
> +		}
> +	}

This would be written in a way to only cover the values that need to be
interpolated.

	for (i = 1; i < 257 - 1; i++) {
        	start = i * 8;
                end = (i + 1) * 8;
                steps = end - start;

                for (j = start + 1; j < end; j++) {
                }
        }

Fill in the gaps. For me I think this is easier to grasp and compare
against the readout and write. I find it very hard to check the ranges
in the loops.

> +
> +	for (k = 265; k < 521; k++) {
> +		a_red = tmp_lut[k].red;
> +		b_red = tmp_lut[k + 1].red;
> +		red_step = ((b_red - a_red) / 127) / 8;
> +
> +		a_green = tmp_lut[k].green;
> +		b_green = tmp_lut[k + 1].green;
> +		green_step = ((b_green - a_green) / 127) / 8;
> +
> +		a_blue = tmp_lut[k].blue;
> +		b_blue = tmp_lut[k + 1].blue;
> +		blue_step = ((b_blue - a_blue) / 127) / 8;
> +
> +		for (m = 0; m < 127; m++) {
> +			for (n = 0; n < 8; n++) {
> +				lut[i].red = lut[i - 1].red + red_step;
> +				lut[i].green = lut[i - 1].green + green_step;
> +				lut[i].blue = lut[i - 1].blue + blue_step;
> +
> +				i++;
> +			}
> +		}
> +	}

Similarly:

	for (i = 0; i < 256 - 1; i++) {
        	start = i * 8 * 128;
                end = (i + 1) * 8 * 128;
                steps = end - start;

                for (j = start + 1; j < end; j++) {
                }
        }


> +
> +	return lut;
> +}
> +
> +static struct drm_property_blob *
> +icl_read_lut_multi_seg(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	int tmp_lut_size = 522;
> +	enum pipe pipe = crtc->pipe;
> +	struct drm_property_blob *blob, *tmp_blob;
> +	struct drm_color_lut *blob_data, *tmp_blob_data;
> +	u32 i, val1, val2;
> +
> +	blob = drm_property_create_blob(&dev_priv->drm,
> +					sizeof(struct drm_color_lut) * lut_size,
> +					NULL);
> +	tmp_blob = drm_property_create_blob(&dev_priv->drm,
> +					    sizeof(struct drm_color_lut) * tmp_lut_size,
> +					    NULL);

You end up leaking the temporary blob. But I don't think you really need
the temporary blob at all. Read on.

> +	if (IS_ERR(blob) || IS_ERR(tmp_blob))
> +		return NULL;
> +
> +	blob_data = blob->data;
> +	tmp_blob_data = tmp_blob->data;
> +
> +	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> +	for (i = 0; i < 9; i++) {
> +		val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> +		val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> +
> +		tmp_blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> +				       REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> +		tmp_blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> +					 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> +		tmp_blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> +					REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> +	}
> +
> +	I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> +	for (i = 1; i < 257; i++) {
> +		val1 = I915_READ(PREC_PAL_DATA(pipe));
> +		val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> +		tmp_blob_data[i + 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> +					   REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> +		tmp_blob_data[i + 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> +					     REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> +		tmp_blob_data[i + 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> +					    REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> +	}
> +
> +	for (i = 0; i < 256; i++) {
> +		val1 = I915_READ(PREC_PAL_DATA(pipe));
> +		val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> +		tmp_blob_data[i + 265].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> +					     REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> +		tmp_blob_data[i + 265].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> +					       REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> +		tmp_blob_data[i + 265].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> +					      REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> +	}
> +
> +	tmp_blob_data[521].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> +					       I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
> +	tmp_blob_data[521].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> +						 I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> +	tmp_blob_data[521].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> +						I915_READ(PREC_PAL_GC_MAX(pipe, 1)));

In the above, I think you should just read the values directly to the
right locations in the actual blob. Then all the indices match the
programming side, and it's easier to review.

> +
> +	blob_data = icl_compute_interpolated_gamma_blob(tmp_blob_data, blob_data, lut_size);

And then you fill in the gaps in the interpolation function.

> +
> +	return blob;
> +}
> +
> +static void icl_read_luts(struct intel_crtc_state *crtc_state)
> +{
> +	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> +	    GAMMA_MODE_MODE_8BIT)
> +		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +	else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> +		 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> +		crtc_state->base.gamma_lut = icl_read_lut_multi_seg(crtc_state);
> +	else
> +		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +}
> +
>  void intel_color_init(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1785,16 +1987,17 @@ void intel_color_init(struct intel_crtc *crtc)
>  		else
>  			dev_priv->display.color_commit = ilk_color_commit;
>  
> -		if (INTEL_GEN(dev_priv) >= 11)
> +		if (INTEL_GEN(dev_priv) >= 11) {
>  			dev_priv->display.load_luts = icl_load_luts;
> -		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> +			dev_priv->display.read_luts = icl_read_luts;
> +		} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>  			dev_priv->display.load_luts = glk_load_luts;
>  			dev_priv->display.read_luts = glk_read_luts;
> -		} else if (INTEL_GEN(dev_priv) >= 8)
> +		} else if (INTEL_GEN(dev_priv) >= 8) {
>  			dev_priv->display.load_luts = bdw_load_luts;
> -		else if (INTEL_GEN(dev_priv) >= 7)
> +		} else if (INTEL_GEN(dev_priv) >= 7) {
>  			dev_priv->display.load_luts = ivb_load_luts;
> -		else {
> +		} else {

Shouldn't the cleanup be part of patch 1?

>  			dev_priv->display.load_luts = ilk_load_luts;
>  			dev_priv->display.read_luts = ilk_read_luts;
>  		}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ece..844dd62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10378,6 +10378,7 @@ enum skl_power_gate {
>  
>  #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
>  #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
> +#define PREC_PAL_GC_MAX_RGB_MASK	 REG_GENMASK(15, 0)
>  #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
>  #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
>  #define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
> @@ -10401,6 +10402,12 @@ enum skl_power_gate {
>  
>  #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
>  #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
> +#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
> +#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
> +#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
> +#define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
> +#define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
> +#define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
>  
>  #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
>  					_PAL_PREC_MULTI_SEG_INDEX_A, \

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [v2][PATCH 2/3] drm/i915/display: Extract icl_read_luts()

[Sharma, Swati2]

On 18-Sep-19 3:31 PM, Jani Nikula wrote:
> On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
>> For icl+, have hw read out to create hw blob of gamma
>> lut values. icl+ platforms supports multi segmented gamma
>> mode, add hw lut creation for this mode.
>>
>> This will be used to validate gamma programming using dsb
>> (display state buffer) which is a tgl feature.
>>
>> v2: -readout code for multisegmented gamma has to come
>>       up with some intermediate entries that aren't preserved
>>       in hardware (Jani N)
>>      -linear interpolation (Ville)
>>      -moved common code to check gamma_enable to specific funcs,
>>       since icl doesn't support that
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_color.c | 243 ++++++++++++++++++++++++++---
>>   drivers/gpu/drm/i915/i915_reg.h            |   7 +
>>   2 files changed, 230 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index b1f0f7e..0008011 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -1370,6 +1370,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>>   
>>   static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>>   {
>> +	if (!crtc_state->gamma_enable)
>> +		return 0;    >> +
> 
> Why are you moving these checks back to the individual functions?
As stated in commit message, moved common code to check gamma_enable to 
specific funcs, since icl doesn't support gamma_enable and code will 
return 0. If i need to make it generic, i need to make gamma_enable true 
in icl_color_check() func. Is it fine? ICL enables gamma through 
gamma_mode unlike other platforms.


-- 
~Swati Sharma
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Re: [v2][PATCH 2/3] drm/i915/display: Extract icl_read_luts()

[Jani Nikula]

On Wed, 18 Sep 2019, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
> On 18-Sep-19 3:31 PM, Jani Nikula wrote:
>> On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
>>> For icl+, have hw read out to create hw blob of gamma
>>> lut values. icl+ platforms supports multi segmented gamma
>>> mode, add hw lut creation for this mode.
>>>
>>> This will be used to validate gamma programming using dsb
>>> (display state buffer) which is a tgl feature.
>>>
>>> v2: -readout code for multisegmented gamma has to come
>>>       up with some intermediate entries that aren't preserved
>>>       in hardware (Jani N)
>>>      -linear interpolation (Ville)
>>>      -moved common code to check gamma_enable to specific funcs,
>>>       since icl doesn't support that
>>>
>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_color.c | 243 ++++++++++++++++++++++++++---
>>>   drivers/gpu/drm/i915/i915_reg.h            |   7 +
>>>   2 files changed, 230 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>> index b1f0f7e..0008011 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>> @@ -1370,6 +1370,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>>>   
>>>   static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>>>   {
>>> +	if (!crtc_state->gamma_enable)
>>> +		return 0;    >> +
>> 
>> Why are you moving these checks back to the individual functions?
> As stated in commit message, moved common code to check gamma_enable to 
> specific funcs, since icl doesn't support gamma_enable and code will 
> return 0. If i need to make it generic, i need to make gamma_enable true 
> in icl_color_check() func. Is it fine? ICL enables gamma through 
> gamma_mode unlike other platforms.

Argh. Right. Okay, let's go with what you have in this patch. We can
clean this stuff up later.

Please write the main part of the commit message such that it is
independent of the changelog. The changelog is good, but the actual
changes need to be evident from the message part.

BR,
Jani.

-- 
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Re: [v2][PATCH 2/3] drm/i915/display: Extract icl_read_luts()

[Sharma, Swati2]

On 19-Sep-19 6:01 PM, Jani Nikula wrote:
> On Wed, 18 Sep 2019, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
>> On 18-Sep-19 3:31 PM, Jani Nikula wrote:
>>> On Tue, 17 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
>>>> For icl+, have hw read out to create hw blob of gamma
>>>> lut values. icl+ platforms supports multi segmented gamma
>>>> mode, add hw lut creation for this mode.
>>>>
>>>> This will be used to validate gamma programming using dsb
>>>> (display state buffer) which is a tgl feature.
>>>>
>>>> v2: -readout code for multisegmented gamma has to come
>>>>        up with some intermediate entries that aren't preserved
>>>>        in hardware (Jani N)
>>>>       -linear interpolation (Ville)
>>>>       -moved common code to check gamma_enable to specific funcs,
>>>>        since icl doesn't support that
>>>>
>>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/display/intel_color.c | 243 ++++++++++++++++++++++++++---
>>>>    drivers/gpu/drm/i915/i915_reg.h            |   7 +
>>>>    2 files changed, 230 insertions(+), 20 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>>> index b1f0f7e..0008011 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>>> @@ -1370,6 +1370,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>>>>    
>>>>    static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>>>>    {
>>>> +	if (!crtc_state->gamma_enable)
>>>> +		return 0;    >> +
>>>
>>> Why are you moving these checks back to the individual functions?
>> As stated in commit message, moved common code to check gamma_enable to
>> specific funcs, since icl doesn't support gamma_enable and code will
>> return 0. If i need to make it generic, i need to make gamma_enable true
>> in icl_color_check() func. Is it fine? ICL enables gamma through
>> gamma_mode unlike other platforms.
> 
> Argh. Right. Okay, let's go with what you have in this patch. We can
> clean this stuff up later.
> 
> Please write the main part of the commit message such that it is
> independent of the changelog. The changelog is good, but the actual
> changes need to be evident from the message part.
sure.
> 
> BR,
> Jani.
> 


-- 
~Swati Sharma
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[v2][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs

[Swati Sharma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 0008011..4bf098f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1474,6 +1474,8 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
 static bool err_check(struct drm_color_lut *lut1,
 		      struct drm_color_lut *lut2, u32 err)
 {
+	DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
+
 	return ((abs((long)lut2->red - lut1->red)) <= err) &&
 		((abs((long)lut2->blue - lut1->blue)) <= err) &&
 		((abs((long)lut2->green - lut1->green)) <= err);
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev2)

[Patchwork]

== Series Details ==

Series: adding gamma state checker for icl+ platforms (rev2)
URL   : https://patchwork.freedesktop.org/series/66811/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
58295b9b8527 drm/i915/display: Fix formatting issues
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 46 lines checked
2d4f98e0b6e0 drm/i915/display: Extract icl_read_luts()
-:81: ERROR:TRAILING_WHITESPACE: trailing whitespace
#81: FILE: drivers/gpu/drm/i915/display/intel_color.c:1444:
+^I^Ireturn 16;  $

-:87: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#87: FILE: drivers/gpu/drm/i915/display/intel_color.c:1450:
+
+}

-:279: WARNING:LONG_LINE: line over 100 characters
#279: FILE: drivers/gpu/drm/i915/display/intel_color.c:1893:
+		tmp_blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |

-:291: WARNING:LONG_LINE: line over 100 characters
#291: FILE: drivers/gpu/drm/i915/display/intel_color.c:1905:
+		tmp_blob_data[i + 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |

-:293: WARNING:LONG_LINE: line over 100 characters
#293: FILE: drivers/gpu/drm/i915/display/intel_color.c:1907:
+		tmp_blob_data[i + 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |

-:295: WARNING:LONG_LINE: line over 100 characters
#295: FILE: drivers/gpu/drm/i915/display/intel_color.c:1909:
+		tmp_blob_data[i + 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |

-:303: WARNING:LONG_LINE: line over 100 characters
#303: FILE: drivers/gpu/drm/i915/display/intel_color.c:1917:
+		tmp_blob_data[i + 265].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |

-:305: WARNING:LONG_LINE: line over 100 characters
#305: FILE: drivers/gpu/drm/i915/display/intel_color.c:1919:
+		tmp_blob_data[i + 265].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |

-:306: WARNING:LONG_LINE: line over 100 characters
#306: FILE: drivers/gpu/drm/i915/display/intel_color.c:1920:
+					       REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);

-:307: WARNING:LONG_LINE: line over 100 characters
#307: FILE: drivers/gpu/drm/i915/display/intel_color.c:1921:
+		tmp_blob_data[i + 265].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |

total: 1 errors, 8 warnings, 1 checks, 344 lines checked
4760f8cc0e59 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:16: WARNING:LONG_LINE: line over 100 characters
#16: FILE: drivers/gpu/drm/i915/display/intel_color.c:1477:
+	DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);

total: 0 errors, 2 warnings, 0 checks, 8 lines checked

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✓ Fi.CI.BAT: success for adding gamma state checker for icl+ platforms (rev2)

[Patchwork]

== Series Details ==

Series: adding gamma state checker for icl+ platforms (rev2)
URL   : https://patchwork.freedesktop.org/series/66811/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6909 -> Patchwork_14432
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/

Known issues
------------

  Here are the changes found in Patchwork_14432 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-bxt-dsi:         [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html

  * igt@gem_mmap_gtt@basic-write-no-prefault:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u3/igt@gem_mmap_gtt@basic-write-no-prefault.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-icl-u3/igt@gem_mmap_gtt@basic-write-no-prefault.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [PASS][5] -> [DMESG-WARN][6] ([fdo#105602]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-apl-guc/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-u2:          [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108569])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-icl-u2/igt@i915_selftest@live_hangcheck.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-apl-guc:         [PASS][9] -> [DMESG-WARN][10] ([fdo#103558])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-apl-guc:         [PASS][11] -> [SKIP][12] ([fdo#109271]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@prime_vgem@basic-fence-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-apl-guc/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - {fi-icl-u4}:        [DMESG-WARN][13] ([fdo#105602]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u4/igt@i915_module_load@reload-no-display.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-icl-u4/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-hsw-4770:        [SKIP][15] ([fdo#109271]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][17] ([fdo#108511]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][19] ([fdo#111108]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@vgem_basic@second-client:
    - fi-icl-u3:          [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22] +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u3/igt@vgem_basic@second-client.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/fi-icl-u3/igt@vgem_basic@second-client.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108


Participating hosts (55 -> 47)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6909 -> Patchwork_14432

  CI-20190529: 20190529
  CI_DRM_6909: 8a0c508a270fe1d5c5586063096bc14d760b5260 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5189: c78b9959fa4050725b16d55a5e56315884a2753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14432: 4760f8cc0e59f56703641ecc41e52375596fcdaf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4760f8cc0e59 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
2d4f98e0b6e0 drm/i915/display: Extract icl_read_luts()
58295b9b8527 drm/i915/display: Fix formatting issues

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/index.html
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✗ Fi.CI.IGT: failure for adding gamma state checker for icl+ platforms (rev2)

[Patchwork]

== Series Details ==

Series: adding gamma state checker for icl+ platforms (rev2)
URL   : https://patchwork.freedesktop.org/series/66811/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6909_full -> Patchwork_14432_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14432_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14432_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14432_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_color@pipe-a-ctm-0-75:
    - shard-iclb:         NOTRUN -> [DMESG-FAIL][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb1/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_color@pipe-b-gamma:
    - shard-iclb:         [PASS][2] -> [DMESG-WARN][3] +5 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@kms_color@pipe-b-gamma.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb1/igt@kms_color@pipe-b-gamma.html

  * igt@kms_color@pipe-c-ctm-negative:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb2/igt@kms_color@pipe-c-ctm-negative.html

  
#### Warnings ####

  * igt@kms_color@pipe-b-ctm-0-25:
    - shard-iclb:         [FAIL][5] ([fdo#110920]) -> [DMESG-FAIL][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb1/igt@kms_color@pipe-b-ctm-0-25.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb1/igt@kms_color@pipe-b-ctm-0-25.html

  * igt@kms_color@pipe-b-degamma:
    - shard-iclb:         [FAIL][7] ([fdo#104782]) -> [DMESG-FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@kms_color@pipe-b-degamma.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb2/igt@kms_color@pipe-b-degamma.html

  
Known issues
------------

  Here are the changes found in Patchwork_14432_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#111325]) +7 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-bsd2:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#109276]) +5 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb1/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb8/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#103313])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-kbl6/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_softpin@noreloc-s3:
    - shard-snb:          [PASS][15] -> [DMESG-WARN][16] ([fdo#102365])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-snb2/igt@gem_softpin@noreloc-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-snb2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +4 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
    - shard-iclb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#107713])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb7/igt@gem_workarounds@suspend-resume-context.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb7/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_busy@extended-pageflip-hang-oldfb-render-c:
    - shard-apl:          [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) +14 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl2/igt@kms_busy@extended-pageflip-hang-oldfb-render-c.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_busy@extended-pageflip-hang-oldfb-render-c.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen:
    - shard-apl:          [PASS][23] -> [SKIP][24] ([fdo#109271]) +119 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#103184] / [fdo#103232] / [fdo#108222])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [PASS][27] -> [INCOMPLETE][28] ([fdo#103540])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-hsw5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [PASS][29] -> [INCOMPLETE][30] ([fdo#109507])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([fdo#103167] / [fdo#110378])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +8 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#103558])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([fdo#108145])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([fdo#108145] / [fdo#110403]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][41] -> [FAIL][42] ([fdo#103166])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109441])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-skl:          [PASS][45] -> [INCOMPLETE][46] ([fdo#104108])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-skl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  
#### Possible fixes ####

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
    - shard-apl:          [INCOMPLETE][47] ([fdo#103927]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl3/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl8/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-hsw:          [FAIL][49] ([fdo#102887]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-hsw5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-hsw6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][51] ([fdo#103167]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][55] ([fdo#99912]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl2/igt@kms_setmode@basic.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_setmode@basic.html
    - shard-glk:          [FAIL][57] ([fdo#99912]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-glk1/igt@kms_setmode@basic.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-glk3/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-query-forked-busy-hang:
    - shard-iclb:         [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb7/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb3/igt@kms_vblank@pipe-a-query-forked-busy-hang.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62] +3 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@prime_busy@after-bsd2:
    - shard-iclb:         [SKIP][63] ([fdo#109276]) -> [PASS][64] +16 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb6/igt@prime_busy@after-bsd2.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb1/igt@prime_busy@after-bsd2.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [SKIP][65] ([fdo#109276]) -> [FAIL][66] ([fdo#111330])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb1/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [FAIL][67] ([fdo#111330]) -> [SKIP][68] ([fdo#109276])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@kms_atomic_transition@5x-modeset-transitions-nonblocking-fencing:
    - shard-apl:          [SKIP][69] ([fdo#109271] / [fdo#109278]) -> [SKIP][70] ([fdo#109271]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl8/igt@kms_atomic_transition@5x-modeset-transitions-nonblocking-fencing.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_atomic_transition@5x-modeset-transitions-nonblocking-fencing.html

  * igt@kms_busy@extended-modeset-hang-oldfb-render-b:
    - shard-apl:          [INCOMPLETE][71] ([fdo#103927]) -> [SKIP][72] ([fdo#109271] / [fdo#109278])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl8/igt@kms_busy@extended-modeset-hang-oldfb-render-b.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_busy@extended-modeset-hang-oldfb-render-b.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][73] ([fdo#107724]) -> [SKIP][74] ([fdo#109349])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-apl:          [FAIL][75] ([fdo#108145]) -> [SKIP][76] ([fdo#109271] / [fdo#109278]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][77] ([fdo#108566]) -> [SKIP][78] ([fdo#109271])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
  [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108222]: https://bugs.freedesktop.org/show_bug.cgi?id=108222
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110920]: https://bugs.freedesktop.org/show_bug.cgi?id=110920
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6909 -> Patchwork_14432

  CI-20190529: 20190529
  CI_DRM_6909: 8a0c508a270fe1d5c5586063096bc14d760b5260 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5189: c78b9959fa4050725b16d55a5e56315884a2753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14432: 4760f8cc0e59f56703641ecc41e52375596fcdaf @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14432/
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