* [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
@ 2018-12-15 0:38 Aditya Swarup
2018-12-15 1:35 ` ✓ Fi.CI.BAT: success for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Aditya Swarup @ 2018-12-15 0:38 UTC (permalink / raw)
To: intel-gfx
CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0796526dc10f..db1332cd9dcd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1836,8 +1836,8 @@ enum i915_power_well_id {
#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
_ICL_PORT_TX_LN(ln) + 4 * (dw))
-#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
-#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
+#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 2))
+#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 2))
#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
@@ -1869,8 +1869,8 @@ enum i915_power_well_id {
#define CURSOR_COEFF(x) ((x) << 0)
#define CURSOR_COEFF_MASK (0x3F << 0)
-#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
-#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
+#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 5))
+#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 5))
#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
@ 2018-12-15 1:35 ` Patchwork
2018-12-15 2:47 ` ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-12-15 1:35 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming
URL : https://patchwork.freedesktop.org/series/54092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5320 -> Patchwork_11103
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11103 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11103, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/54092/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11103:
### IGT changes ###
#### Warnings ####
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: SKIP -> PASS +33
Known issues
------------
Here are the changes found in Patchwork_11103 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5320 -> Patchwork_11103
CI_DRM_5320: 2abfab12278273a26679335d0c65980816c42206 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4747: ad821d1dc5d0eea4ac3a0e8e29c56c7f66191108 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11103: 1b05f6152b57fea4451bd79e91375d3cbf1ef968 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1b05f6152b57 drm/i915/cnl: Fix CNL macros for Voltage Swing programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11103/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
2018-12-15 1:35 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-12-15 2:47 ` Patchwork
2018-12-31 9:03 ` [PATCH] " Jani Nikula
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-12-15 2:47 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming
URL : https://patchwork.freedesktop.org/series/54092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5320_full -> Patchwork_11103_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11103_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11103_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11103_full:
### IGT changes ###
#### Warnings ####
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
Known issues
------------
Here are the changes found in Patchwork_11103_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-internal-1us:
- shard-glk: PASS -> FAIL [fdo#107799]
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-iclb: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#106887]
* igt@gem_softpin@noreloc-s3:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +7
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-apl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled:
- shard-iclb: PASS -> WARN [fdo#108336]
* igt@kms_flip@2x-flip-vs-dpms:
- shard-hsw: PASS -> DMESG-WARN [fdo#102614]
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-iclb: NOTRUN -> FAIL [fdo#108948]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-iclb: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@pm_rpm@basic-pci-d3-state:
- shard-iclb: PASS -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@cursor:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@pm-tiling:
- shard-iclb: PASS -> DMESG-WARN [fdo#108654]
* igt@pm_rps@reset:
- shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059]
#### Possible fixes ####
* igt@gem_userptr_blits@readonly-unsync:
- shard-iclb: TIMEOUT -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-glk: FAIL [fdo#103184] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-modeset-vs-hang:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS
* igt@kms_psr@no_drrs:
- shard-iclb: FAIL [fdo#108341] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS
* igt@pm_rpm@gem-evict-pwrite:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +1
#### Warnings ####
* igt@i915_selftest@live_contexts:
- shard-iclb: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]
* igt@i915_suspend@shrink:
- shard-skl: DMESG-WARN [fdo#108784] -> INCOMPLETE [fdo#106886]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: DMESG-FAIL [fdo#108950] -> DMESG-WARN [fdo#105604]
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#106887]: https://bugs.freedesktop.org/show_bug.cgi?id=106887
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5320 -> Patchwork_11103
CI_DRM_5320: 2abfab12278273a26679335d0c65980816c42206 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4747: ad821d1dc5d0eea4ac3a0e8e29c56c7f66191108 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11103: 1b05f6152b57fea4451bd79e91375d3cbf1ef968 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11103/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
2018-12-15 1:35 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-12-15 2:47 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-12-31 9:03 ` Jani Nikula
2019-01-08 7:13 ` Aditya Swarup
2019-01-11 0:25 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2) Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2018-12-31 9:03 UTC (permalink / raw)
To: Aditya Swarup, intel-gfx
On Fri, 14 Dec 2018, Aditya Swarup <aditya.swarup@intel.com> wrote:
> CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
> configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
What a mess.
Please fix this by making CNL and ICL macros behave the same way. It's
silly to have the macro args reversed between them. I think dw first,
port second.
BR,
Jani.
>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0796526dc10f..db1332cd9dcd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1836,8 +1836,8 @@ enum i915_power_well_id {
> #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> _ICL_PORT_TX_LN(ln) + 4 * (dw))
>
> -#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> -#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
> +#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 2))
> +#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 2))
> #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
> #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
> #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
> @@ -1869,8 +1869,8 @@ enum i915_power_well_id {
> #define CURSOR_COEFF(x) ((x) << 0)
> #define CURSOR_COEFF_MASK (0x3F << 0)
>
> -#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> -#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
> +#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 5))
> +#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 5))
> #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
> #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
> #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2018-12-31 9:03 ` [PATCH] " Jani Nikula
@ 2019-01-08 7:13 ` Aditya Swarup
2019-01-08 7:47 ` Jani Nikula
0 siblings, 1 reply; 11+ messages in thread
From: Aditya Swarup @ 2019-01-08 7:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Dec 31, 2018 at 11:03:22AM +0200, Jani Nikula wrote:
> On Fri, 14 Dec 2018, Aditya Swarup <aditya.swarup@intel.com> wrote:
> > CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
> > configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
>
> What a mess.
>
> Please fix this by making CNL and ICL macros behave the same way. It's
> silly to have the macro args reversed between them. I think dw first,
> port second.
>
> BR,
> Jani.
I believe it should be the other way round for the macros to make sense.
Port first, followed by dw and then ln. For example we can see in the following
macro expansion:
#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
4 * (dw))
port is used before dw and we should follow that sequence.
I have another patch ready which makes ICL macros consistent with CNL
macros if you approve the sequence of (port, dw, ln).
Let me know if you agree.
Regards,
Aditya Swarup
>
>
> >
> > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0796526dc10f..db1332cd9dcd 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1836,8 +1836,8 @@ enum i915_power_well_id {
> > #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> > _ICL_PORT_TX_LN(ln) + 4 * (dw))
> >
> > -#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> > -#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
> > +#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 2))
> > +#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 2))
> > #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
> > #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
> > #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
> > @@ -1869,8 +1869,8 @@ enum i915_power_well_id {
> > #define CURSOR_COEFF(x) ((x) << 0)
> > #define CURSOR_COEFF_MASK (0x3F << 0)
> >
> > -#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> > -#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
> > +#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 5))
> > +#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 5))
> > #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
> > #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
> > #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2019-01-08 7:13 ` Aditya Swarup
@ 2019-01-08 7:47 ` Jani Nikula
2019-01-10 23:08 ` [PATCH v2] " Aditya Swarup
0 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2019-01-08 7:47 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
On Mon, 07 Jan 2019, Aditya Swarup <aditya.swarup@intel.com> wrote:
> On Mon, Dec 31, 2018 at 11:03:22AM +0200, Jani Nikula wrote:
>> On Fri, 14 Dec 2018, Aditya Swarup <aditya.swarup@intel.com> wrote:
>> > CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
>> > configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
>>
>> What a mess.
>>
>> Please fix this by making CNL and ICL macros behave the same way. It's
>> silly to have the macro args reversed between them. I think dw first,
>> port second.
>>
>> BR,
>> Jani.
>
> I believe it should be the other way round for the macros to make sense.
> Port first, followed by dw and then ln. For example we can see in the following
> macro expansion:
> #define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
> 4 * (dw))
>
> port is used before dw and we should follow that sequence.
It's not about the usage, it's about semantics. We group primarily by
function, secondarily by port/pipe/transcoder.
BR,
Jani.
>
> I have another patch ready which makes ICL macros consistent with CNL
> macros if you approve the sequence of (port, dw, ln).
>
> Let me know if you agree.
>
> Regards,
> Aditya Swarup
>>
>>
>> >
>> > Cc: Clint Taylor <clinton.a.taylor@intel.com>
>> > Cc: Imre Deak <imre.deak@intel.com>
>> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
>> > 1 file changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 0796526dc10f..db1332cd9dcd 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -1836,8 +1836,8 @@ enum i915_power_well_id {
>> > #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
>> > _ICL_PORT_TX_LN(ln) + 4 * (dw))
>> >
>> > -#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
>> > -#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
>> > +#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 2))
>> > +#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 2))
>> > #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
>> > #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
>> > #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
>> > @@ -1869,8 +1869,8 @@ enum i915_power_well_id {
>> > #define CURSOR_COEFF(x) ((x) << 0)
>> > #define CURSOR_COEFF_MASK (0x3F << 0)
>> >
>> > -#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
>> > -#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
>> > +#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(port, 5))
>> > +#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(port, 5))
>> > #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
>> > #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
>> > #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2019-01-08 7:47 ` Jani Nikula
@ 2019-01-10 23:08 ` Aditya Swarup
2019-01-15 10:03 ` Jani Nikula
0 siblings, 1 reply; 11+ messages in thread
From: Aditya Swarup @ 2019-01-10 23:08 UTC (permalink / raw)
To: jani.nikula; +Cc: intel-gfx
CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
v2: Jani suggested to keep the macros organized semantically i.e., by
function, secondarily by port/pipe/transcoder.->(dw, port)
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
There are still inconsistencies in some macro definitions. The macros
for MG phy registers are (port, ln) e.g.,
MG_TX2_LINK_PARAMS(port, ln) and also CNL_PORT_TX_DW4_LN(port, ln)
whereas for ICL -> _ICL_PORT_PCS_DW_LN(dw, ln, port).
Do you feel that we need to make these definitions consistent and what
should be the sequence -> (dw, ln, port)/(ln, port) or (dw, port, ln)/
(port,ln)?
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d994bfa..fad5a9e8b44d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1814,7 +1814,7 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
-#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
+#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \
@@ -1822,7 +1822,7 @@ enum i915_power_well_id {
_CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_F_GRP_OFFSET) + \
4 * (dw))
-#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
+#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \
@@ -1858,9 +1858,9 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
-#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
-#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
-#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
+#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
+#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
+#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
_CNL_PORT_TX_DW4_LN0_AE)))
#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
@@ -1888,8 +1888,8 @@ enum i915_power_well_id {
#define RTERM_SELECT(x) ((x) << 3)
#define RTERM_SELECT_MASK (0x7 << 3)
-#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
-#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
+#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
` (2 preceding siblings ...)
2018-12-31 9:03 ` [PATCH] " Jani Nikula
@ 2019-01-11 0:25 ` Patchwork
2019-01-11 0:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-11 11:35 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-01-11 0:25 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
URL : https://patchwork.freedesktop.org/series/54092/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8b810fada4b5 drm/i915/cnl: Fix CNL macros for Voltage Swing programming
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:1817:
+#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \
-:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:1825:
+#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \
total: 2 errors, 0 warnings, 0 checks, 38 lines checked
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
` (3 preceding siblings ...)
2019-01-11 0:25 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2) Patchwork
@ 2019-01-11 0:55 ` Patchwork
2019-01-11 11:35 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-01-11 0:55 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
URL : https://patchwork.freedesktop.org/series/54092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5400 -> Patchwork_11277
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/54092/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_11277 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (47 -> 41)
------------------------------
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y
Build changes
-------------
* Linux: CI_DRM_5400 -> Patchwork_11277
CI_DRM_5400: 4982584021f0b046841f196efc25735bd71ebdcf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4759: 478452fece3997dfacaa4d6babe6b8bf6fef784f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11277: 8b810fada4b5414a7d0aff0b90ada0bb178ccaee @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8b810fada4b5 drm/i915/cnl: Fix CNL macros for Voltage Swing programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11277/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
` (4 preceding siblings ...)
2019-01-11 0:55 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-01-11 11:35 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-01-11 11:35 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
URL : https://patchwork.freedesktop.org/series/54092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5400_full -> Patchwork_11277_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11277_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11277_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11277_full:
### IGT changes ###
#### Warnings ####
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-snb: PASS -> {SKIP} +1
* igt@pm_rc6_residency@rc6-accuracy:
- shard-kbl: PASS -> {SKIP}
* igt@tools_test@tools_test:
- shard-glk: {SKIP} -> PASS
Known issues
------------
Here are the changes found in Patchwork_11277_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] +1
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108228] / [fdo#108470]
* igt@kms_atomic_transition@plane-all-transition-fencing:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] / [fdo#109225]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-iclb: NOTRUN -> FAIL [fdo#107725] +1
* igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-glk: PASS -> FAIL [fdo#103232]
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +31
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-iclb: PASS -> FAIL [fdo#105683] / [fdo#108040]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-skl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-iclb: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-iclb: NOTRUN -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> DMESG-FAIL [fdo#108950]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
* igt@pm_rpm@gem-evict-pwrite:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@pm_rps@waitboost:
- shard-apl: PASS -> FAIL [fdo#102250]
#### Possible fixes ####
* igt@gem_workarounds@suspend-resume-fd:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: FAIL [fdo#106641] -> PASS
* igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-skl: FAIL [fdo#103191] / [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-iclb: FAIL [fdo#103355] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-skl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-iclb: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_rmfb@rmfb-ioctl:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +3
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS
#### Warnings ####
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> DMESG-FAIL [fdo#103166] / [fdo#103558] / [fdo#105602]
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5400 -> Patchwork_11277
CI_DRM_5400: 4982584021f0b046841f196efc25735bd71ebdcf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4759: 478452fece3997dfacaa4d6babe6b8bf6fef784f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11277: 8b810fada4b5414a7d0aff0b90ada0bb178ccaee @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11277/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915/cnl: Fix CNL macros for Voltage Swing programming
2019-01-10 23:08 ` [PATCH v2] " Aditya Swarup
@ 2019-01-15 10:03 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2019-01-15 10:03 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
On Thu, 10 Jan 2019, Aditya Swarup <aditya.swarup@intel.com> wrote:
> CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
> configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
>
> v2: Jani suggested to keep the macros organized semantically i.e., by
> function, secondarily by port/pipe/transcoder.->(dw, port)
>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Pushed to dinq with the appropriate Fixes: tag added, thanks for the
patch.
> ---
> There are still inconsistencies in some macro definitions. The macros
> for MG phy registers are (port, ln) e.g.,
> MG_TX2_LINK_PARAMS(port, ln) and also CNL_PORT_TX_DW4_LN(port, ln)
> whereas for ICL -> _ICL_PORT_PCS_DW_LN(dw, ln, port).
>
> Do you feel that we need to make these definitions consistent and what
> should be the sequence -> (dw, ln, port)/(ln, port) or (dw, port, ln)/
> (port,ln)?
Feel free to send the patches. I think (dw, port, ln).
BR,
Jani.
>
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44958d994bfa..fad5a9e8b44d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1814,7 +1814,7 @@ enum i915_power_well_id {
> #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
> #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
> #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
> -#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
> +#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
> _CNL_PORT_TX_AE_GRP_OFFSET, \
> _CNL_PORT_TX_B_GRP_OFFSET, \
> _CNL_PORT_TX_B_GRP_OFFSET, \
> @@ -1822,7 +1822,7 @@ enum i915_power_well_id {
> _CNL_PORT_TX_AE_GRP_OFFSET, \
> _CNL_PORT_TX_F_GRP_OFFSET) + \
> 4 * (dw))
> -#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
> +#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
> _CNL_PORT_TX_AE_LN0_OFFSET, \
> _CNL_PORT_TX_B_LN0_OFFSET, \
> _CNL_PORT_TX_B_LN0_OFFSET, \
> @@ -1858,9 +1858,9 @@ enum i915_power_well_id {
>
> #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
> #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
> -#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
> -#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
> -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
> +#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
> +#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
> +#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
> ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> _CNL_PORT_TX_DW4_LN0_AE)))
> #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
> @@ -1888,8 +1888,8 @@ enum i915_power_well_id {
> #define RTERM_SELECT(x) ((x) << 3)
> #define RTERM_SELECT_MASK (0x7 << 3)
>
> -#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> -#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> +#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
> +#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
> #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-01-15 10:01 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-12-15 0:38 [PATCH] drm/i915/cnl: Fix CNL macros for Voltage Swing programming Aditya Swarup
2018-12-15 1:35 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-12-15 2:47 ` ✓ Fi.CI.IGT: " Patchwork
2018-12-31 9:03 ` [PATCH] " Jani Nikula
2019-01-08 7:13 ` Aditya Swarup
2019-01-08 7:47 ` Jani Nikula
2019-01-10 23:08 ` [PATCH v2] " Aditya Swarup
2019-01-15 10:03 ` Jani Nikula
2019-01-11 0:25 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2) Patchwork
2019-01-11 0:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-11 11:35 ` ✓ Fi.CI.IGT: " Patchwork
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