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From: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ander Conselvan de Oliveira
	<ander.conselvan.de.oliveira@intel.com>,
	Dave Airlie <airlied@linux.ie>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	DRI mailing list <dri-devel@lists.freedesktop.org>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [PATCH] drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()
Date: Tue, 30 Jun 2015 16:47:06 +0300	[thread overview]
Message-ID: <876165wbol.fsf@intel.com> (raw)
In-Reply-To: <1435669838-24747-1-git-send-email-ander.conselvan.de.oliveira@intel.com>

On Tue, 30 Jun 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> Similarly to what is done for SKL, clear the dpll_hw_state of the pipe
> config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values.
> That can happen if a crtc that was previously driving an HDMI connector
> switches to a DP connector. In that case, the wrpll field was left with
> its old value, leading to warnings like the one below:
>
> [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000)
> ------------[ cut here ]------------
> WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]()
> pipe state doesn't match!
>
> This regression was indroduced in
>
> commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Fri May 15 13:34:29 2015 +0300
>
>     drm/i915: Don't overwrite (e)DP PLL selection on SKL
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Tested-by: Jani Nikula <jani.nikula@intel.com>

> ---
>
> Only compile tested, for the wrpll warning.
>
> Thanks,
> Ander
>
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4ebfc3a..fbd9ac3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1147,6 +1147,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  static void
>  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
>  {
> +	memset(&pipe_config->dpll_hw_state, 0,
> +	       sizeof(pipe_config->dpll_hw_state));
> +
>  	switch (link_bw) {
>  	case DP_LINK_BW_1_62:
>  		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> -- 
> 2.1.0
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ander Conselvan de Oliveira  <ander.conselvan.de.oliveira@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
	Dave Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel.vetter@intel.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	DRI mailing list <dri-devel@lists.freedesktop.org>,
	Ander Conselvan de Oliveira 
	<ander.conselvan.de.oliveira@intel.com>
Subject: Re: [PATCH] drm/i915: Clear pipe's pll hw state in  hsw_dp_set_ddi_pll_sel()
Date: Tue, 30 Jun 2015 16:47:06 +0300	[thread overview]
Message-ID: <876165wbol.fsf@intel.com> (raw)
In-Reply-To: <1435669838-24747-1-git-send-email-ander.conselvan.de.oliveira@intel.com>

On Tue, 30 Jun 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> Similarly to what is done for SKL, clear the dpll_hw_state of the pipe
> config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values.
> That can happen if a crtc that was previously driving an HDMI connector
> switches to a DP connector. In that case, the wrpll field was left with
> its old value, leading to warnings like the one below:
>
> [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000)
> ------------[ cut here ]------------
> WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]()
> pipe state doesn't match!
>
> This regression was indroduced in
>
> commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Fri May 15 13:34:29 2015 +0300
>
>     drm/i915: Don't overwrite (e)DP PLL selection on SKL
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Tested-by: Jani Nikula <jani.nikula@intel.com>

> ---
>
> Only compile tested, for the wrpll warning.
>
> Thanks,
> Ander
>
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4ebfc3a..fbd9ac3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1147,6 +1147,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  static void
>  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
>  {
> +	memset(&pipe_config->dpll_hw_state, 0,
> +	       sizeof(pipe_config->dpll_hw_state));
> +
>  	switch (link_bw) {
>  	case DP_LINK_BW_1_62:
>  		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> -- 
> 2.1.0
>

-- 
Jani Nikula, Intel Open Source Technology Center

  reply	other threads:[~2015-06-30 13:47 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-26  1:00 [git pull] drm tree for 4.2 Dave Airlie
2015-06-26  1:00 ` Dave Airlie
2015-06-26  8:05 ` Christian König
2015-06-26 20:37   ` Dave Airlie
2015-06-26 20:37     ` Dave Airlie
2015-06-26 20:41     ` Linus Torvalds
2015-06-26 20:41       ` Linus Torvalds
2015-06-26 21:43 ` Linus Torvalds
2015-06-26 21:43   ` Linus Torvalds
2015-06-29 12:43   ` Ander Conselvan De Oliveira
2015-06-29 12:43     ` Ander Conselvan De Oliveira
2015-06-29 14:50     ` Jani Nikula
2015-06-29 14:50       ` Jani Nikula
2015-06-29 15:35       ` [Intel-gfx] " Daniel Vetter
2015-06-29 15:35         ` Daniel Vetter
2015-06-30 13:00         ` Jani Nikula
2015-06-30 13:00           ` [Intel-gfx] " Jani Nikula
2015-06-30 13:10           ` [PATCH] drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel() Ander Conselvan de Oliveira
2015-06-30 13:10             ` Ander Conselvan de Oliveira
2015-06-30 13:47             ` Jani Nikula [this message]
2015-06-30 13:47               ` Jani Nikula
2015-06-30 14:22               ` [Intel-gfx] " Daniel Vetter
2015-06-30 14:22                 ` Daniel Vetter
2015-06-30 15:41                 ` Jani Nikula
2015-06-30 15:41                   ` Jani Nikula
2015-07-01 14:54                   ` Ander Conselvan De Oliveira
2015-07-01 14:54                     ` Ander Conselvan De Oliveira
2015-07-01 15:02                     ` Daniel Vetter
2015-07-01 15:02                       ` Daniel Vetter
2015-07-02  2:38             ` shuang.he

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