From: Eric Anholt <eric@anholt.net>
To: Peter Clifton <pcjc2@cam.ac.uk>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: intel graphics performance thought
Date: Tue, 26 Oct 2010 09:45:21 -0700 [thread overview]
Message-ID: <8762wohpi6.fsf@pollan.anholt.net> (raw)
In-Reply-To: <1288064133.32016.25.camel@pcjc2lap>
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On Tue, 26 Oct 2010 04:35:33 +0100, Peter Clifton <pcjc2@cam.ac.uk> wrote:
> On Mon, 2010-10-25 at 12:44 -0700, Eric Anholt wrote:
>
> > So, what if the problem is that our URB allocations aren't big enough?
> > I would expect that to look kind of like what I'm seeing. One
> > experiment would be to go double the preferred size of each stage in
> > brw_urb.c one by one -- is one stage's URB allocation a limit? Or, am I
> > on the right track at all (go reduce all the preferred sizes to 1/2 and
> > see if that hurts)?
>
> I think what we really need for better understanding is a per-frame
> profile of when different execution units are busy. It sounds like you
> have something like this in development for Ironlake (unfortunately I'm
> only on GM45 here).
Sadly, it's nothing that awesome. Just like intel_gpu_top, but a
different set of bits.
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prev parent reply other threads:[~2010-10-26 16:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <87r5fe6os9.fsf@pollan.anholt.net>
2010-10-26 3:35 ` intel graphics performance thought Peter Clifton
2010-10-26 16:45 ` Eric Anholt [this message]
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