Re: [PATCH v2 6/6] target/arm: Permit configurations with SME but not SVE

["Alex Bennée" <alex.bennee@linaro.org>]

Peter Maydell <peter.maydell@linaro.org> writes:

> In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled")
> we added code that forces SME to be disabled if SVE is disabled.
> This was something we did in the run-up to a release to avoid an
> assertion failure in smcr_write() if the user disabled SVE on the
> 'max' CPU without disabling SME also.
>
> Now that we have corrected the code so that it doesn't assert
> in an SME-without-SVE setup, we can let users select it.
>
> This effectively reverts f7767ca30179.
>
> Note that this now means that command lines like "-cpu max,sve=off"
> which used to turn off SME and SVE will now give you a CPU with SME
> but not SVE.  This is permitted by our loose "max can always give you
> extra stuff" rules, but may be unexpected to users.  Mention this in
> the CPU property documentation.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  docs/system/arm/cpu-features.rst | 10 ++++++++--
>  target/arm/cpu.c                 | 10 ----------
>  2 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
> index 37d5dfd15b..9d0c5731cc 100644
> --- a/docs/system/arm/cpu-features.rst
> +++ b/docs/system/arm/cpu-features.rst
> @@ -318,12 +318,18 @@ SVE CPU Property Parsing Semantics
>       provided an error will be generated.  To avoid this error, one must
>       enable at least one vector length prior to enabling SVE.
>  
> +  10) Disabling SVE does not automatically disable SME. If you want to
> +      disable both you must use ``sve=off,sme=off``. In particular,
> +      for the ``max`` CPU, ``sve=off`` alone will give you a CPU with
> +      SME only (and which therefore still has the SVE vector registers).
> +      Most users will want to disable both at once.
> +
>  SVE CPU Property Examples
>  -------------------------
>  
> -  1) Disable SVE::
> +  1) Disable SVE and SME::
>  
> -     $ qemu-system-aarch64 -M virt -cpu max,sve=off
> +     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sme=off
>  
>    2) Implicitly enable all vector lengths for the ``max`` CPU type::


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro