From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterlin@andestech.com,
peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, ycliang@andestech.com
Subject: Re: [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip
Date: Fri, 27 Oct 2023 09:13:59 +0200 [thread overview]
Message-ID: <877cn84jwo.ffs@tglx> (raw)
In-Reply-To: <20231023004100.2663486-4-peterlin@andestech.com>
On Mon, Oct 23 2023 at 08:40, Yu Chien Peter Lin wrote:
> +
> + if (strcmp(cp, "riscv,cpu-intc") == 0)
> + chip = &riscv_intc_chip;
> + else if (strcmp(cp, "andestech,cpu-intc") == 0)
> + chip = &andes_intc_chip;
> + else
> + return -ENXIO;
See the other reply.
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterlin@andestech.com,
peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, ycliang@andestech.com
Subject: Re: [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip
Date: Fri, 27 Oct 2023 09:13:59 +0200 [thread overview]
Message-ID: <877cn84jwo.ffs@tglx> (raw)
In-Reply-To: <20231023004100.2663486-4-peterlin@andestech.com>
On Mon, Oct 23 2023 at 08:40, Yu Chien Peter Lin wrote:
> +
> + if (strcmp(cp, "riscv,cpu-intc") == 0)
> + chip = &riscv_intc_chip;
> + else if (strcmp(cp, "andestech,cpu-intc") == 0)
> + chip = &andes_intc_chip;
> + else
> + return -ENXIO;
See the other reply.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterlin@andestech.com,
peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, ycliang@andestech.com
Subject: Re: [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip
Date: Fri, 27 Oct 2023 09:13:59 +0200 [thread overview]
Message-ID: <877cn84jwo.ffs@tglx> (raw)
In-Reply-To: <20231023004100.2663486-4-peterlin@andestech.com>
On Mon, Oct 23 2023 at 08:40, Yu Chien Peter Lin wrote:
> +
> + if (strcmp(cp, "riscv,cpu-intc") == 0)
> + chip = &riscv_intc_chip;
> + else if (strcmp(cp, "andestech,cpu-intc") == 0)
> + chip = &andes_intc_chip;
> + else
> + return -ENXIO;
See the other reply.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-10-27 7:14 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 0:40 [PATCH v3 RESEND 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 9:23 ` Conor Dooley
2023-10-23 9:23 ` Conor Dooley
2023-10-23 9:23 ` Conor Dooley
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-27 7:12 ` Thomas Gleixner
2023-10-27 7:12 ` Thomas Gleixner
2023-10-27 7:12 ` Thomas Gleixner
2023-10-30 7:12 ` Yu-Chien Peter Lin
2023-10-30 7:12 ` Yu-Chien Peter Lin
2023-10-30 7:12 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-27 7:13 ` Thomas Gleixner [this message]
2023-10-27 7:13 ` Thomas Gleixner
2023-10-27 7:13 ` Thomas Gleixner
2023-10-23 0:40 ` [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 13:15 ` Conor Dooley
2023-10-23 13:15 ` Conor Dooley
2023-10-23 13:15 ` Conor Dooley
2023-10-26 8:50 ` Yu-Chien Peter Lin
2023-10-26 8:50 ` Yu-Chien Peter Lin
2023-10-26 8:50 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 06/13] perf: RISC-V: Eliminate redundant IRQ enable/disable operations Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 11:56 ` Conor Dooley
2023-10-23 11:56 ` Conor Dooley
2023-10-23 11:56 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 12:25 ` Conor Dooley
2023-10-23 12:25 ` Conor Dooley
2023-10-23 12:25 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 12:03 ` Conor Dooley
2023-10-23 12:03 ` Conor Dooley
2023-10-23 12:03 ` Conor Dooley
2023-10-26 8:22 ` Yu-Chien Peter Lin
2023-10-26 8:22 ` Yu-Chien Peter Lin
2023-10-26 8:22 ` Yu-Chien Peter Lin
2023-10-26 14:09 ` Conor Dooley
2023-10-26 14:09 ` Conor Dooley
2023-10-26 14:09 ` Conor Dooley
2023-10-27 7:22 ` Yu-Chien Peter Lin
2023-10-27 7:22 ` Yu-Chien Peter Lin
2023-10-27 7:22 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:40 ` Yu Chien Peter Lin
2023-10-23 0:41 ` [PATCH v3 RESEND 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-10-23 0:41 ` Yu Chien Peter Lin
2023-10-23 0:41 ` Yu Chien Peter Lin
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