* [PATCH v2 1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
@ 2019-08-05 23:17 Daniele Ceraolo Spurio
2019-08-05 23:17 ` [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-05 23:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Like Gen11, Gen12 has 11 available bits for the ctx id field. However,
the last value (0x7FF) is reserved to indicate engine idle, so we
need to reduce the maximum number of contexts by 1 compared to Gen11.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 64f7a533e886..5c474f38bac6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -172,7 +172,9 @@ static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
lockdep_assert_held(&i915->contexts.mutex);
- if (INTEL_GEN(i915) >= 11)
+ if (INTEL_GEN(i915) >= 12)
+ max = GEN12_MAX_CONTEXT_HW_ID;
+ else if (INTEL_GEN(i915) >= 11)
max = GEN11_MAX_CONTEXT_HW_ID;
else if (USES_GUC_SUBMISSION(i915))
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8931dd847bb5..be5995c60f73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1581,6 +1581,8 @@ struct drm_i915_private {
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+/* in Gen12 ID 0x7FF is reserved to indicate idle */
+#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
struct list_head hw_id_list;
} contexts;
--
2.22.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support 2019-08-05 23:17 [PATCH v2 1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio @ 2019-08-05 23:17 ` Daniele Ceraolo Spurio 2019-08-06 14:06 ` Mika Kuoppala 2019-08-05 23:46 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Patchwork 2019-08-06 10:04 ` ✓ Fi.CI.IGT: " Patchwork 2 siblings, 1 reply; 6+ messages in thread From: Daniele Ceraolo Spurio @ 2019-08-05 23:17 UTC (permalink / raw) To: intel-gfx The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the csb. One of the context IDs (0x7FF) has also been reserved to indicate the invalid ctx, i.e. engine idle. Note that the full context ID includes the SW counter as well, but since we currently only care if the context is valid or not we can ignore that part. v2: fix mask size, fix and expand comments (Tvrtko), use if-ladder (Chris) Bspec: 45555, 46144 Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 79 ++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 48b7114094f1..6cd756b15098 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -163,6 +163,13 @@ #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) +#define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */ +#define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */ +#define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15) +#define GEN12_IDLE_CTX_ID 0x7FF +#define GEN12_CSB_CTX_VALID(csb_dw) \ + (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID) + /* Typical size of the average request (2 pipecontrols and a MI_BB) */ #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ #define WA_TAIL_DWORDS 2 @@ -1326,6 +1333,69 @@ enum csb_step { CSB_COMPLETE, }; +/* + * Starting with Gen12, the status has a new format: + * + * bit 0: switched to new queue + * bit 1: reserved + * bit 2: semaphore wait mode (poll or signal), only valid when + * switch detail is set to "wait on semaphore" + * bits 3-5: engine class + * bits 6-11: engine instance + * bits 12-14: reserved + * bits 15-25: sw context id of the lrc the GT switched to + * bits 26-31: sw counter of the lrc the GT switched to + * bits 32-35: context switch detail + * - 0: ctx complete + * - 1: wait on sync flip + * - 2: wait on vblank + * - 3: wait on scanline + * - 4: wait on semaphore + * - 5: context preempted (not on SEMAPHORE_WAIT or + * WAIT_FOR_EVENT) + * bit 36: reserved + * bits 37-43: wait detail (for switch detail 1 to 4) + * bits 44-46: reserved + * bits 47-57: sw context id of the lrc the GT switched away from + * bits 58-63: sw counter of the lrc the GT switched away from + */ +static inline enum csb_step +gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) +{ + u32 lower_dw = csb[0]; + u32 upper_dw = csb[1]; + bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw); + bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw); + bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE; + + if (!ctx_away_valid && ctx_to_valid) + return CSB_PROMOTE; + + /* + * The context switch detail is not guaranteed to be 5 when a preemption + * occurs, so we can't just check for that. The check below works for + * all the cases we care about, including preemptions of WAIT + * instructions and lite-restore. Preempt-to-idle via the CTRL register + * would require some extra handling, but we don't support that. + */ + if (new_queue && ctx_away_valid) + return CSB_PREEMPT; + + /* + * switch detail = 5 is covered by the case above and we do not expect a + * context switch on an unsuccessful wait instruction since we always + * use polling mode. + */ + GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw)); + + if (*execlists->active) { + GEM_BUG_ON(!ctx_away_valid); + return CSB_COMPLETE; + } + + return CSB_NOP; +} + static inline enum csb_step csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) { @@ -1380,6 +1450,8 @@ static void process_csb(struct intel_engine_cs *engine) rmb(); do { + enum csb_step csb_step; + if (++head == num_entries) head = 0; @@ -1405,7 +1477,12 @@ static void process_csb(struct intel_engine_cs *engine) engine->name, head, buf[2 * head + 0], buf[2 * head + 1]); - switch (csb_parse(execlists, buf + 2 * head)) { + if (INTEL_GEN(engine->i915) >= 12) + csb_step = gen12_csb_parse(execlists, buf + 2 * head); + else + csb_step = csb_parse(execlists, buf + 2 * head); + + switch (csb_step) { case CSB_PREEMPT: /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", execlists->active); -- 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support 2019-08-05 23:17 ` [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio @ 2019-08-06 14:06 ` Mika Kuoppala 2019-08-06 14:17 ` Chris Wilson 0 siblings, 1 reply; 6+ messages in thread From: Mika Kuoppala @ 2019-08-06 14:06 UTC (permalink / raw) To: Daniele Ceraolo Spurio, intel-gfx Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> writes: > The CSB format has been reworked for Gen12 to include information on > both the context we're switching away from and the context we're > switching to. After the change, some of the events don't have their > own bit anymore and need to be inferred from other values in the csb. > One of the context IDs (0x7FF) has also been reserved to indicate > the invalid ctx, i.e. engine idle. > > Note that the full context ID includes the SW counter as well, but since > we currently only care if the context is valid or not we can ignore that > part. > > v2: fix mask size, fix and expand comments (Tvrtko), > use if-ladder (Chris) > > Bspec: 45555, 46144 > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 79 ++++++++++++++++++++++++++++- > 1 file changed, 78 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 48b7114094f1..6cd756b15098 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -163,6 +163,13 @@ > > #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) > > +#define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */ > +#define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */ > +#define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15) > +#define GEN12_IDLE_CTX_ID 0x7FF Without looking at bspec first I thought FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, ~0) would emphasize the mask size. But as bspec uses 0x7FF it is well suited in here too. > +#define GEN12_CSB_CTX_VALID(csb_dw) \ > + (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID) > + > /* Typical size of the average request (2 pipecontrols and a MI_BB) */ > #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ > #define WA_TAIL_DWORDS 2 > @@ -1326,6 +1333,69 @@ enum csb_step { > CSB_COMPLETE, > }; > > +/* > + * Starting with Gen12, the status has a new format: > + * > + * bit 0: switched to new queue > + * bit 1: reserved > + * bit 2: semaphore wait mode (poll or signal), only valid when > + * switch detail is set to "wait on semaphore" > + * bits 3-5: engine class > + * bits 6-11: engine instance > + * bits 12-14: reserved > + * bits 15-25: sw context id of the lrc the GT switched to > + * bits 26-31: sw counter of the lrc the GT switched to > + * bits 32-35: context switch detail > + * - 0: ctx complete > + * - 1: wait on sync flip > + * - 2: wait on vblank > + * - 3: wait on scanline > + * - 4: wait on semaphore > + * - 5: context preempted (not on SEMAPHORE_WAIT or > + * WAIT_FOR_EVENT) > + * bit 36: reserved > + * bits 37-43: wait detail (for switch detail 1 to 4) > + * bits 44-46: reserved > + * bits 47-57: sw context id of the lrc the GT switched away from > + * bits 58-63: sw counter of the lrc the GT switched away from > + */ > +static inline enum csb_step > +gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) > +{ > + u32 lower_dw = csb[0]; > + u32 upper_dw = csb[1]; > + bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw); > + bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw); > + bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE; > + For a longer more complex function, the above could be consts to relieve the readers burden. In here, terse is as good. > + if (!ctx_away_valid && ctx_to_valid) > + return CSB_PROMOTE; > + > + /* > + * The context switch detail is not guaranteed to be 5 when a preemption > + * occurs, so we can't just check for that. The check below works for > + * all the cases we care about, including preemptions of WAIT > + * instructions and lite-restore. Preempt-to-idle via the CTRL register > + * would require some extra handling, but we don't support that. > + */ > + if (new_queue && ctx_away_valid) > + return CSB_PREEMPT; > + > + /* > + * switch detail = 5 is covered by the case above and we do not expect a > + * context switch on an unsuccessful wait instruction since we always > + * use polling mode. > + */ > + GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw)); > + > + if (*execlists->active) { > + GEM_BUG_ON(!ctx_away_valid); > + return CSB_COMPLETE; > + } > + > + return CSB_NOP; I don't have a tgl to play with to try it out, but the comments are golden. > +} > + > static inline enum csb_step > csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) > { > @@ -1380,6 +1450,8 @@ static void process_csb(struct intel_engine_cs *engine) > rmb(); > > do { > + enum csb_step csb_step; > + > if (++head == num_entries) > head = 0; > > @@ -1405,7 +1477,12 @@ static void process_csb(struct intel_engine_cs *engine) > engine->name, head, > buf[2 * head + 0], buf[2 * head + 1]); > > - switch (csb_parse(execlists, buf + 2 * head)) { > + if (INTEL_GEN(engine->i915) >= 12) > + csb_step = gen12_csb_parse(execlists, buf + 2 * head); > + else > + csb_step = csb_parse(execlists, buf + 2 * head); This could have been s/csb_parse/gen8_csb_parse to emphasize the gen range but I am not insisting. I remember doing a patch where we read full 64bit at a time, as we use upper part in tracing as well on gen < 12. Could be that Chris didn't like it. But now with doing a csb parsing function pointer for each gen range, it could fly. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > + > + switch (csb_step) { > case CSB_PREEMPT: /* cancel old inflight, prepare for switch */ > trace_ports(execlists, "preempted", execlists->active); > > -- > 2.22.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support 2019-08-06 14:06 ` Mika Kuoppala @ 2019-08-06 14:17 ` Chris Wilson 0 siblings, 0 replies; 6+ messages in thread From: Chris Wilson @ 2019-08-06 14:17 UTC (permalink / raw) To: Daniele Ceraolo Spurio, Mika Kuoppala, intel-gfx Quoting Mika Kuoppala (2019-08-06 15:06:09) > I remember doing a patch where we read full 64bit at a time, > as we use upper part in tracing as well on gen < 12. > Could be that Chris didn't like it. But now with doing a csb > parsing function pointer for each gen range, it could fly. Tracing doesn't exist in production, but if you can show me gcc prefers one way or another, I'm easily convinced. * reminder to self, get retpolines and see what happens -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID 2019-08-05 23:17 [PATCH v2 1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio 2019-08-05 23:17 ` [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio @ 2019-08-05 23:46 ` Patchwork 2019-08-06 10:04 ` ✓ Fi.CI.IGT: " Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2019-08-05 23:46 UTC (permalink / raw) To: Daniele Ceraolo Spurio; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID URL : https://patchwork.freedesktop.org/series/64738/ State : success == Summary == CI Bug Log - changes from CI_DRM_6633 -> Patchwork_13878 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/ Known issues ------------ Here are the changes found in Patchwork_13878 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html * igt@i915_module_load@reload-no-display: - fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-dsi/igt@i915_module_load@reload-no-display.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-dsi/igt@i915_module_load@reload-no-display.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][5] -> [WARN][6] ([fdo#109380]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][7] -> [WARN][8] ([fdo#109483] / [fdo#111156]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][11] -> [SKIP][12] ([fdo#109271]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html #### Possible fixes #### * igt@gem_flink_basic@flink-lifetime: - fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][15] ([fdo#111108]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_hangcheck: - {fi-icl-guc}: [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-guc/igt@i915_selftest@live_hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-guc/igt@i915_selftest@live_hangcheck.html * igt@kms_busy@basic-flip-c: - fi-kbl-7500u: [SKIP][19] ([fdo#109271] / [fdo#109278]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][21] ([fdo#102505] / [fdo#110390]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - {fi-icl-u4}: [FAIL][23] ([fdo#111045] / [fdo#111046 ]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][25] ([fdo#109483]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html - fi-kbl-7500u: [FAIL][27] ([fdo#109485]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html - {fi-icl-u4}: [FAIL][29] ([fdo#111045]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049 [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108 [fdo#111156]: https://bugs.freedesktop.org/show_bug.cgi?id=111156 Participating hosts (52 -> 46) ------------------------------ Additional (1): fi-kbl-r Missing (7): fi-kbl-soraka fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6633 -> Patchwork_13878 CI-20190529: 20190529 CI_DRM_6633: 8009b790d05451f3c92fb5f49d2c0f697e08a2d2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5121: 242cb6f2149cb9699ba9b316e5f60b756260e829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13878: 58ba66faedb7e8aceac89af73e832f49d56d52f2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 58ba66faedb7 drm/i915/tgl: Gen12 csb support 31422fa3cacd drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID 2019-08-05 23:17 [PATCH v2 1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio 2019-08-05 23:17 ` [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio 2019-08-05 23:46 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Patchwork @ 2019-08-06 10:04 ` Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2019-08-06 10:04 UTC (permalink / raw) To: Daniele Ceraolo Spurio; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID URL : https://patchwork.freedesktop.org/series/64738/ State : success == Summary == CI Bug Log - changes from CI_DRM_6633_full -> Patchwork_13878_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_13878_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-apl4/igt@gem_workarounds@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-apl7/igt@gem_workarounds@suspend-resume-context.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][3] -> [FAIL][4] ([fdo#104873]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167] / [fdo#110378]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#110036 ]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb2/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb3/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html #### Possible fixes #### * igt@gem_eio@reset-stress: - shard-skl: [FAIL][19] ([fdo#109661]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-skl8/igt@gem_eio@reset-stress.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-skl5/igt@gem_eio@reset-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][21] ([fdo#110854]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb7/igt@gem_exec_balancer@smoke.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb2/igt@gem_exec_balancer@smoke.html * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: [INCOMPLETE][23] ([fdo#107713] / [fdo#108840]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb7/igt@i915_pm_rpm@cursor-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb1/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@i2c: - shard-hsw: [FAIL][25] ([fdo#104097]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-hsw7/igt@i915_pm_rpm@i2c.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-hsw7/igt@i915_pm_rpm@i2c.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [FAIL][27] ([fdo#105363]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [FAIL][29] ([fdo#103167]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-skl: [INCOMPLETE][31] ([fdo#104108] / [fdo#106978]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-kbl: [INCOMPLETE][33] ([fdo#103665]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +7 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb6/igt@kms_psr@psr2_no_drrs.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb2/igt@kms_psr@psr2_no_drrs.html * igt@kms_setmode@basic: - shard-skl: [FAIL][39] ([fdo#99912]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-skl2/igt@kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-skl10/igt@kms_setmode@basic.html * igt@perf_pmu@busy-no-semaphores-bcs0: - shard-skl: [DMESG-WARN][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-skl7/igt@perf_pmu@busy-no-semaphores-bcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-skl8/igt@perf_pmu@busy-no-semaphores-bcs0.html #### Warnings #### * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [DMESG-WARN][43] ([fdo#107724]) -> [SKIP][44] ([fdo#109349]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6633/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661 [fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036 [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6633 -> Patchwork_13878 CI-20190529: 20190529 CI_DRM_6633: 8009b790d05451f3c92fb5f49d2c0f697e08a2d2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5121: 242cb6f2149cb9699ba9b316e5f60b756260e829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13878: 58ba66faedb7e8aceac89af73e832f49d56d52f2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13878/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-08-06 14:17 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-08-05 23:17 [PATCH v2 1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Daniele Ceraolo Spurio 2019-08-05 23:17 ` [PATCH v2 2/2] drm/i915/tgl: Gen12 csb support Daniele Ceraolo Spurio 2019-08-06 14:06 ` Mika Kuoppala 2019-08-06 14:17 ` Chris Wilson 2019-08-05 23:46 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Patchwork 2019-08-06 10:04 ` ✓ Fi.CI.IGT: " Patchwork
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