[PATCH] drm/i915/icl: restore WaEnableFloatBlendOptimization

[PATCH] drm/i915/icl: restore WaEnableFloatBlendOptimization

[Talha, Nassar, talha.nassar]

From: talha nassar <talha.nassar@intel.com>

Enables blend optimization for floating point RTs

This restores the workaround that was reverted in c358514ba8da
("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").

The revert was due to the register write seemingly not sticking,
but the HW team has confirmed that this is because the
register is WO and that the workaround is indeed required.

References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: talha nassar <talha.nassar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0796526..5c43720 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2795,6 +2795,9 @@ enum i915_power_well_id {
 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
 
+#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
+
 /* Fuse readout registers for GT */
 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
 #define   HSW_F1_EU_DIS_SHIFT		16
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7a86180..bc614f0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -532,6 +532,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
 	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
+	/* WaEnableFloatBlendOptimization:icl */
+	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
+			  FLOAT_BLEND_OPTIMIZATION_ENABLE);
 }
 
 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: restore WaEnableFloatBlendOptimization

[Patchwork]

== Series Details ==

Series: drm/i915/icl: restore WaEnableFloatBlendOptimization
URL   : https://patchwork.freedesktop.org/series/54091/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7da6a989f1e7 drm/i915/icl: restore WaEnableFloatBlendOptimization
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit c358514ba8da ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"")'
#8: 
This restores the workaround that was reverted in c358514ba8da

total: 1 errors, 0 warnings, 0 checks, 19 lines checked

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✗ Fi.CI.BAT: failure for drm/i915/icl: restore WaEnableFloatBlendOptimization

[Patchwork]

== Series Details ==

Series: drm/i915/icl: restore WaEnableFloatBlendOptimization
URL   : https://patchwork.freedesktop.org/series/54091/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5320 -> Patchwork_11102
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_11102 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11102, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54091/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11102:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_workarounds@basic-read:
    - fi-icl-u3:          PASS -> FAIL
    - fi-icl-u2:          PASS -> FAIL

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-gdg-551:         PASS -> INCOMPLETE

  
#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       SKIP -> PASS +33

  
Known issues
------------

  Here are the changes found in Patchwork_11102 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * {igt@runner@aborted}:
    - fi-gdg-551:         NOTRUN -> FAIL [fdo#108926]

  
#### Possible fixes ####

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        DMESG-FAIL [fdo#108735] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108926]: https://bugs.freedesktop.org/show_bug.cgi?id=108926


Participating hosts (54 -> 47)
------------------------------

  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5320 -> Patchwork_11102

  CI_DRM_5320: 2abfab12278273a26679335d0c65980816c42206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4747: ad821d1dc5d0eea4ac3a0e8e29c56c7f66191108 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11102: 7da6a989f1e7d440d802da9c2d060413920678f4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7da6a989f1e7 drm/i915/icl: restore WaEnableFloatBlendOptimization

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11102/
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Re: [PATCH] drm/i915/icl: restore WaEnableFloatBlendOptimization

[Chris Wilson]

Quoting TalhaNassartalha.nassar@intel.com (2018-12-15 00:29:19)
> From: talha nassar <talha.nassar@intel.com>
> 
> Enables blend optimization for floating point RTs
> 
> This restores the workaround that was reverted in c358514ba8da
> ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
> 
> The revert was due to the register write seemingly not sticking,
> but the HW team has confirmed that this is because the
> register is WO and that the workaround is indeed required.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: talha nassar <talha.nassar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0796526..5c43720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2795,6 +2795,9 @@ enum i915_power_well_id {
>  #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
>  #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
>  
> +#define GEN10_CACHE_MODE_SS                    _MMIO(0xe420)
> +#define   FLOAT_BLEND_OPTIMIZATION_ENABLE      (1 << 4)
> +
>  /* Fuse readout registers for GT */
>  #define HSW_PAVP_FUSE1                 _MMIO(0x911C)
>  #define   HSW_F1_EU_DIS_SHIFT          16
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 7a86180..bc614f0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -532,6 +532,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
>                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> +
> +       /* WaEnableFloatBlendOptimization:icl */
> +       WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
> +                         FLOAT_BLEND_OPTIMIZATION_ENABLE);

Hmm, I thought we had coverage of this list in selftests as well as igt,
I was mistaken. To be completed then.

Anyway I was thinking more of

	wa_write_masked_or(wal, 
			   GEN10_CACHE_MODE_SS,
			   0, /* write-only, so skip validation */
			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE))

Though it works for this case, if we need any more complex fixup in
future, we should track it in the wa struct explicitly.
-Chris
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Re: [PATCH] drm/i915/icl: restore WaEnableFloatBlendOptimization

[Mika Kuoppala]

Talha writes:

> From: talha nassar <talha.nassar@intel.com>
>
> Enables blend optimization for floating point RTs
>
> This restores the workaround that was reverted in c358514ba8da
> ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
>
> The revert was due to the register write seemingly not sticking,
> but the HW team has confirmed that this is because the
> register is WO and that the workaround is indeed required.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: talha nassar <talha.nassar@intel.com>

Could you add HSDES# if you have it? eg.

References: HSDES# 12345679000

Thanks,
-Mika

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0796526..5c43720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2795,6 +2795,9 @@ enum i915_power_well_id {
>  #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
>  #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
>  
> +#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
> +#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
> +
>  /* Fuse readout registers for GT */
>  #define HSW_PAVP_FUSE1			_MMIO(0x911C)
>  #define   HSW_F1_EU_DIS_SHIFT		16
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 7a86180..bc614f0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -532,6 +532,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>  	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
>  		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>  				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> +
> +	/* WaEnableFloatBlendOptimization:icl */
> +	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
> +			  FLOAT_BLEND_OPTIMIZATION_ENABLE);
>  }
>  
>  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> -- 
> 2.7.4
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