* [PATCH] drm/i915/fia: FIA registers offset implementation.
@ 2018-10-29 23:23 Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Anusha Srivatsa @ 2018-10-29 23:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..dd74bc01c64e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,15 @@ enum i915_power_well_id {
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+/* FIA Offsets */
+#define FIA1_BASE 0x163000
+#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
+#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
+#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
+#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
+
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
@@ -10988,17 +10995,17 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
@ 2018-10-29 23:34 ` Lucas De Marchi
2018-10-30 0:34 ` ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2) Patchwork
2018-10-30 13:57 ` [PATCH] drm/i915/fia: FIA registers offset implementation Jani Nikula
2 siblings, 0 replies; 13+ messages in thread
From: Lucas De Marchi @ 2018-10-29 23:34 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 29, 2018 at 04:23:15PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..dd74bc01c64e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +/* FIA Offsets */
> +#define FIA1_BASE 0x163000
> +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
> #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>
> @@ -10988,17 +10995,17 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> --
> 2.17.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2)
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi
@ 2018-10-30 0:34 ` Patchwork
2018-10-30 13:57 ` [PATCH] drm/i915/fia: FIA registers offset implementation Jani Nikula
2 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-10-30 0:34 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation. (rev2)
URL : https://patchwork.freedesktop.org/series/51566/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10640 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10640 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10640, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51566/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10640:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_requests:
fi-icl-u: NOTRUN -> INCOMPLETE
== Known issues ==
Here are the changes found in Patchwork_10640 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s3:
fi-icl-u: INCOMPLETE (fdo#107713) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
== Participating hosts (49 -> 44) ==
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5052 -> Patchwork_10640
CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10640: 45d8bcb2c70420a81d0b4bb3d6c20fef33bf9ee2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
45d8bcb2c704 drm/i915/fia: FIA registers offset implementation.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10640/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi
2018-10-30 0:34 ` ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2) Patchwork
@ 2018-10-30 13:57 ` Jani Nikula
2018-10-30 15:15 ` Lucas De Marchi
2 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2018-10-30 13:57 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Lucas De Marchi
On Mon, 29 Oct 2018, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
Why?
If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
I'm looking for.
We generally don't follow this type of definitions for registers. We may
have some, but those are exceptions.
Please don't do this without some pretty good rationale written in the
commit message.
BR,
Jani.
>
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..dd74bc01c64e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +/* FIA Offsets */
> +#define FIA1_BASE 0x163000
> +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
> #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>
> @@ -10988,17 +10995,17 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-30 13:57 ` [PATCH] drm/i915/fia: FIA registers offset implementation Jani Nikula
@ 2018-10-30 15:15 ` Lucas De Marchi
2018-10-31 9:28 ` Jani Nikula
0 siblings, 1 reply; 13+ messages in thread
From: Lucas De Marchi @ 2018-10-30 15:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi
On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Mon, 29 Oct 2018, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> > from the base - which is the FLexi IO Adaptor. Lets follow the
> > offset calculation while accessing these registers.
>
> Why?
>
> If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
> I'm looking for.
>
> We generally don't follow this type of definitions for registers. We may
> have some, but those are exceptions.
Because spec 29550 treats those registers as a base + offset to be more
future proof regarding a change of the base. And yes, I think something
like that needs to be stated in the commit message. Is this enough?
Lucas De Marchi
>
> Please don't do this without some pretty good rationale written in the
> commit message.
>
> BR,
> Jani.
>
> >
> > v2:
> > - Follow spec for numbering - s/0/1(Lucas)
> > - s/FIA_1/FIA1_BASE (Anusha)
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
> > 1 file changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index bcee91bcfba6..dd74bc01c64e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
> >
> > +/* FIA Offsets */
> > +#define FIA1_BASE 0x163000
> > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> > +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
> > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> > +
> > /* ICL PHY DFLEX registers */
> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
> > #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> >
> > @@ -10988,17 +10995,17 @@ enum skl_power_gate {
> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> >
> > -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
> > +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
> > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
> >
> > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
> > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
> >
> > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
> > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
> >
> > #endif /* _I915_REG_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-30 15:15 ` Lucas De Marchi
@ 2018-10-31 9:28 ` Jani Nikula
2018-10-31 16:58 ` Srivatsa, Anusha
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2018-10-31 9:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi
On Tue, 30 Oct 2018, Lucas De Marchi <lucas.de.marchi@gmail.com> wrote:
> On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Mon, 29 Oct 2018, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
>> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
>> > from the base - which is the FLexi IO Adaptor. Lets follow the
>> > offset calculation while accessing these registers.
>>
>> Why?
>>
>> If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
>> I'm looking for.
>>
>> We generally don't follow this type of definitions for registers. We may
>> have some, but those are exceptions.
>
> Because spec 29550 treats those registers as a base + offset to be more
> future proof regarding a change of the base. And yes, I think something
> like that needs to be stated in the commit message. Is this enough?
Fair enough. Please also see comments in-line.
>
> Lucas De Marchi
>
>>
>> Please don't do this without some pretty good rationale written in the
>> commit message.
>>
>> BR,
>> Jani.
>>
>> >
>> > v2:
>> > - Follow spec for numbering - s/0/1(Lucas)
>> > - s/FIA_1/FIA1_BASE (Anusha)
>> >
>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
>> > 1 file changed, 11 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index bcee91bcfba6..dd74bc01c64e 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
>> > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>> > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>> >
>> > +/* FIA Offsets */
>> > +#define FIA1_BASE 0x163000
Ok.
>> > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
>> > +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
>> > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
>> > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
These should not be grouped here, instead please add above each macro
below or just leave out, see below.
>> > +
>> > /* ICL PHY DFLEX registers */
>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + PORT_TX_DFLEXDPMLE1_OFFSET)
IMO either:
#define _PORT_TX_DFLEXDPMLE1 0x008C0
#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + _PORT_TX_DFLEXDPMLE1)
or just:
#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
BR,
Jani.
>> > #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
>> > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>> >
>> > @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>> >
>> > -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
>> > +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + PORT_TX_DFLEXDPSP_OFFSET)
>> > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
>> > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
>> > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>> > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>> > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>> >
>> > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
>> > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPPMS_OFFSET)
>> > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>> >
>> > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
>> > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + PORT_TX_DFLEXDPCSSS_OFFSET)
>> > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>> >
>> > #endif /* _I915_REG_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-31 9:28 ` Jani Nikula
@ 2018-10-31 16:58 ` Srivatsa, Anusha
2018-10-31 17:23 ` Lucas De Marchi
0 siblings, 1 reply; 13+ messages in thread
From: Srivatsa, Anusha @ 2018-10-31 16:58 UTC (permalink / raw)
To: Jani Nikula, Lucas De Marchi
Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas
>-----Original Message-----
>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>Sent: Wednesday, October 31, 2018 2:29 AM
>To: Lucas De Marchi <lucas.de.marchi@gmail.com>
>Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>gfx@lists.freedesktop.org; De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset
>implementation.
>
>On Tue, 30 Oct 2018, Lucas De Marchi <lucas.de.marchi@gmail.com> wrote:
>> On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula <jani.nikula@linux.intel.com>
>wrote:
>>>
>>> On Mon, 29 Oct 2018, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
>>> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
>>> > from the base - which is the FLexi IO Adaptor. Lets follow the
>>> > offset calculation while accessing these registers.
>>>
>>> Why?
>>>
>>> If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
>>> I'm looking for.
>>>
>>> We generally don't follow this type of definitions for registers. We
>>> may have some, but those are exceptions.
>>
>> Because spec 29550 treats those registers as a base + offset to be
>> more future proof regarding a change of the base. And yes, I think
>> something like that needs to be stated in the commit message. Is this enough?
>
>Fair enough. Please also see comments in-line.
>
>>
>> Lucas De Marchi
>>
>>>
>>> Please don't do this without some pretty good rationale written in
>>> the commit message.
>>>
>>> BR,
>>> Jani.
>>>
>>> >
>>> > v2:
>>> > - Follow spec for numbering - s/0/1(Lucas)
>>> > - s/FIA_1/FIA1_BASE (Anusha)
>>> >
>>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> > ---
>>> > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
>>> > 1 file changed, 11 insertions(+), 4 deletions(-)
>>> >
>>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> > b/drivers/gpu/drm/i915/i915_reg.h index bcee91bcfba6..dd74bc01c64e
>>> > 100644
>>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> > @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
>>> > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy),
>_PORT_CL2CM_DW6_BC)
>>> > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>>> >
>>> > +/* FIA Offsets */
>>> > +#define FIA1_BASE 0x163000
>
>Ok.
>
>>> > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
>>> > +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
>>> > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
>>> > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
>
>These should not be grouped here, instead please add above each macro below
>or just leave out, see below.
>
>>> > +
>>> > /* ICL PHY DFLEX registers */
>>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
>>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
>PORT_TX_DFLEXDPMLE1_OFFSET)
>
>IMO either:
>
>#define _PORT_TX_DFLEXDPMLE1 0x008C0
>#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
>_PORT_TX_DFLEXDPMLE1)
>
>or just:
>
>#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
Makes sense. I ll make this change...
Anusha
>
>BR,
>Jani.
>
>>> > #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
>>> > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>>> >
>>> > @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>>> >
>>> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>>> >
>>> > -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
>>> > +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE +
>PORT_TX_DFLEXDPSP_OFFSET)
>>> > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
>>> > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
>>> > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>>> > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>>> > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>>> >
>>> > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
>>> > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
>PORT_TX_DFLEXDPPMS_OFFSET)
>>> > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 <<
>(tc_port))
>>> >
>>> > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
>>> > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE +
>PORT_TX_DFLEXDPCSSS_OFFSET)
>>> > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 <<
>(tc_port))
>>> >
>>> > #endif /* _I915_REG_H_ */
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-31 16:58 ` Srivatsa, Anusha
@ 2018-10-31 17:23 ` Lucas De Marchi
2018-10-31 17:33 ` Srivatsa, Anusha
0 siblings, 1 reply; 13+ messages in thread
From: Lucas De Marchi @ 2018-10-31 17:23 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas
On Wed, Oct 31, 2018 at 04:58:27PM +0000, Srivatsa, Anusha wrote:
> >>> > /* ICL PHY DFLEX registers */
> >>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> >>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> >PORT_TX_DFLEXDPMLE1_OFFSET)
> >
> >IMO either:
> >
> >#define _PORT_TX_DFLEXDPMLE1 0x008C0
> >#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> >_PORT_TX_DFLEXDPMLE1)
> >
> >or just:
> >
> >#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
>
> Makes sense. I ll make this change...
I think the second option makes more sense. The additional underscored name
doesn't improve readability.
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-31 17:23 ` Lucas De Marchi
@ 2018-10-31 17:33 ` Srivatsa, Anusha
0 siblings, 0 replies; 13+ messages in thread
From: Srivatsa, Anusha @ 2018-10-31 17:33 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas
>-----Original Message-----
>From: Lucas De Marchi [mailto:lucas.de.marchi@gmail.com]
>Sent: Wednesday, October 31, 2018 10:23 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>; intel-gfx@lists.freedesktop.org; De
>Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset
>implementation.
>
>On Wed, Oct 31, 2018 at 04:58:27PM +0000, Srivatsa, Anusha wrote:
>> >>> > /* ICL PHY DFLEX registers */
>> >>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
>> >>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
>> >PORT_TX_DFLEXDPMLE1_OFFSET)
>> >
>> >IMO either:
>> >
>> >#define _PORT_TX_DFLEXDPMLE1 0x008C0
>> >#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
>> >_PORT_TX_DFLEXDPMLE1)
>> >
>> >or just:
>> >
>> >#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
>>
>> Makes sense. I ll make this change...
>
>I think the second option makes more sense. The additional underscored name
>doesn't improve readability.
Yes, so no special additional defines for offsets, just -
#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
Anusha
>Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/fia: FIA registers offset implementation.
@ 2018-11-01 18:55 Anusha Srivatsa
2018-11-02 17:44 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: Anusha Srivatsa @ 2018-11-01 18:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
v3:
- Remove register offset defines. (Jani)
- Update comment. (Anusha)
v4: rebase. Remove comment.(Lucas)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c7df179da28..9744cb59acd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,10 @@ enum i915_power_well_id {
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+#define FIA1_BASE 0x163000
+
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
@@ -11091,17 +11093,17 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-11-01 18:55 Anusha Srivatsa
@ 2018-11-02 17:44 ` Rodrigo Vivi
0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-11-02 17:44 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Thu, Nov 01, 2018 at 11:55:57AM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
>
> v3:
> - Remove register offset defines. (Jani)
> - Update comment. (Anusha)
>
> v4: rebase. Remove comment.(Lucas)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
pushed to dinq. thanks for patch and review.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6c7df179da28..9744cb59acd3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,10 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +#define FIA1_BASE 0x163000
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> @@ -11091,17 +11093,17 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/fia: FIA registers offset implementation.
@ 2018-10-26 5:14 Anusha Srivatsa
2018-10-26 16:21 ` Lucas De Marchi
0 siblings, 1 reply; 13+ messages in thread
From: Anusha Srivatsa @ 2018-10-26 5:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573348b3..e2f5c3a95ad4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,15 @@ enum i915_power_well_id {
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+/* FIA Offsets */
+#define FIA_0 0x163000
+#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
+#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
+#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
+#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
+
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA_0 + PORT_TX_DFLEXDPMLE1_OFFSET)
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
@@ -10957,17 +10964,17 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP _MMIO(FIA_0 + PORT_TX_DFLEXDPSP_OFFSET)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS _MMIO(FIA_0 + PORT_TX_DFLEXDPPMS_OFFSET)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS _MMIO(FIA_0 + PORT_TX_DFLEXDPCSSS_OFFSET)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH] drm/i915/fia: FIA registers offset implementation.
2018-10-26 5:14 Anusha Srivatsa
@ 2018-10-26 16:21 ` Lucas De Marchi
0 siblings, 0 replies; 13+ messages in thread
From: Lucas De Marchi @ 2018-10-26 16:21 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Thu, Oct 25, 2018 at 10:14:39PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 69eb573348b3..e2f5c3a95ad4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +/* FIA Offsets */
> +#define FIA_0 0x163000
spec and other registers start at 1, not 0. So for consistency I think you should change
the name here to FIA_1, or even _FIA1 to follow what's done in other registers.
Lucas De Marchi
> +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA_0 + PORT_TX_DFLEXDPMLE1_OFFSET)
> #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>
> @@ -10957,17 +10964,17 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP _MMIO(FIA_0 + PORT_TX_DFLEXDPSP_OFFSET)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA_0 + PORT_TX_DFLEXDPPMS_OFFSET)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA_0 + PORT_TX_DFLEXDPCSSS_OFFSET)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-11-02 17:44 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-29 23:23 [PATCH] drm/i915/fia: FIA registers offset implementation Anusha Srivatsa
2018-10-29 23:34 ` Lucas De Marchi
2018-10-30 0:34 ` ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2) Patchwork
2018-10-30 13:57 ` [PATCH] drm/i915/fia: FIA registers offset implementation Jani Nikula
2018-10-30 15:15 ` Lucas De Marchi
2018-10-31 9:28 ` Jani Nikula
2018-10-31 16:58 ` Srivatsa, Anusha
2018-10-31 17:23 ` Lucas De Marchi
2018-10-31 17:33 ` Srivatsa, Anusha
-- strict thread matches above, loose matches on Subject: below --
2018-11-01 18:55 Anusha Srivatsa
2018-11-02 17:44 ` Rodrigo Vivi
2018-10-26 5:14 Anusha Srivatsa
2018-10-26 16:21 ` Lucas De Marchi
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