* Fixes that failed to cleanly apply to v4.15-rc1
@ 2017-11-28 8:54 Joonas Lahtinen
2017-11-28 9:27 ` Zhenyu Wang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Joonas Lahtinen @ 2017-11-28 8:54 UTC (permalink / raw)
To: intel-gfx, intel-gvt-dev; +Cc: fred gao, Rodrigo Vivi
Hello,
TL;DR Reply with backported patches for v4.15-rc1 latest TODAY
Dear patch authors/Cc:s, the following patches failed to cleanly
backport to v4.15-rc1, if you believe they still are valid patches to
be included in drm-intel-fixes, please backport them and send them as a
REPLY TO THIS EMAIL before the END OF TODAY.
The patches that failed to cherry-pick:
8cf80a2e4b31 ("drm/i915/gvt: Rename reserved ring buffer")
f2880e04f3a5 ("drm/i915/gvt: Move request alloc to dispatch_workload path only")
0cfecb7c4b9b ("Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"")
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: Fixes that failed to cleanly apply to v4.15-rc1 2017-11-28 8:54 Fixes that failed to cleanly apply to v4.15-rc1 Joonas Lahtinen @ 2017-11-28 9:27 ` Zhenyu Wang 2017-12-05 15:02 ` Joonas Lahtinen 2018-01-02 11:53 ` Jani Nikula 2 siblings, 0 replies; 6+ messages in thread From: Zhenyu Wang @ 2017-11-28 9:27 UTC (permalink / raw) To: Joonas Lahtinen; +Cc: fred gao, intel-gfx, Rodrigo Vivi, intel-gvt-dev [-- Attachment #1.1: Type: text/plain, Size: 846 bytes --] On 2017.11.28 10:54:27 +0200, Joonas Lahtinen wrote: > Hello, > > TL;DR Reply with backported patches for v4.15-rc1 latest TODAY > > Dear patch authors/Cc:s, the following patches failed to cleanly > backport to v4.15-rc1, if you believe they still are valid patches to > be included in drm-intel-fixes, please backport them and send them as a > REPLY TO THIS EMAIL before the END OF TODAY. > > The patches that failed to cherry-pick: > 8cf80a2e4b31 ("drm/i915/gvt: Rename reserved ring buffer") ignore this one. > f2880e04f3a5 ("drm/i915/gvt: Move request alloc to dispatch_workload path only") Done in last gvt-fixes pull request, but seems that missed 4.15-rc1, so will send new pull to include this. thanks -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Fixes that failed to cleanly apply to v4.15-rc1 2017-11-28 8:54 Fixes that failed to cleanly apply to v4.15-rc1 Joonas Lahtinen 2017-11-28 9:27 ` Zhenyu Wang @ 2017-12-05 15:02 ` Joonas Lahtinen 2017-12-06 3:24 ` Zhenyu Wang 2018-01-02 11:53 ` Jani Nikula 2 siblings, 1 reply; 6+ messages in thread From: Joonas Lahtinen @ 2017-12-05 15:02 UTC (permalink / raw) To: intel-gfx, intel-gvt-dev, Rodrigo Vivi, Radhakrishna Sripada Dropping GVT folks that are not affected. Keeping Zhenyu and Zhi as a heads-up, there's no need for GVT pull for this rc? On Tue, 2017-11-28 at 10:54 +0200, Joonas Lahtinen wrote: > Hello, > > TL;DR Reply with backported patches for v4.15-rc1 latest TODAY > > Dear patch authors/Cc:s, the following patches failed to cleanly > backport to v4.15-rc1, if you believe they still are valid patches to > be included in drm-intel-fixes, please backport them and send them as a > REPLY TO THIS EMAIL before the END OF TODAY. <SNIP> > 0cfecb7c4b9b ("Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"") This patch still fails to apply and I'm looking at -rc3 already. Rodrigo and Radhakrishna, do we actually want to see the patch backported? Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Fixes that failed to cleanly apply to v4.15-rc1 2017-12-05 15:02 ` Joonas Lahtinen @ 2017-12-06 3:24 ` Zhenyu Wang 0 siblings, 0 replies; 6+ messages in thread From: Zhenyu Wang @ 2017-12-06 3:24 UTC (permalink / raw) To: Joonas Lahtinen; +Cc: intel-gfx, intel-gvt-dev, Rodrigo Vivi [-- Attachment #1.1: Type: text/plain, Size: 412 bytes --] On 2017.12.05 17:02:34 +0200, Joonas Lahtinen wrote: > Dropping GVT folks that are not affected. > > Keeping Zhenyu and Zhi as a heads-up, there's no need for GVT pull for this rc? > I need to backport one from -next once it's pulled and it's done now. I will send a fixes pull today. thanks -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Fixes that failed to cleanly apply to v4.15-rc1 2017-11-28 8:54 Fixes that failed to cleanly apply to v4.15-rc1 Joonas Lahtinen 2017-11-28 9:27 ` Zhenyu Wang 2017-12-05 15:02 ` Joonas Lahtinen @ 2018-01-02 11:53 ` Jani Nikula 2018-01-02 20:18 ` [PATCH] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl Lucas De Marchi 2 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2018-01-02 11:53 UTC (permalink / raw) To: Joonas Lahtinen, intel-gfx, intel-gvt-dev; +Cc: Lucas De Marchi, Rodrigo Vivi On Tue, 28 Nov 2017, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote: > Hello, > > TL;DR Reply with backported patches for v4.15-rc1 latest TODAY > > Dear patch authors/Cc:s, the following patches failed to cleanly > backport to v4.15-rc1, if you believe they still are valid patches to > be included in drm-intel-fixes, please backport them and send them as a > REPLY TO THIS EMAIL before the END OF TODAY. > > The patches that failed to cherry-pick: > 8cf80a2e4b31 ("drm/i915/gvt: Rename reserved ring buffer") > f2880e04f3a5 ("drm/i915/gvt: Move request alloc to dispatch_workload path only") > 0cfecb7c4b9b ("Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"") Update for -rc6 f745e9cc7e40 ("drm/i915/gvt: Add missing breaks in switch statement") 4e889d62b89d ("drm/i915/gvt: Fix pipe A enable as default for vgpu") 53421c2fe99c ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl") BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl 2018-01-02 11:53 ` Jani Nikula @ 2018-01-02 20:18 ` Lucas De Marchi 0 siblings, 0 replies; 6+ messages in thread From: Lucas De Marchi @ 2018-01-02 20:18 UTC (permalink / raw) To: jani.nikula Cc: Arthur J Runyan, Ville Syrjälä, Rodrigo Vivi, stable, Lucas De Marchi Display WA #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." This workaround was designed to minimize the impact only to save the bad case with that link rates. But HW engineers indicated that it should be safe to apply broadly, although they were expecting the DPLL0 link rate to be unchanged on runtime. We need to cover 2 cases: when we are in fact enabling DPLL0 and when we are just changing the frequency with small differences. This is based on previous patch by Rodrigo Vivi with suggestions from Ville Syrjälä. Cc: Arthur J Runyan <arthur.j.runyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171204232210.4958-1-lucas.demarchi@intel.com [ Lucas: Backport to 4.15 adding back variable that has been removed on commits not meant to be backported ] Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_cdclk.c | 35 ++++++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++ 3 files changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3866c49bc390..333f40bc03bb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6977,6 +6977,7 @@ enum { #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) +#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30) #define MASK_WAKEMEM (1<<13) #define SKL_DFSM _MMIO(0x51000) @@ -8522,6 +8523,7 @@ enum skl_power_gate { #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) +#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19) #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index b2a6d62b71c0..60cf4e58389a 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { - int min_cdclk = skl_calc_cdclk(0, vco); u32 val; WARN_ON(vco != 8100000 && vco != 8640000); - /* select the minimum CDCLK before enabling DPLL 0 */ - val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); - I915_WRITE(CDCLK_CTL, val); - POSTING_READ(CDCLK_CTL); - /* * We always enable DPLL0 with the lowest link rate possible, but still * taking into account the VCO required to operate the eDP panel at the @@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, { int cdclk = cdclk_state->cdclk; int vco = cdclk_state->vco; - u32 freq_select, pcu_ack; + u32 freq_select, pcu_ack, cdclk_ctl; int ret; WARN_ON((cdclk == 24000) != (vco == 0)); @@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, return; } - /* set CDCLK_CTL */ + /* Choose frequency for this cdclk */ switch (cdclk) { case 450000: case 432000: @@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv->cdclk.hw.vco != vco) skl_dpll0_disable(dev_priv); + cdclk_ctl = I915_READ(CDCLK_CTL); + + if (dev_priv->cdclk.hw.vco != vco) { + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + } + + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, cdclk_ctl); + POSTING_READ(CDCLK_CTL); + if (dev_priv->cdclk.hw.vco != vco) skl_dpll0_enable(dev_priv, vco); - I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); + I915_WRITE(CDCLK_CTL, cdclk_ctl); + + /* Wa Display #1183: skl,kbl,cfl */ + cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, cdclk_ctl); POSTING_READ(CDCLK_CTL); /* inform PCU of the change */ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8af286c63d3b..e0bc2debdad0 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("Enabling DC5\n"); + /* Wa Display #1183: skl,kbl,cfl */ + if (IS_GEN9_BC(dev_priv)) + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | + SKL_SELECT_ALTERNATE_DC_EXIT); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } @@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) { DRM_DEBUG_KMS("Disabling DC6\n"); + /* Wa Display #1183: skl,kbl,cfl */ + if (IS_GEN9_BC(dev_priv)) + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | + SKL_SELECT_ALTERNATE_DC_EXIT); + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); } -- 2.14.3 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-01-02 20:18 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-11-28 8:54 Fixes that failed to cleanly apply to v4.15-rc1 Joonas Lahtinen 2017-11-28 9:27 ` Zhenyu Wang 2017-12-05 15:02 ` Joonas Lahtinen 2017-12-06 3:24 ` Zhenyu Wang 2018-01-02 11:53 ` Jani Nikula 2018-01-02 20:18 ` [PATCH] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl Lucas De Marchi
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