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From: Nam Cao <namcao@linutronix.de>
To: Xiaofeng Yuan <xiaofengmian@163.com>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Charlie Jenkins <thecharlesjenkins@gmail.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	xiaofengmian@163.com
Subject: Re: [PATCH v6 1/2] riscv: probes: simulate c.jal instruction
Date: Thu, 02 Jul 2026 11:49:34 +0200	[thread overview]
Message-ID: <878q7tu3f5.fsf@yellow.woof> (raw)
In-Reply-To: <20260701081033.49871-2-xiaofengmian@163.com>

Xiaofeng Yuan <xiaofengmian@163.com> writes:

> The c.jal instruction is currently marked REJECTED in kprobes
> instruction decoding, but it should be SIMULATED like other
> compressed jump instructions.
>
> Add simulate_c_jal() which saves the return address to RA and
> sets the program counter to the target offset, reusing
> simulate_c_j for the common jump logic.
>
> Although c.jal is RV32-only, the function compiles unconditionally.
> On RV64, riscv_insn_is_c_jal() always returns 0, so the simulation
> code is never invoked and the small overhead in kernel size is
> acceptable.
>
> Signed-off-by: Xiaofeng Yuan <xiaofengmian@163.com>

Reviewed-by: Nam Cao <namcao@linutronix.de>
Tested-by: Nam Cao <namcao@linutronix.de>

WARNING: multiple messages have this Message-ID (diff)
From: Nam Cao <namcao@linutronix.de>
To: Xiaofeng Yuan <xiaofengmian@163.com>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Charlie Jenkins <thecharlesjenkins@gmail.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	xiaofengmian@163.com
Subject: Re: [PATCH v6 1/2] riscv: probes: simulate c.jal instruction
Date: Thu, 02 Jul 2026 11:49:34 +0200	[thread overview]
Message-ID: <878q7tu3f5.fsf@yellow.woof> (raw)
In-Reply-To: <20260701081033.49871-2-xiaofengmian@163.com>

Xiaofeng Yuan <xiaofengmian@163.com> writes:

> The c.jal instruction is currently marked REJECTED in kprobes
> instruction decoding, but it should be SIMULATED like other
> compressed jump instructions.
>
> Add simulate_c_jal() which saves the return address to RA and
> sets the program counter to the target offset, reusing
> simulate_c_j for the common jump logic.
>
> Although c.jal is RV32-only, the function compiles unconditionally.
> On RV64, riscv_insn_is_c_jal() always returns 0, so the simulation
> code is never invoked and the small overhead in kernel size is
> acceptable.
>
> Signed-off-by: Xiaofeng Yuan <xiaofengmian@163.com>

Reviewed-by: Nam Cao <namcao@linutronix.de>
Tested-by: Nam Cao <namcao@linutronix.de>

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  reply	other threads:[~2026-07-02  9:49 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-01  8:10 [PATCH v6 0/2] riscv: add c.jal instruction simulation for kprobes Xiaofeng Yuan
2026-07-01  8:10 ` Xiaofeng Yuan
2026-07-01  8:10 ` [PATCH v6 1/2] riscv: probes: simulate c.jal instruction Xiaofeng Yuan
2026-07-01  8:10   ` Xiaofeng Yuan
2026-07-02  9:49   ` Nam Cao [this message]
2026-07-02  9:49     ` Nam Cao
2026-07-09  7:19   ` Charlie Jenkins
2026-07-09  7:19     ` Charlie Jenkins
2026-07-10 18:39     ` Paul Walmsley
2026-07-10 18:39       ` Paul Walmsley
2026-07-01  8:10 ` [PATCH v6 2/2] riscv: kprobes: add test case for c.jal instruction simulation Xiaofeng Yuan
2026-07-01  8:10   ` Xiaofeng Yuan
2026-07-09  7:19   ` Charlie Jenkins
2026-07-09  7:19     ` Charlie Jenkins
2026-07-10 18:35 ` [PATCH v6 0/2] riscv: add c.jal instruction simulation for kprobes Paul Walmsley
2026-07-10 18:35   ` Paul Walmsley

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