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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	linux-spi@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-mtd@lists.infradead.org,  Michael Walle <mwalle@kernel.org>,
	Takahiro Kuwano <takahiro.kuwano@infineon.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Steam Lin <STLin2@winbond.com>,  Santhosh Kumar K <s-k6@ti.com>
Subject: Re: [PATCH 0/4] spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62
Date: Tue, 28 Apr 2026 14:44:33 +0200	[thread overview]
Message-ID: <878qa7dzke.fsf@bootlin.com> (raw)
In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> (Miquel Raynal's message of "Thu, 26 Mar 2026 17:47:14 +0100")

On 26/03/2026 at 17:47:14 +01, Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> TI errata i2351 explains there is a problem with CS handling, SPI NOR
> are immune to the problem, but the CS being deasserted spuriously when
> there is DMA arbitration on long accesses (every 1023 bytes), SPI NAND
> continuous reads cannot be leveraged.
>
> Link: https://www.ti.com/lit/er/sprz544c/sprz544c.pdf
>
> I created a 2-page read setup for testing all variants available on a
> W35N chip wired to this controller. I reliably observed all variants to
> always (in my tests) report correct data, except the 8D-8D-8D
> variant *when setting an extended number of dummy cycles* (>= 12, so 24
> dummy bytes). In this case, I got the first 6144 bytes correct (over
> 8192), the rest being full of ones (0xFF), indicating the CS has likely
> been deasserted there. This is not exactly 6 x 1023 bytes (?), but
> close.
>
> This series shall be applied on top of the SPI NAND continuous read
> series that I am also carrying, but ideally not too far in the future
> because there are Winbond (continuous read capable) NAND chips mounted
> on TI platforms AM62 based which could make use of that new feature and
> expose the issue described above.

Applied to nand/next (except the spi patch).


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WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	linux-spi@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-mtd@lists.infradead.org,  Michael Walle <mwalle@kernel.org>,
	Takahiro Kuwano <takahiro.kuwano@infineon.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Steam Lin <STLin2@winbond.com>,  Santhosh Kumar K <s-k6@ti.com>
Subject: Re: [PATCH 0/4] spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62
Date: Tue, 28 Apr 2026 14:44:33 +0200	[thread overview]
Message-ID: <878qa7dzke.fsf@bootlin.com> (raw)
In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> (Miquel Raynal's message of "Thu, 26 Mar 2026 17:47:14 +0100")

On 26/03/2026 at 17:47:14 +01, Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> TI errata i2351 explains there is a problem with CS handling, SPI NOR
> are immune to the problem, but the CS being deasserted spuriously when
> there is DMA arbitration on long accesses (every 1023 bytes), SPI NAND
> continuous reads cannot be leveraged.
>
> Link: https://www.ti.com/lit/er/sprz544c/sprz544c.pdf
>
> I created a 2-page read setup for testing all variants available on a
> W35N chip wired to this controller. I reliably observed all variants to
> always (in my tests) report correct data, except the 8D-8D-8D
> variant *when setting an extended number of dummy cycles* (>= 12, so 24
> dummy bytes). In this case, I got the first 6144 bytes correct (over
> 8192), the rest being full of ones (0xFF), indicating the CS has likely
> been deasserted there. This is not exactly 6 x 1023 bytes (?), but
> close.
>
> This series shall be applied on top of the SPI NAND continuous read
> series that I am also carrying, but ideally not too far in the future
> because there are Winbond (continuous read capable) NAND chips mounted
> on TI platforms AM62 based which could make use of that new feature and
> expose the issue described above.

Applied to nand/next (except the spi patch).


  parent reply	other threads:[~2026-04-28 12:44 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-26 16:47 [PATCH 0/4] spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62 Miquel Raynal
2026-03-26 16:47 ` Miquel Raynal
2026-03-26 16:47 ` [PATCH 1/4] spi: spi-mem: Add a no_cs_assertion capability Miquel Raynal
2026-03-26 16:47   ` Miquel Raynal
2026-04-27 23:46   ` Mark Brown
2026-04-27 23:46     ` Mark Brown
2026-03-26 16:47 ` [PATCH 2/4] mtd: spinand: Make sure continuous read is always disabled during probe Miquel Raynal
2026-03-26 16:47   ` Miquel Raynal
2026-03-26 16:47 ` [PATCH 3/4] mtd: spinand: Prevent continuous reads on some controllers Miquel Raynal
2026-03-26 16:47   ` Miquel Raynal
2026-03-26 16:47 ` [PATCH 4/4] spi: cadence-qspi: Prevent SPI NAND continuous reads Miquel Raynal
2026-03-26 16:47   ` Miquel Raynal
2026-04-27 13:28 ` [PATCH 0/4] spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62 Miquel Raynal
2026-04-27 13:28   ` Miquel Raynal
2026-04-27 23:45   ` Mark Brown
2026-04-27 23:45     ` Mark Brown
2026-04-28 12:44 ` Miquel Raynal [this message]
2026-04-28 12:44   ` Miquel Raynal

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