* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-30 10:08 Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-30 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h | 12 ++++++----
5 files changed, 44 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-01-30 10:08 ` Chaitanya Kumar Borah
2023-11-17 23:35 ` Lucas De Marchi
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-30 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
Separate out RPLU device ids and add them to both RPL and
newly created RPL-U subplatforms.
v2: (Matt)
- Sort PCI-IDs numerically
- Name the sub-platform to accurately depict what it is for
- Make RPL-U part of RPL subplatform
v3: revert to RPL-U subplatform (Jani)
v4: (Jani)
- Add RPL-U ids to RPL-P platform
- Remove redundant comment
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h | 12 ++++++++----
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12..c88e514728a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ADLP_RPLP(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_RPLU(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 849baf6c3b3c..322e1ef94c47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -201,6 +201,10 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
};
+static const u16 subplatform_rplu_ids[] = {
+ INTEL_RPLU_IDS(0),
+};
+
static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
@@ -268,6 +272,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+ if (find_devid(devid, subplatform_rplu_ids,
+ ARRAY_SIZE(subplatform_rplu_ids)))
+ mask |= BIT(INTEL_SUBPLATFORM_RPLU);
} else if (find_devid(devid, subplatform_g10_ids,
ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d588e5fd2eea..3e3ca5eb073f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,7 @@ enum intel_platform {
* bit set
*/
#define INTEL_SUBPLATFORM_N 1
+#define INTEL_SUBPLATFORM_RPLU 2
/* MTL */
#define INTEL_SUBPLATFORM_M 0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4a4c190f7698..5824e1d7d162 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -684,14 +684,18 @@
INTEL_VGA_DEVICE(0xA78A, info), \
INTEL_VGA_DEVICE(0xA78B, info)
+/* RPL-U */
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
+
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
+ INTEL_RPLU_IDS(info), \
INTEL_VGA_DEVICE(0xA720, info), \
- INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
- INTEL_VGA_DEVICE(0xA7A1, info), \
- INTEL_VGA_DEVICE(0xA7A8, info), \
- INTEL_VGA_DEVICE(0xA7A9, info)
+ INTEL_VGA_DEVICE(0xA7A8, info)
/* DG2 */
#define INTEL_DG2_G10_IDS(info) \
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [RFC v4 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
@ 2023-01-30 10:08 ` Chaitanya Kumar Borah
2023-01-30 11:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev6) Patchwork
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-30 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
v3: - Revert to RPL-U subplatform (Jani)
v4: - Remove Bspec reference from code (Jani)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..2e26e6762f35 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3377,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ else if (IS_ADLP_RPLU(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev6)
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-30 11:32 ` Patchwork
2023-01-30 11:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-30 11:32 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev6)
URL : https://patchwork.freedesktop.org/series/111472/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add new CDCLK step for RPL-U (rev6)
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (2 preceding siblings ...)
2023-01-30 11:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev6) Patchwork
@ 2023-01-30 11:44 ` Patchwork
2023-01-30 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-30 11:44 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4279 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev6)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12663 -> Patchwork_111472v6
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/index.html
Participating hosts (24 -> 23)
------------------------------
Additional (1): bat-rpls-2
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_111472v6 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@fbdev@write:
- fi-blb-e6850: [SKIP][1] ([fdo#109271]) -> [PASS][2] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/fi-blb-e6850/igt@fbdev@write.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/fi-blb-e6850/igt@fbdev@write.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: [ABORT][3] ([i915#7359]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-n3050: [FAIL][5] ([i915#6298]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
Build changes
-------------
* Linux: CI_DRM_12663 -> Patchwork_111472v6
CI-20190529: 20190529
CI_DRM_12663: 515fcd5308bda45b7832e0ce12bec6830f64aa08 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7141: a978df7912acda18eada1b1d2ae4b438ed3e940b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v6: 515fcd5308bda45b7832e0ce12bec6830f64aa08 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
75ef0bc64cc3 drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
212d1ae733c2 drm/i915: Add RPL-U sub platform
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/index.html
[-- Attachment #2: Type: text/html, Size: 3534 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add new CDCLK step for RPL-U (rev6)
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (3 preceding siblings ...)
2023-01-30 11:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-30 14:05 ` Patchwork
2023-02-16 10:52 ` [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Jani Nikula
2023-02-28 0:35 ` Matt Roper
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-30 14:05 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 19250 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev6)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12663_full -> Patchwork_111472v6_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/index.html
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_111472v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-glk1/igt@gem_exec_fair@basic-deadline.html
#### Possible fixes ####
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}: [SKIP][3] ([i915#3281]) -> [PASS][4] +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}: [FAIL][5] ([i915#7742]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@fbdev@read:
- {shard-rkl}: [SKIP][7] ([i915#2582]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@fbdev@read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@fbdev@read.html
* igt@feature_discovery@psr2:
- {shard-rkl}: [SKIP][9] ([i915#658]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-2/igt@feature_discovery@psr2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}: [FAIL][11] ([fdo#103375]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_eio@in-flight-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@suspend:
- {shard-rkl}: [FAIL][13] ([i915#7052]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_eio@suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-2/igt@gem_eio@suspend.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}: [FAIL][15] ([i915#2842]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_suspend@basic-s3-devices@smem:
- {shard-rkl}: [FAIL][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@gem_exec_suspend@basic-s3-devices@smem.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-2/igt@gem_exec_suspend@basic-s3-devices@smem.html
* igt@gem_readwrite@write-bad-handle:
- {shard-rkl}: [SKIP][19] ([i915#3282]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@gem_readwrite@write-bad-handle.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@gem_readwrite@write-bad-handle.html
* igt@gen9_exec_parse@bb-secure:
- {shard-rkl}: [SKIP][21] ([i915#2527]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-1/igt@gen9_exec_parse@bb-secure.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-5/igt@gen9_exec_parse@bb-secure.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][23] ([fdo#109308]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@i915_pm_rpm@i2c.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][25] ([i915#1397]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}: [SKIP][27] ([i915#4098]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@kms_atomic@atomic_plane_damage.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][29] ([i915#1845] / [i915#4098]) -> [PASS][30] +20 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_draw_crc@draw-method@xrgb2101010-blt-ytiled:
- shard-glk: [DMESG-WARN][31] -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk5/igt@kms_draw_crc@draw-method@xrgb2101010-blt-ytiled.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-glk9/igt@kms_draw_crc@draw-method@xrgb2101010-blt-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a1:
- {shard-dg1}: [FAIL][33] -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-dg1-14/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-dg1-14/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: [DMESG-FAIL][35] ([i915#118]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-glk9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-rkl}: [SKIP][37] ([i915#1849] / [i915#4098]) -> [PASS][38] +14 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- {shard-rkl}: [SKIP][39] ([i915#1849]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr@sprite_plane_onoff:
- {shard-rkl}: [SKIP][41] ([i915#1072]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-2/igt@kms_psr@sprite_plane_onoff.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- {shard-rkl}: [SKIP][43] ([i915#5461]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-4/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- {shard-rkl}: [SKIP][45] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12663/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
Build changes
-------------
* Linux: CI_DRM_12663 -> Patchwork_111472v6
CI-20190529: 20190529
CI_DRM_12663: 515fcd5308bda45b7832e0ce12bec6830f64aa08 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7141: a978df7912acda18eada1b1d2ae4b438ed3e940b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v6: 515fcd5308bda45b7832e0ce12bec6830f64aa08 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v6/index.html
[-- Attachment #2: Type: text/html, Size: 12603 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (4 preceding siblings ...)
2023-01-30 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-02-16 10:52 ` Jani Nikula
2023-02-28 0:35 ` Matt Roper
6 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2023-02-16 10:52 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Mon, 30 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> A new step of 480MHz has been added on SKUs that have an RPL-U
> device id. This particular step is to support 120Hz panels
> more efficiently.
>
> This patchset adds a new table to include this new CDCLK
> step. Details can be found in BSpec entry 55409.
>
> Create a new sub-platform to identify RPL-U which will enable
> us to make the differentiation during CDCLK initialization.
Thanks, pushed the series to drm-intel-next.
BR,
Jani.
>
> Furthermore, we need to make a distinction between ES (Engineering
> Sample) and QS (Quality Sample) parts as this change comes only
> to QS parts. This version of the patch does not include this change
> as we are yet to make a decision if this particular part needs
> to be upstreamed.(see comments on revision 2)
>
> Chaitanya Kumar Borah (2):
> drm/i915: Add RPL-U sub platform
> drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 12 ++++++----
> 5 files changed, 44 insertions(+), 4 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (5 preceding siblings ...)
2023-02-16 10:52 ` [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Jani Nikula
@ 2023-02-28 0:35 ` Matt Roper
2023-02-28 10:42 ` Borah, Chaitanya Kumar
6 siblings, 1 reply; 11+ messages in thread
From: Matt Roper @ 2023-02-28 0:35 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: ville.syrjala, intel-gfx
On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote:
> A new step of 480MHz has been added on SKUs that have an RPL-U
> device id. This particular step is to support 120Hz panels
> more efficiently.
>
> This patchset adds a new table to include this new CDCLK
> step. Details can be found in BSpec entry 55409.
Hi Chaitanya. It looks like we probably need one more change related to
the 480MHz rate beyond what was in this series. For platforms that
support this rate, we can set voltage level 1 (see bspec 49208) whereas
the i915 code at the moment will push it up to voltage level 2 instead.
Matt
>
> Create a new sub-platform to identify RPL-U which will enable
> us to make the differentiation during CDCLK initialization.
>
> Furthermore, we need to make a distinction between ES (Engineering
> Sample) and QS (Quality Sample) parts as this change comes only
> to QS parts. This version of the patch does not include this change
> as we are yet to make a decision if this particular part needs
> to be upstreamed.(see comments on revision 2)
>
> Chaitanya Kumar Borah (2):
> drm/i915: Add RPL-U sub platform
> drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 12 ++++++----
> 5 files changed, 44 insertions(+), 4 deletions(-)
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-02-28 0:35 ` Matt Roper
@ 2023-02-28 10:42 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 11+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-02-28 10:42 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Syrjala, Ville, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, February 28, 2023 6:06 AM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar,
> Uma <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>
> Subject: Re: [RFC 0/2] Add new CDCLK step for RPL-U
>
> On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote:
> > A new step of 480MHz has been added on SKUs that have an RPL-U device
> > id. This particular step is to support 120Hz panels more efficiently.
> >
> > This patchset adds a new table to include this new CDCLK step. Details
> > can be found in BSpec entry 55409.
>
> Hi Chaitanya. It looks like we probably need one more change related to the
> 480MHz rate beyond what was in this series. For platforms that support this
> rate, we can set voltage level 1 (see bspec 49208) whereas the i915 code at
> the moment will push it up to voltage level 2 instead.
Hello Matt,
Thank you for pointing it out. I will have a look and float a patch ASAP.
Regards
Chaitanya
>
>
> Matt
>
> >
> > Create a new sub-platform to identify RPL-U which will enable us to
> > make the differentiation during CDCLK initialization.
> >
> > Furthermore, we need to make a distinction between ES (Engineering
> > Sample) and QS (Quality Sample) parts as this change comes only to QS
> > parts. This version of the patch does not include this change as we
> > are yet to make a decision if this particular part needs to be
> > upstreamed.(see comments on revision 2)
> >
> > Chaitanya Kumar Borah (2):
> > drm/i915: Add RPL-U sub platform
> > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
> >
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 26
> ++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > include/drm/i915_pciids.h | 12 ++++++----
> > 5 files changed, 44 insertions(+), 4 deletions(-)
> >
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
@ 2023-11-17 23:35 ` Lucas De Marchi
2023-11-20 10:30 ` Jani Nikula
0 siblings, 1 reply; 11+ messages in thread
From: Lucas De Marchi @ 2023-11-17 23:35 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx, ville.syrjala
On Mon, Jan 30, 2023 at 03:38:05PM +0530, Chaitanya Kumar Borah wrote:
>Separate out RPLU device ids and add them to both RPL and
>newly created RPL-U subplatforms.
>
>v2: (Matt)
> - Sort PCI-IDs numerically
> - Name the sub-platform to accurately depict what it is for
> - Make RPL-U part of RPL subplatform
>
>v3: revert to RPL-U subplatform (Jani)
>
>v4: (Jani)
> - Add RPL-U ids to RPL-P platform
humn...
>diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>index 4a4c190f7698..5824e1d7d162 100644
>--- a/include/drm/i915_pciids.h
>+++ b/include/drm/i915_pciids.h
>@@ -684,14 +684,18 @@
> INTEL_VGA_DEVICE(0xA78A, info), \
> INTEL_VGA_DEVICE(0xA78B, info)
>
>+/* RPL-U */
>+#define INTEL_RPLU_IDS(info) \
>+ INTEL_VGA_DEVICE(0xA721, info), \
>+ INTEL_VGA_DEVICE(0xA7A1, info), \
>+ INTEL_VGA_DEVICE(0xA7A9, info)
>+
> /* RPL-P */
> #define INTEL_RPLP_IDS(info) \
>+ INTEL_RPLU_IDS(info), \
drive by comment while reviewing other stuff. Why was U added to the
P macro? That looks odd. Adding it to the rpl subplatform, together with P would
be ok, but in this macro it looks wrong. Doing it the other way I think the
only affected place would be the early-quirks, which would need a separate entry,
but admitedly they should had been INTEL_RPL_IDS() with all the
variants.
Lucas De Marchi
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform
2023-11-17 23:35 ` Lucas De Marchi
@ 2023-11-20 10:30 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2023-11-20 10:30 UTC (permalink / raw)
To: Lucas De Marchi, Chaitanya Kumar Borah; +Cc: intel-gfx, ville.syrjala
On Fri, 17 Nov 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Jan 30, 2023 at 03:38:05PM +0530, Chaitanya Kumar Borah wrote:
>>Separate out RPLU device ids and add them to both RPL and
>>newly created RPL-U subplatforms.
>>
>>v2: (Matt)
>> - Sort PCI-IDs numerically
>> - Name the sub-platform to accurately depict what it is for
>> - Make RPL-U part of RPL subplatform
>>
>>v3: revert to RPL-U subplatform (Jani)
>>
>>v4: (Jani)
>> - Add RPL-U ids to RPL-P platform
>
> humn...
>
>>diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>index 4a4c190f7698..5824e1d7d162 100644
>>--- a/include/drm/i915_pciids.h
>>+++ b/include/drm/i915_pciids.h
>>@@ -684,14 +684,18 @@
>> INTEL_VGA_DEVICE(0xA78A, info), \
>> INTEL_VGA_DEVICE(0xA78B, info)
>>
>>+/* RPL-U */
>>+#define INTEL_RPLU_IDS(info) \
>>+ INTEL_VGA_DEVICE(0xA721, info), \
>>+ INTEL_VGA_DEVICE(0xA7A1, info), \
>>+ INTEL_VGA_DEVICE(0xA7A9, info)
>>+
>> /* RPL-P */
>> #define INTEL_RPLP_IDS(info) \
>>+ INTEL_RPLU_IDS(info), \
>
> drive by comment while reviewing other stuff. Why was U added to the
> P macro? That looks odd. Adding it to the rpl subplatform, together with P would
> be ok, but in this macro it looks wrong. Doing it the other way I think the
> only affected place would be the early-quirks, which would need a separate entry,
> but admitedly they should had been INTEL_RPL_IDS() with all the
> variants.
It's been 10 months, I have no recollection, but this is what I found in
old mails [1].
BR,
Jani.
[1] https://lore.kernel.org/r/87mt686m1o.fsf@intel.com
>
>
> Lucas De Marchi
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-11-20 10:31 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
2023-11-17 23:35 ` Lucas De Marchi
2023-11-20 10:30 ` Jani Nikula
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-30 11:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev6) Patchwork
2023-01-30 11:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-30 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-02-16 10:52 ` [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Jani Nikula
2023-02-28 0:35 ` Matt Roper
2023-02-28 10:42 ` Borah, Chaitanya Kumar
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