* [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
@ 2021-10-27 13:59 Jani Nikula
2021-10-27 16:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jani Nikula @ 2021-10-27 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
debugging, and should not be info level messages.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index fa84be609d5d..bf8d3c7ca2d9 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -598,7 +598,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val |= DSC_422_ENABLE;
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_VBR_ENABLE;
- drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
pps_val);
@@ -622,7 +622,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
/* Populate PICTURE_PARAMETER_SET_1 registers */
pps_val = 0;
pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
- drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
pps_val);
@@ -647,7 +647,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
- drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
pps_val);
@@ -672,7 +672,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
- drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
pps_val);
@@ -697,7 +697,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
- drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
pps_val);
@@ -722,7 +722,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
- drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
pps_val);
@@ -749,7 +749,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
- drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
pps_val);
@@ -774,7 +774,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
- drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
pps_val);
@@ -799,7 +799,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
- drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
pps_val);
@@ -824,7 +824,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val = 0;
pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
- drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
pps_val);
@@ -851,7 +851,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
- drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
pps_val);
@@ -879,7 +879,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
vdsc_cfg->slice_width) |
DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
- drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
+ drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
pps_val);
@@ -906,8 +906,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
rc_buf_thresh_dword[i / 4] |=
(u32)(vdsc_cfg->rc_buf_thresh[i] <<
BITS_PER_BYTE * (i % 4));
- drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
- rc_buf_thresh_dword[i / 4]);
+ drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
+ rc_buf_thresh_dword[i / 4]);
}
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
@@ -963,8 +963,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
RC_MAX_QP_SHIFT) |
(vdsc_cfg->rc_range_params[i].range_min_qp <<
RC_MIN_QP_SHIFT)) << 16 * (i % 2));
- drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
- rc_range_params_dword[i / 2]);
+ drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
+ rc_range_params_dword[i / 2]);
}
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
2021-10-27 13:59 [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg() Jani Nikula
@ 2021-10-27 16:58 ` Patchwork
2021-10-27 19:42 ` [Intel-gfx] [PATCH] " Navare, Manasi
2021-10-27 21:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2021-10-27 16:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2808 bytes --]
== Series Details ==
Series: drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
URL : https://patchwork.freedesktop.org/series/96344/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21463
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/index.html
Participating hosts (38 -> 33)
------------------------------
Missing (5): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_21463 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html
- fi-tgl-1115g4: [PASS][4] -> [FAIL][5] ([i915#1888])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][6] ([i915#2940]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
Build changes
-------------
* Linux: CI_DRM_10797 -> Patchwork_21463
CI-20190529: 20190529
CI_DRM_10797: 048d1b5b865500e0aad21924985e32a48920b75a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6262: d1c793b26e31cc6ae3f9fa3239805a9bbcc749fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21463: 1250a9fe273933ed81535f419da65ef0c1171119 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1250a9fe2739 drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/index.html
[-- Attachment #2: Type: text/html, Size: 3487 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
2021-10-27 13:59 [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg() Jani Nikula
2021-10-27 16:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-10-27 19:42 ` Navare, Manasi
2021-10-28 9:52 ` Jani Nikula
2021-10-27 21:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Navare, Manasi @ 2021-10-27 19:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Oct 27, 2021 at 04:59:00PM +0300, Jani Nikula wrote:
> The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
> debugging, and should not be info level messages.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
I think in the patch commit title there is a typo 'dcs' i think you meant drm/i915/dsc:
Other than that I agree with having these as debug messages rather than info.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index fa84be609d5d..bf8d3c7ca2d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -598,7 +598,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val |= DSC_422_ENABLE;
> if (vdsc_cfg->vbr_enable)
> pps_val |= DSC_VBR_ENABLE;
> - drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
> pps_val);
> @@ -622,7 +622,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> /* Populate PICTURE_PARAMETER_SET_1 registers */
> pps_val = 0;
> pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
> - drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
> pps_val);
> @@ -647,7 +647,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> - drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
> pps_val);
> @@ -672,7 +672,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> - drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
> pps_val);
> @@ -697,7 +697,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> - drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
> pps_val);
> @@ -722,7 +722,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> - drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
> pps_val);
> @@ -749,7 +749,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
> DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> - drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
> pps_val);
> @@ -774,7 +774,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> - drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
> pps_val);
> @@ -799,7 +799,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> - drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
> pps_val);
> @@ -824,7 +824,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> pps_val = 0;
> pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> - drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
> pps_val);
> @@ -851,7 +851,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
> DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
> DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> - drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
> pps_val);
> @@ -879,7 +879,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> vdsc_cfg->slice_width) |
> DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> vdsc_cfg->slice_height);
> - drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
> + drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
> pps_val);
> @@ -906,8 +906,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> rc_buf_thresh_dword[i / 4] |=
> (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> BITS_PER_BYTE * (i % 4));
> - drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
> - rc_buf_thresh_dword[i / 4]);
> + drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
> + rc_buf_thresh_dword[i / 4]);
> }
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
> @@ -963,8 +963,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> RC_MAX_QP_SHIFT) |
> (vdsc_cfg->rc_range_params[i].range_min_qp <<
> RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> - drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
> - rc_range_params_dword[i / 2]);
> + drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
> + rc_range_params_dword[i / 2]);
> }
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
2021-10-27 13:59 [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg() Jani Nikula
2021-10-27 16:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-27 19:42 ` [Intel-gfx] [PATCH] " Navare, Manasi
@ 2021-10-27 21:59 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2021-10-27 21:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30277 bytes --]
== Series Details ==
Series: drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
URL : https://patchwork.freedesktop.org/series/96344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21463_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21463_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21463_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21463_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@pi-common@vecs0:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl4/igt@gem_exec_schedule@pi-common@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@gem_exec_schedule@pi-common@vecs0.html
Known issues
------------
Here are the changes found in Patchwork_21463_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [FAIL][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk7/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk9/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk2/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk2/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk5/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk5/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk6/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][53] -> [FAIL][54] ([i915#2842]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][55] ([i915#2842])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][56] -> [FAIL][57] ([i915#2842]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-tglb: [PASS][58] -> [FAIL][59] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-sync@rcs0:
- shard-kbl: [PASS][60] -> [SKIP][61] ([fdo#109271])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl4/igt@gem_exec_fair@basic-sync@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@gem_exec_fair@basic-sync@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][62] -> [FAIL][63] ([i915#2849])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2190])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-glk: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#3323])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_workarounds@suspend-resume:
- shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#456])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb2/igt@gem_workarounds@suspend-resume.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-tglb7/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#1937])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-apl1/igt@i915_suspend@sysfs-reader.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl6/igt@i915_suspend@sysfs-reader.html
- shard-kbl: [PASS][71] -> [DMESG-WARN][72] ([i915#180])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl4/igt@i915_suspend@sysfs-reader.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][73] ([i915#3743]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3777]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3777])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271]) +138 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +6 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886]) +4 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +8 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +7 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-c-ctm-negative:
- shard-skl: [PASS][85] -> [DMESG-WARN][86] ([i915#1982])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl8/igt@kms_color@pipe-c-ctm-negative.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_color@pipe-c-ctm-negative.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][87] ([i915#1319]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> [TIMEOUT][88] ([i915#1319])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl3/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271]) +102 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][90] ([i915#2346])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [PASS][91] -> [FAIL][92] ([i915#2346])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][93] -> [INCOMPLETE][94] ([i915#180] / [i915#636])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271]) +93 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [PASS][96] -> [FAIL][97] ([i915#79])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [PASS][98] -> [SKIP][99] ([i915#3701])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-tglb: [PASS][100] -> [INCOMPLETE][101] ([i915#2828] / [i915#456])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-glk: NOTRUN -> [SKIP][102] ([fdo#109271]) +40 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-tglb: [PASS][103] -> [INCOMPLETE][104] ([i915#2411] / [i915#456])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][105] ([i915#1188])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#533]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#533])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: NOTRUN -> [DMESG-WARN][108] ([i915#180]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][109] ([fdo#108145] / [i915#265])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][110] -> [FAIL][111] ([fdo#108145] / [i915#265]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][114] ([i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-glk: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#2733])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#658])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#658]) +3 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
- shard-kbl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#658]) +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][119] -> [SKIP][120] ([fdo#109441]) +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#533]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2437])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2437])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][124] -> [FAIL][125] ([i915#1722])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl8/igt@perf@polling-small-buf.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl9/igt@perf@polling-small-buf.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2994]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl7/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-1:
- shard-skl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#2994])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@pidname:
- shard-kbl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#2994])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@drm_mm@all@insert:
- shard-skl: [INCOMPLETE][129] ([i915#2485]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@drm_mm@all@insert.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl6/igt@drm_mm@all@insert.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [TIMEOUT][131] ([i915#3063]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb5/igt@gem_eio@in-flight-contexts-immediate.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][133] ([i915#2842]) -> [PASS][134] +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][135] ([i915#180]) -> [PASS][136] +2 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-skl: [DMESG-WARN][137] ([i915#1982]) -> [PASS][138] +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl10/igt@kms_color@pipe-c-ctm-blue-to-red.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl7/igt@kms_color@pipe-c-ctm-blue-to-red.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][139] ([i915#72]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [FAIL][141] ([i915#2346]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
- shard-skl: [FAIL][143] ([i915#2122]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl6/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][145] ([i915#79]) -> [PASS][146] +1 similar issue
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][147] ([i915#180]) -> [PASS][148] +7 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: [INCOMPLETE][149] ([i915#198]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][151] ([fdo#108145] / [i915#265]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][153] ([fdo#109441]) -> [PASS][154] +3 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][155] ([i915#1542]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl10/igt@perf@polling-parameterized.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-skl9/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][157] ([i915#2842]) -> [FAIL][158] ([i915#2852])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][159] ([i915#2842]) -> [SKIP][160] ([fdo#109271])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][161] ([i915#1804] / [i915#2684]) -> [WARN][162] ([i915#2684])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][163] ([i915#2684]) -> [WARN][164] ([i915#1804] / [i915#2684])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][165] ([i915#2920]) -> [SKIP][166] ([i915#658])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/shard-iclb5/igt@kms_psr2_sf@primary-plane
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21463/index.html
[-- Attachment #2: Type: text/html, Size: 33397 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
2021-10-27 19:42 ` [Intel-gfx] [PATCH] " Navare, Manasi
@ 2021-10-28 9:52 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2021-10-28 9:52 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Wed, 27 Oct 2021, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Wed, Oct 27, 2021 at 04:59:00PM +0300, Jani Nikula wrote:
>> The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
>> debugging, and should not be info level messages.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> I think in the patch commit title there is a typo 'dcs' i think you meant drm/i915/dsc:
> Other than that I agree with having these as debug messages rather than info.
Whoops, fixed while pushing. Thanks.
Jani.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------
>> 1 file changed, 16 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index fa84be609d5d..bf8d3c7ca2d9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -598,7 +598,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val |= DSC_422_ENABLE;
>> if (vdsc_cfg->vbr_enable)
>> pps_val |= DSC_VBR_ENABLE;
>> - drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
>> pps_val);
>> @@ -622,7 +622,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> /* Populate PICTURE_PARAMETER_SET_1 registers */
>> pps_val = 0;
>> pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
>> - drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
>> pps_val);
>> @@ -647,7 +647,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
>> DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
>> - drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
>> pps_val);
>> @@ -672,7 +672,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
>> DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
>> - drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
>> pps_val);
>> @@ -697,7 +697,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
>> DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>> - drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
>> pps_val);
>> @@ -722,7 +722,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
>> DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
>> - drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
>> pps_val);
>> @@ -749,7 +749,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
>> DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
>> DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
>> - drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
>> pps_val);
>> @@ -774,7 +774,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
>> DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>> - drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
>> pps_val);
>> @@ -799,7 +799,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
>> DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>> - drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
>> pps_val);
>> @@ -824,7 +824,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> pps_val = 0;
>> pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
>> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>> - drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
>> pps_val);
>> @@ -851,7 +851,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
>> DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
>> DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
>> - drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
>> pps_val);
>> @@ -879,7 +879,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> vdsc_cfg->slice_width) |
>> DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
>> vdsc_cfg->slice_height);
>> - drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
>> + drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
>> pps_val);
>> @@ -906,8 +906,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> rc_buf_thresh_dword[i / 4] |=
>> (u32)(vdsc_cfg->rc_buf_thresh[i] <<
>> BITS_PER_BYTE * (i % 4));
>> - drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
>> - rc_buf_thresh_dword[i / 4]);
>> + drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
>> + rc_buf_thresh_dword[i / 4]);
>> }
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
>> @@ -963,8 +963,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> RC_MAX_QP_SHIFT) |
>> (vdsc_cfg->rc_range_params[i].range_min_qp <<
>> RC_MIN_QP_SHIFT)) << 16 * (i % 2));
>> - drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
>> - rc_range_params_dword[i / 2]);
>> + drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
>> + rc_range_params_dword[i / 2]);
>> }
>> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
>> --
>> 2.30.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-10-28 9:52 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-10-27 13:59 [Intel-gfx] [PATCH] drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg() Jani Nikula
2021-10-27 16:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-27 19:42 ` [Intel-gfx] [PATCH] " Navare, Manasi
2021-10-28 9:52 ` Jani Nikula
2021-10-27 21:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
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