* [v4][PATCH 0/3] adding gamma state checker for icl+ platforms
@ 2019-09-21 20:10 Swati Sharma
2019-09-21 20:10 ` [v4][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Swati Sharma @ 2019-09-21 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal
In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.
Major changes done in patch 2, details in commit message.
Swati Sharma (3):
drm/i915/color: Fix formatting issues
drm/i915/color: Extract icl_read_luts()
FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
drivers/gpu/drm/i915/display/intel_color.c | 168 ++++++++++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 138 insertions(+), 36 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [v4][PATCH 1/3] drm/i915/color: Fix formatting issues 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma @ 2019-09-21 20:10 ` Swati Sharma 2019-09-22 10:26 ` Jani Nikula 2019-09-21 20:10 ` [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma ` (5 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Swati Sharma @ 2019-09-21 20:10 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal Fixed few formatting issues in multi-segmented load_lut(). v3: -style nitting [Jani] -balanced parentheses moved from patch 2 to 1 [Jani] -subject prefix change [Jani] -added commit message [Jani] v4: -rearranged INDEX register write in ilk_read_luts() Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 40 ++++++++++++++---------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 318308d..f774938 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) u32 i; /* - * Every entry in the multi-segment LUT is corresponding to a superfine - * segment step which is 1/(8 * 128 * 256). + * Program Super Fine segment (let's call it seg1)... * - * Superfine segment has 9 entries, corresponding to values - * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256). + * Super Fine segment's step is 1/(8 * 128 * 256) and it has + * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), + * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). */ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); @@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) u32 i; /* - * * Program Fine segment (let's call it seg2)... * - * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256) - * ... 256/(128*256). So in order to program fine segment of LUT we - * need to pick every 8'th entry in LUT, and program 256 indexes. + * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) + * ... 256/(128 * 256). So in order to program fine segment of LUT we + * need to pick every 8th entry in the LUT, and program 256 indexes. * * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], - * with seg2[0] being unused by the hardware. + * seg2[0] being unused by the hardware. */ I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); + for (i = 1; i < 257; i++) { entry = &lut[i * 8]; I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); @@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) /* * Program Coarse segment (let's call it seg3)... * - * Coarse segment's starts from index 0 and it's step is 1/256 ie 0, - * 1/256, 2/256 ...256/256. As per the description of each entry in LUT + * Coarse segment starts from index 0 and it's step is 1/256 ie 0, + * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT * above, we need to pick every (8 * 128)th entry in LUT, and * program 256 of those. * @@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) case GAMMA_MODE_MODE_8BIT: i9xx_load_luts(crtc_state); break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: icl_program_gamma_superfine_segment(crtc_state); icl_program_gamma_multi_segment(crtc_state); break; - default: bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc); @@ -1712,9 +1710,6 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) struct drm_color_lut *blob_data; u32 i, val; - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | - PAL_PREC_AUTO_INCREMENT); - blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * hw_lut_size, NULL); @@ -1723,6 +1718,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) blob_data = blob->data; + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | + PAL_PREC_AUTO_INCREMENT); + for (i = 0; i < hw_lut_size; i++) { val = I915_READ(PREC_PAL_DATA(pipe)); @@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc) else dev_priv->display.color_commit = ilk_color_commit; - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_GEN(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { dev_priv->display.load_luts = glk_load_luts; dev_priv->display.read_luts = glk_read_luts; - } else if (INTEL_GEN(dev_priv) >= 8) + } else if (INTEL_GEN(dev_priv) >= 8) { dev_priv->display.load_luts = bdw_load_luts; - else if (INTEL_GEN(dev_priv) >= 7) + } else if (INTEL_GEN(dev_priv) >= 7) { dev_priv->display.load_luts = ivb_load_luts; - else { + } else { dev_priv->display.load_luts = ilk_load_luts; dev_priv->display.read_luts = ilk_read_luts; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 1/3] drm/i915/color: Fix formatting issues 2019-09-21 20:10 ` [v4][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma @ 2019-09-22 10:26 ` Jani Nikula 2019-09-23 5:29 ` Sharma, Swati2 0 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2019-09-22 10:26 UTC (permalink / raw) To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > Fixed few formatting issues in multi-segmented load_lut(). > > v3: -style nitting [Jani] > -balanced parentheses moved from patch 2 to 1 [Jani] > -subject prefix change [Jani] > -added commit message [Jani] > v4: -rearranged INDEX register write in ilk_read_luts() > > Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> but please read on about something else inline... > --- > drivers/gpu/drm/i915/display/intel_color.c | 40 ++++++++++++++---------------- > 1 file changed, 19 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index 318308d..f774938 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) > u32 i; > > /* > - * Every entry in the multi-segment LUT is corresponding to a superfine > - * segment step which is 1/(8 * 128 * 256). > + * Program Super Fine segment (let's call it seg1)... > * > - * Superfine segment has 9 entries, corresponding to values > - * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256). > + * Super Fine segment's step is 1/(8 * 128 * 256) and it has > + * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), > + * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). > */ > I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); > > @@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) > u32 i; > > /* > - * > * Program Fine segment (let's call it seg2)... > * > - * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256) > - * ... 256/(128*256). So in order to program fine segment of LUT we > - * need to pick every 8'th entry in LUT, and program 256 indexes. > + * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) > + * ... 256/(128 * 256). So in order to program fine segment of LUT we > + * need to pick every 8th entry in the LUT, and program 256 indexes. > * > * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], > - * with seg2[0] being unused by the hardware. > + * seg2[0] being unused by the hardware. > */ > I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); > + > for (i = 1; i < 257; i++) { > entry = &lut[i * 8]; > I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); > @@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) > /* > * Program Coarse segment (let's call it seg3)... > * > - * Coarse segment's starts from index 0 and it's step is 1/256 ie 0, > - * 1/256, 2/256 ...256/256. As per the description of each entry in LUT > + * Coarse segment starts from index 0 and it's step is 1/256 ie 0, > + * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT > * above, we need to pick every (8 * 128)th entry in LUT, and > * program 256 of those. > * > @@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) > case GAMMA_MODE_MODE_8BIT: > i9xx_load_luts(crtc_state); > break; > - > case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > icl_program_gamma_superfine_segment(crtc_state); > icl_program_gamma_multi_segment(crtc_state); > break; > - > default: > bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); > ivb_load_lut_ext_max(crtc); > @@ -1712,9 +1710,6 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) > struct drm_color_lut *blob_data; > u32 i, val; > > - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | > - PAL_PREC_AUTO_INCREMENT); > - > blob = drm_property_create_blob(&dev_priv->drm, > sizeof(struct drm_color_lut) * hw_lut_size, > NULL); > @@ -1723,6 +1718,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) > > blob_data = blob->data; > > + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | > + PAL_PREC_AUTO_INCREMENT); > + The above two hunks actually change glk_read_lut_10(). You're running a really old version of git that has a bug in the context annotation. Please consider upgrading when you have a moment to spare for that. BR, Jani. > for (i = 0; i < hw_lut_size; i++) { > val = I915_READ(PREC_PAL_DATA(pipe)); > > @@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc) > else > dev_priv->display.color_commit = ilk_color_commit; > > - if (INTEL_GEN(dev_priv) >= 11) > + if (INTEL_GEN(dev_priv) >= 11) { > dev_priv->display.load_luts = icl_load_luts; > - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { > + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { > dev_priv->display.load_luts = glk_load_luts; > dev_priv->display.read_luts = glk_read_luts; > - } else if (INTEL_GEN(dev_priv) >= 8) > + } else if (INTEL_GEN(dev_priv) >= 8) { > dev_priv->display.load_luts = bdw_load_luts; > - else if (INTEL_GEN(dev_priv) >= 7) > + } else if (INTEL_GEN(dev_priv) >= 7) { > dev_priv->display.load_luts = ivb_load_luts; > - else { > + } else { > dev_priv->display.load_luts = ilk_load_luts; > dev_priv->display.read_luts = ilk_read_luts; > } -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 1/3] drm/i915/color: Fix formatting issues 2019-09-22 10:26 ` Jani Nikula @ 2019-09-23 5:29 ` Sharma, Swati2 0 siblings, 0 replies; 13+ messages in thread From: Sharma, Swati2 @ 2019-09-23 5:29 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal On 22-Sep-19 3:56 PM, Jani Nikula wrote: > On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: >> Fixed few formatting issues in multi-segmented load_lut(). >> >> v3: -style nitting [Jani] >> -balanced parentheses moved from patch 2 to 1 [Jani] >> -subject prefix change [Jani] >> -added commit message [Jani] >> v4: -rearranged INDEX register write in ilk_read_luts() >> >> Signed-off-by: Swati Sharma <swati2.sharma@intel.com> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > but please read on about something else inline... > >> --- >> drivers/gpu/drm/i915/display/intel_color.c | 40 ++++++++++++++---------------- >> 1 file changed, 19 insertions(+), 21 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c >> index 318308d..f774938 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color.c >> +++ b/drivers/gpu/drm/i915/display/intel_color.c >> @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) >> u32 i; >> >> /* >> - * Every entry in the multi-segment LUT is corresponding to a superfine >> - * segment step which is 1/(8 * 128 * 256). >> + * Program Super Fine segment (let's call it seg1)... >> * >> - * Superfine segment has 9 entries, corresponding to values >> - * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256). >> + * Super Fine segment's step is 1/(8 * 128 * 256) and it has >> + * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), >> + * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). >> */ >> I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); >> >> @@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) >> u32 i; >> >> /* >> - * >> * Program Fine segment (let's call it seg2)... >> * >> - * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256) >> - * ... 256/(128*256). So in order to program fine segment of LUT we >> - * need to pick every 8'th entry in LUT, and program 256 indexes. >> + * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) >> + * ... 256/(128 * 256). So in order to program fine segment of LUT we >> + * need to pick every 8th entry in the LUT, and program 256 indexes. >> * >> * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], >> - * with seg2[0] being unused by the hardware. >> + * seg2[0] being unused by the hardware. >> */ >> I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); >> + >> for (i = 1; i < 257; i++) { >> entry = &lut[i * 8]; >> I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); >> @@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) >> /* >> * Program Coarse segment (let's call it seg3)... >> * >> - * Coarse segment's starts from index 0 and it's step is 1/256 ie 0, >> - * 1/256, 2/256 ...256/256. As per the description of each entry in LUT >> + * Coarse segment starts from index 0 and it's step is 1/256 ie 0, >> + * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT >> * above, we need to pick every (8 * 128)th entry in LUT, and >> * program 256 of those. >> * >> @@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) >> case GAMMA_MODE_MODE_8BIT: >> i9xx_load_luts(crtc_state); >> break; >> - >> case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: >> icl_program_gamma_superfine_segment(crtc_state); >> icl_program_gamma_multi_segment(crtc_state); >> break; >> - >> default: >> bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); >> ivb_load_lut_ext_max(crtc); >> @@ -1712,9 +1710,6 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) >> struct drm_color_lut *blob_data; >> u32 i, val; >> >> - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | >> - PAL_PREC_AUTO_INCREMENT); >> - >> blob = drm_property_create_blob(&dev_priv->drm, >> sizeof(struct drm_color_lut) * hw_lut_size, >> NULL); >> @@ -1723,6 +1718,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) >> >> blob_data = blob->data; >> >> + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | >> + PAL_PREC_AUTO_INCREMENT); >> + > > The above two hunks actually change glk_read_lut_10(). You're running a > really old version of git that has a bug in the context > annotation. Please consider upgrading when you have a moment to spare > for that.Done. > > BR, > Jani. > > >> for (i = 0; i < hw_lut_size; i++) { >> val = I915_READ(PREC_PAL_DATA(pipe)); >> >> @@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc) >> else >> dev_priv->display.color_commit = ilk_color_commit; >> >> - if (INTEL_GEN(dev_priv) >= 11) >> + if (INTEL_GEN(dev_priv) >= 11) { >> dev_priv->display.load_luts = icl_load_luts; >> - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { >> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { >> dev_priv->display.load_luts = glk_load_luts; >> dev_priv->display.read_luts = glk_read_luts; >> - } else if (INTEL_GEN(dev_priv) >= 8) >> + } else if (INTEL_GEN(dev_priv) >= 8) { >> dev_priv->display.load_luts = bdw_load_luts; >> - else if (INTEL_GEN(dev_priv) >= 7) >> + } else if (INTEL_GEN(dev_priv) >= 7) { >> dev_priv->display.load_luts = ivb_load_luts; >> - else { >> + } else { >> dev_priv->display.load_luts = ilk_load_luts; >> dev_priv->display.read_luts = ilk_read_luts; >> } > -- ~Swati Sharma _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma 2019-09-21 20:10 ` [v4][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma @ 2019-09-21 20:10 ` Swati Sharma 2019-09-24 12:17 ` Jani Nikula 2019-09-21 20:10 ` [v4][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma ` (4 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Swati Sharma @ 2019-09-21 20:10 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal For icl+, have hw read out to create hw blob of gamma lut values. icl+ platforms supports multi segmented gamma mode by default, add hw lut creation for this mode. This will be used to validate gamma programming using dsb (display state buffer) which is a tgl specific feature. Major change done-removal of readouts of coarse and fine segments because PAL_PREC_DATA register isn't giving propoer values. State checker limited only to "fine segment" v2: -readout code for multisegmented gamma has to come up with some intermediate entries that aren't preserved in hardware (Jani N) -linear interpolation (Ville) -moved common code to check gamma_enable to specific funcs, since icl doesn't support that v3: -use u16 instead of __u16 [Jani N] -used single lut [Jani N] -improved and more readable for loops [Jani N] -read values directly to actual locations and then fill gaps [Jani N] -moved cleaning to patch 1 [Jani N] -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to make it similar to icl_load_luts() -renamed icl_compute_interpolated_gamma_blob() to icl_compute_interpolated_gamma_lut_values() more sensible, I guess v4: -removed interpolated func for creating gamma lut values -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA correctly Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 126 +++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 2 files changed, 117 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index f774938..299ada5b 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) { + if (!crtc_state->gamma_enable) + return 0; + switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: return 8; @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) { + if (!crtc_state->gamma_enable) + return 0; + if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) return 0; @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) { + if (!crtc_state->gamma_enable) + return 0; + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) return 10; else @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) { + if (!crtc_state->gamma_enable) + return 0; + switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: return 8; @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) } } +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) +{ + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + return 0; + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + return 8; + case GAMMA_MODE_MODE_10BIT: + return 10; + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + return 16; + default: + MISSING_CASE(crtc_state->gamma_mode); + return 0; + } + +} + int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!crtc_state->gamma_enable) - return 0; - if (HAS_GMCH(dev_priv)) { if (IS_CHERRYVIEW(dev_priv)) return chv_gamma_precision(crtc_state); else return i9xx_gamma_precision(crtc_state); } else { - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 11) + return icl_gamma_precision(crtc_state); + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) return glk_gamma_precision(crtc_state); else if (IS_IRONLAKE(dev_priv)) return ilk_gamma_precision(crtc_state); @@ -1464,6 +1494,20 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1, return true; } +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1, + struct drm_color_lut *lut2, + int lut_size, u32 err) +{ + int i; + + for (i = 0; i < 9; i++) { + if (!err_check(&lut1[i], &lut2[i], err)) + return false; + } + + return true; +} + bool intel_color_lut_equal(struct drm_property_blob *blob1, struct drm_property_blob *blob2, u32 gamma_mode, u32 bit_precision) @@ -1482,16 +1526,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, lut_size2 = drm_color_lut_size(blob2); /* check sw and hw lut size */ - switch (gamma_mode) { - case GAMMA_MODE_MODE_8BIT: - case GAMMA_MODE_MODE_10BIT: - if (lut_size1 != lut_size2) - return false; - break; - default: - MISSING_CASE(gamma_mode); - return false; - } + if (lut_size1 != lut_size2) + return false; lut1 = blob1->data; lut2 = blob2->data; @@ -1499,13 +1535,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, err = 0xffff >> bit_precision; /* check sw and hw lut entry to be equal */ - switch (gamma_mode) { + switch (gamma_mode & GAMMA_MODE_MODE_MASK) { case GAMMA_MODE_MODE_8BIT: case GAMMA_MODE_MODE_10BIT: if (!intel_color_lut_entry_equal(lut1, lut2, lut_size2, err)) return false; break; + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + if (!intel_color_lut_entry_multi_equal(lut1, lut2, + lut_size2, err)) + return false; + break; default: MISSING_CASE(gamma_mode); return false; @@ -1745,6 +1786,60 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state) crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); } +static struct drm_property_blob * +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *blob_data; + u32 i, val1, val2; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + blob_data = blob->data; + + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < 9; i++) { + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); + + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 | + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1); + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 | + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1); + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 | + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1); + } + + /* + * FIXME readouts from PAL_PREC_DATA register aren't giving correct values + * in the case of fine and coarse segments. Restricting readouts only for + * super fine segment as of now. + */ + + return blob; +} + +static void icl_read_luts(struct intel_crtc_state *crtc_state) +{ + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == + GAMMA_MODE_MODE_8BIT) + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED) + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state); + else + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1788,6 +1883,7 @@ void intel_color_init(struct intel_crtc *crtc) if (INTEL_GEN(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; + dev_priv->display.read_luts = icl_read_luts; } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { dev_priv->display.load_luts = glk_load_luts; dev_priv->display.read_luts = glk_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bf37ece..1ea26c8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10401,6 +10401,12 @@ enum skl_power_gate { #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ _PAL_PREC_MULTI_SEG_INDEX_A, \ -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() 2019-09-21 20:10 ` [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma @ 2019-09-24 12:17 ` Jani Nikula 2019-09-24 14:28 ` Sharma, Swati2 2019-09-25 5:43 ` Saarinen, Jani 0 siblings, 2 replies; 13+ messages in thread From: Jani Nikula @ 2019-09-24 12:17 UTC (permalink / raw) To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > For icl+, have hw read out to create hw blob of gamma > lut values. icl+ platforms supports multi segmented gamma > mode by default, add hw lut creation for this mode. > > This will be used to validate gamma programming using dsb > (display state buffer) which is a tgl specific feature. > > Major change done-removal of readouts of coarse and fine segments > because PAL_PREC_DATA register isn't giving propoer values. > State checker limited only to "fine segment" > > v2: -readout code for multisegmented gamma has to come > up with some intermediate entries that aren't preserved > in hardware (Jani N) > -linear interpolation (Ville) > -moved common code to check gamma_enable to specific funcs, > since icl doesn't support that > v3: -use u16 instead of __u16 [Jani N] > -used single lut [Jani N] > -improved and more readable for loops [Jani N] > -read values directly to actual locations and then fill gaps [Jani N] > -moved cleaning to patch 1 [Jani N] > -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to > make it similar to icl_load_luts() > -renamed icl_compute_interpolated_gamma_blob() to > icl_compute_interpolated_gamma_lut_values() more sensible, I guess > v4: -removed interpolated func for creating gamma lut values > -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA > correctly > > Signed-off-by: Swati Sharma <swati2.sharma@intel.com> > --- > drivers/gpu/drm/i915/display/intel_color.c | 126 +++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 6 ++ > 2 files changed, 117 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index f774938..299ada5b 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) > > static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) > { > + if (!crtc_state->gamma_enable) > + return 0; > + > switch (crtc_state->gamma_mode) { > case GAMMA_MODE_MODE_8BIT: > return 8; > @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) > > static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) > { > + if (!crtc_state->gamma_enable) > + return 0; > + > if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) > return 0; > > @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) > > static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) > { > + if (!crtc_state->gamma_enable) > + return 0; > + > if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) > return 10; > else > @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) > > static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) > { > + if (!crtc_state->gamma_enable) > + return 0; > + > switch (crtc_state->gamma_mode) { > case GAMMA_MODE_MODE_8BIT: > return 8; > @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) > } > } > > +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) > +{ > + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) > + return 0; > + > + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { > + case GAMMA_MODE_MODE_8BIT: > + return 8; > + case GAMMA_MODE_MODE_10BIT: > + return 10; > + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > + return 16; > + default: > + MISSING_CASE(crtc_state->gamma_mode); > + return 0; > + } > + > +} > + > int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > - if (!crtc_state->gamma_enable) > - return 0; > - > if (HAS_GMCH(dev_priv)) { > if (IS_CHERRYVIEW(dev_priv)) > return chv_gamma_precision(crtc_state); > else > return i9xx_gamma_precision(crtc_state); > } else { > - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) > + if (INTEL_GEN(dev_priv) >= 11) > + return icl_gamma_precision(crtc_state); > + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) > return glk_gamma_precision(crtc_state); > else if (IS_IRONLAKE(dev_priv)) > return ilk_gamma_precision(crtc_state); > @@ -1464,6 +1494,20 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1, > return true; > } > > +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1, > + struct drm_color_lut *lut2, > + int lut_size, u32 err) > +{ > + int i; > + > + for (i = 0; i < 9; i++) { > + if (!err_check(&lut1[i], &lut2[i], err)) > + return false; > + } > + > + return true; > +} > + > bool intel_color_lut_equal(struct drm_property_blob *blob1, > struct drm_property_blob *blob2, > u32 gamma_mode, u32 bit_precision) > @@ -1482,16 +1526,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, > lut_size2 = drm_color_lut_size(blob2); > > /* check sw and hw lut size */ > - switch (gamma_mode) { > - case GAMMA_MODE_MODE_8BIT: > - case GAMMA_MODE_MODE_10BIT: > - if (lut_size1 != lut_size2) > - return false; > - break; > - default: > - MISSING_CASE(gamma_mode); > - return false; > - } > + if (lut_size1 != lut_size2) > + return false; > > lut1 = blob1->data; > lut2 = blob2->data; > @@ -1499,13 +1535,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, > err = 0xffff >> bit_precision; > > /* check sw and hw lut entry to be equal */ > - switch (gamma_mode) { > + switch (gamma_mode & GAMMA_MODE_MODE_MASK) { > case GAMMA_MODE_MODE_8BIT: > case GAMMA_MODE_MODE_10BIT: > if (!intel_color_lut_entry_equal(lut1, lut2, > lut_size2, err)) > return false; > break; > + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > + if (!intel_color_lut_entry_multi_equal(lut1, lut2, > + lut_size2, err)) > + return false; > + break; > default: > MISSING_CASE(gamma_mode); > return false; > @@ -1745,6 +1786,60 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state) > crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); > } > > +static struct drm_property_blob * > +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; > + enum pipe pipe = crtc->pipe; > + struct drm_property_blob *blob; > + struct drm_color_lut *blob_data; > + u32 i, val1, val2; > + > + blob = drm_property_create_blob(&dev_priv->drm, > + sizeof(struct drm_color_lut) * lut_size, > + NULL); > + if (IS_ERR(blob)) > + return NULL; > + > + blob_data = blob->data; > + > + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); > + > + for (i = 0; i < 9; i++) { > + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); > + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); > + > + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 | > + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1); > + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 | > + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1); > + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 | > + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1); > + } > + > + /* > + * FIXME readouts from PAL_PREC_DATA register aren't giving correct values > + * in the case of fine and coarse segments. Restricting readouts only for > + * super fine segment as of now. > + */ Apparently this is causing problems with the display, possibly because the blob ends up being only 9 entries. Can you try to reproduce locally? We're likely going to have to revert this. BR, Jani. > + > + return blob; > +} > + > +static void icl_read_luts(struct intel_crtc_state *crtc_state) > +{ > + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == > + GAMMA_MODE_MODE_8BIT) > + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); > + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == > + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED) > + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state); > + else > + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); > +} > + > void intel_color_init(struct intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > @@ -1788,6 +1883,7 @@ void intel_color_init(struct intel_crtc *crtc) > > if (INTEL_GEN(dev_priv) >= 11) { > dev_priv->display.load_luts = icl_load_luts; > + dev_priv->display.read_luts = icl_read_luts; > } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { > dev_priv->display.load_luts = glk_load_luts; > dev_priv->display.read_luts = glk_read_luts; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index bf37ece..1ea26c8 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10401,6 +10401,12 @@ enum skl_power_gate { > > #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C > #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C > +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) > +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) > +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) > +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) > +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) > +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) > > #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ > _PAL_PREC_MULTI_SEG_INDEX_A, \ -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() 2019-09-24 12:17 ` Jani Nikula @ 2019-09-24 14:28 ` Sharma, Swati2 2019-09-25 5:43 ` Saarinen, Jani 1 sibling, 0 replies; 13+ messages in thread From: Sharma, Swati2 @ 2019-09-24 14:28 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal On 24-Sep-19 5:47 PM, Jani Nikula wrote: > On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: >> For icl+, have hw read out to create hw blob of gamma >> lut values. icl+ platforms supports multi segmented gamma >> mode by default, add hw lut creation for this mode. >> >> This will be used to validate gamma programming using dsb >> (display state buffer) which is a tgl specific feature. >> >> Major change done-removal of readouts of coarse and fine segments >> because PAL_PREC_DATA register isn't giving propoer values. >> State checker limited only to "fine segment" >> >> v2: -readout code for multisegmented gamma has to come >> up with some intermediate entries that aren't preserved >> in hardware (Jani N) >> -linear interpolation (Ville) >> -moved common code to check gamma_enable to specific funcs, >> since icl doesn't support that >> v3: -use u16 instead of __u16 [Jani N] >> -used single lut [Jani N] >> -improved and more readable for loops [Jani N] >> -read values directly to actual locations and then fill gaps [Jani N] >> -moved cleaning to patch 1 [Jani N] >> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to >> make it similar to icl_load_luts() >> -renamed icl_compute_interpolated_gamma_blob() to >> icl_compute_interpolated_gamma_lut_values() more sensible, I guess >> v4: -removed interpolated func for creating gamma lut values >> -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA >> correctly >> >> Signed-off-by: Swati Sharma <swati2.sharma@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_color.c | 126 +++++++++++++++++++++++++---- >> drivers/gpu/drm/i915/i915_reg.h | 6 ++ >> 2 files changed, 117 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c >> index f774938..299ada5b 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color.c >> +++ b/drivers/gpu/drm/i915/display/intel_color.c >> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) >> >> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) >> { >> + if (!crtc_state->gamma_enable) >> + return 0; >> + >> switch (crtc_state->gamma_mode) { >> case GAMMA_MODE_MODE_8BIT: >> return 8; >> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) >> >> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) >> { >> + if (!crtc_state->gamma_enable) >> + return 0; >> + >> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) >> return 0; >> >> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) >> >> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) >> { >> + if (!crtc_state->gamma_enable) >> + return 0; >> + >> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) >> return 10; >> else >> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) >> >> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) >> { >> + if (!crtc_state->gamma_enable) >> + return 0; >> + >> switch (crtc_state->gamma_mode) { >> case GAMMA_MODE_MODE_8BIT: >> return 8; >> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) >> } >> } >> >> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) >> +{ >> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) >> + return 0; >> + >> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { >> + case GAMMA_MODE_MODE_8BIT: >> + return 8; >> + case GAMMA_MODE_MODE_10BIT: >> + return 10; >> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: >> + return 16; >> + default: >> + MISSING_CASE(crtc_state->gamma_mode); >> + return 0; >> + } >> + >> +} >> + >> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) >> { >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> >> - if (!crtc_state->gamma_enable) >> - return 0; >> - >> if (HAS_GMCH(dev_priv)) { >> if (IS_CHERRYVIEW(dev_priv)) >> return chv_gamma_precision(crtc_state); >> else >> return i9xx_gamma_precision(crtc_state); >> } else { >> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) >> + if (INTEL_GEN(dev_priv) >= 11) >> + return icl_gamma_precision(crtc_state); >> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) >> return glk_gamma_precision(crtc_state); >> else if (IS_IRONLAKE(dev_priv)) >> return ilk_gamma_precision(crtc_state); >> @@ -1464,6 +1494,20 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1, >> return true; >> } >> >> +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1, >> + struct drm_color_lut *lut2, >> + int lut_size, u32 err) >> +{ >> + int i; >> + >> + for (i = 0; i < 9; i++) { >> + if (!err_check(&lut1[i], &lut2[i], err)) >> + return false; >> + } >> + >> + return true; >> +} >> + >> bool intel_color_lut_equal(struct drm_property_blob *blob1, >> struct drm_property_blob *blob2, >> u32 gamma_mode, u32 bit_precision) >> @@ -1482,16 +1526,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, >> lut_size2 = drm_color_lut_size(blob2); >> >> /* check sw and hw lut size */ >> - switch (gamma_mode) { >> - case GAMMA_MODE_MODE_8BIT: >> - case GAMMA_MODE_MODE_10BIT: >> - if (lut_size1 != lut_size2) >> - return false; >> - break; >> - default: >> - MISSING_CASE(gamma_mode); >> - return false; >> - } >> + if (lut_size1 != lut_size2) >> + return false; >> >> lut1 = blob1->data; >> lut2 = blob2->data; >> @@ -1499,13 +1535,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, >> err = 0xffff >> bit_precision; >> >> /* check sw and hw lut entry to be equal */ >> - switch (gamma_mode) { >> + switch (gamma_mode & GAMMA_MODE_MODE_MASK) { >> case GAMMA_MODE_MODE_8BIT: >> case GAMMA_MODE_MODE_10BIT: >> if (!intel_color_lut_entry_equal(lut1, lut2, >> lut_size2, err)) >> return false; >> break; >> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: >> + if (!intel_color_lut_entry_multi_equal(lut1, lut2, >> + lut_size2, err)) >> + return false; >> + break; >> default: >> MISSING_CASE(gamma_mode); >> return false; >> @@ -1745,6 +1786,60 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state) >> crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); >> } >> >> +static struct drm_property_blob * >> +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) >> +{ >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; >> + enum pipe pipe = crtc->pipe; >> + struct drm_property_blob *blob; >> + struct drm_color_lut *blob_data; >> + u32 i, val1, val2; >> + >> + blob = drm_property_create_blob(&dev_priv->drm, >> + sizeof(struct drm_color_lut) * lut_size, >> + NULL); >> + if (IS_ERR(blob)) >> + return NULL; >> + >> + blob_data = blob->data; >> + >> + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); >> + >> + for (i = 0; i < 9; i++) { >> + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); >> + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); >> + >> + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 | >> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1); >> + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 | >> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1); >> + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 | >> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1); >> + } >> + >> + /* >> + * FIXME readouts from PAL_PREC_DATA register aren't giving correct values >> + * in the case of fine and coarse segments. Restricting readouts only for >> + * super fine segment as of now. >> + */ > > Apparently this is causing problems with the display, possibly because > the blob ends up being only 9 entries. Can you try to reproduce locally? Reproduced locally. Revert patch sent https://patchwork.freedesktop.org/series/67174/ > > We're likely going to have to revert this. > > BR, > Jani. > > >> + >> + return blob; >> +} >> + >> +static void icl_read_luts(struct intel_crtc_state *crtc_state) >> +{ >> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == >> + GAMMA_MODE_MODE_8BIT) >> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state); >> + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == >> + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED) >> + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state); >> + else >> + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); >> +} >> + >> void intel_color_init(struct intel_crtc *crtc) >> { >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> @@ -1788,6 +1883,7 @@ void intel_color_init(struct intel_crtc *crtc) >> >> if (INTEL_GEN(dev_priv) >= 11) { >> dev_priv->display.load_luts = icl_load_luts; >> + dev_priv->display.read_luts = icl_read_luts; >> } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { >> dev_priv->display.load_luts = glk_load_luts; >> dev_priv->display.read_luts = glk_read_luts; >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index bf37ece..1ea26c8 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -10401,6 +10401,12 @@ enum skl_power_gate { >> >> #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C >> #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C >> +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) >> +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) >> +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) >> +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) >> +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) >> +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) >> >> #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ >> _PAL_PREC_MULTI_SEG_INDEX_A, \ > -- ~Swati Sharma _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() 2019-09-24 12:17 ` Jani Nikula 2019-09-24 14:28 ` Sharma, Swati2 @ 2019-09-25 5:43 ` Saarinen, Jani 1 sibling, 0 replies; 13+ messages in thread From: Saarinen, Jani @ 2019-09-25 5:43 UTC (permalink / raw) To: Nikula, Jani, Sharma, Swati2, intel-gfx@lists.freedesktop.org Cc: daniel.vetter@ffwll.ch, Nautiyal, Ankit K Hi, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula > Sent: tiistai 24. syyskuuta 2019 15.18 > To: Sharma, Swati2 <swati2.sharma@intel.com>; intel-gfx@lists.freedesktop.org > Cc: daniel.vetter@ffwll.ch; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Subject: Re: [Intel-gfx] [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() > > On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > > For icl+, have hw read out to create hw blob of gamma lut values. icl+ > > platforms supports multi segmented gamma mode by default, add hw lut > > creation for this mode. > > > > This will be used to validate gamma programming using dsb (display > > state buffer) which is a tgl specific feature. > > > > Major change done-removal of readouts of coarse and fine segments > > because PAL_PREC_DATA register isn't giving propoer values. > > State checker limited only to "fine segment" > > > > v2: -readout code for multisegmented gamma has to come > > up with some intermediate entries that aren't preserved > > in hardware (Jani N) > > -linear interpolation (Ville) > > -moved common code to check gamma_enable to specific funcs, > > since icl doesn't support that > > v3: -use u16 instead of __u16 [Jani N] > > -used single lut [Jani N] > > -improved and more readable for loops [Jani N] > > -read values directly to actual locations and then fill gaps [Jani N] > > -moved cleaning to patch 1 [Jani N] > > -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to > > make it similar to icl_load_luts() > > -renamed icl_compute_interpolated_gamma_blob() to > > icl_compute_interpolated_gamma_lut_values() more sensible, I > > guess > > v4: -removed interpolated func for creating gamma lut values > > -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA > > correctly > > > > Signed-off-by: Swati Sharma <swati2.sharma@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_color.c | 126 +++++++++++++++++++++++++-- > -- > > drivers/gpu/drm/i915/i915_reg.h | 6 ++ > > 2 files changed, 117 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > > b/drivers/gpu/drm/i915/display/intel_color.c > > index f774938..299ada5b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_color.c > > +++ b/drivers/gpu/drm/i915/display/intel_color.c > > @@ -1371,6 +1371,9 @@ static int icl_color_check(struct > > intel_crtc_state *crtc_state) > > > > static int i9xx_gamma_precision(const struct intel_crtc_state > > *crtc_state) { > > + if (!crtc_state->gamma_enable) > > + return 0; > > + > > switch (crtc_state->gamma_mode) { > > case GAMMA_MODE_MODE_8BIT: > > return 8; > > @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct > > intel_crtc_state *crtc_state) > > > > static int ilk_gamma_precision(const struct intel_crtc_state > > *crtc_state) { > > + if (!crtc_state->gamma_enable) > > + return 0; > > + > > if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) > > return 0; > > > > @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct > > intel_crtc_state *crtc_state) > > > > static int chv_gamma_precision(const struct intel_crtc_state > > *crtc_state) { > > + if (!crtc_state->gamma_enable) > > + return 0; > > + > > if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) > > return 10; > > else > > @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct > > intel_crtc_state *crtc_state) > > > > static int glk_gamma_precision(const struct intel_crtc_state > > *crtc_state) { > > + if (!crtc_state->gamma_enable) > > + return 0; > > + > > switch (crtc_state->gamma_mode) { > > case GAMMA_MODE_MODE_8BIT: > > return 8; > > @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct > intel_crtc_state *crtc_state) > > } > > } > > > > +static int icl_gamma_precision(const struct intel_crtc_state > > +*crtc_state) { > > + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) > > + return 0; > > + > > + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { > > + case GAMMA_MODE_MODE_8BIT: > > + return 8; > > + case GAMMA_MODE_MODE_10BIT: > > + return 10; > > + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > > + return 16; > > + default: > > + MISSING_CASE(crtc_state->gamma_mode); > > + return 0; > > + } > > + > > +} > > + > > int intel_color_get_gamma_bit_precision(const struct intel_crtc_state > > *crtc_state) { > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > - if (!crtc_state->gamma_enable) > > - return 0; > > - > > if (HAS_GMCH(dev_priv)) { > > if (IS_CHERRYVIEW(dev_priv)) > > return > chv_gamma_precision(crtc_state); > > else > > return > i9xx_gamma_precision(crtc_state); > > } else { > > - if (IS_CANNONLAKE(dev_priv) || > IS_GEMINILAKE(dev_priv)) > > + if (INTEL_GEN(dev_priv) >= 11) > > + return > icl_gamma_precision(crtc_state); > > + else if (IS_CANNONLAKE(dev_priv) || > IS_GEMINILAKE(dev_priv)) > > return > glk_gamma_precision(crtc_state); > > else if (IS_IRONLAKE(dev_priv)) > > return > ilk_gamma_precision(crtc_state); @@ -1464,6 +1494,20 @@ > > static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1, > > return true; > > } > > > > +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1, > > + struct > drm_color_lut *lut2, > > + int > lut_size, u32 err) > > +{ > > + int i; > > + > > + for (i = 0; i < 9; i++) { > > + if (!err_check(&lut1[i], &lut2[i], err)) > > + return false; > > + } > > + > > + return true; > > +} > > + > > bool intel_color_lut_equal(struct drm_property_blob *blob1, > > struct drm_property_blob *blob2, > > u32 gamma_mode, u32 bit_precision) > @@ -1482,16 +1526,8 @@ bool > > intel_color_lut_equal(struct drm_property_blob *blob1, > > lut_size2 = drm_color_lut_size(blob2); > > > > /* check sw and hw lut size */ > > - switch (gamma_mode) { > > - case GAMMA_MODE_MODE_8BIT: > > - case GAMMA_MODE_MODE_10BIT: > > - if (lut_size1 != lut_size2) > > - return false; > > - break; > > - default: > > - MISSING_CASE(gamma_mode); > > - return false; > > - } > > + if (lut_size1 != lut_size2) > > + return false; > > > > lut1 = blob1->data; > > lut2 = blob2->data; > > @@ -1499,13 +1535,18 @@ bool intel_color_lut_equal(struct drm_property_blob > *blob1, > > err = 0xffff >> bit_precision; > > > > /* check sw and hw lut entry to be equal */ > > - switch (gamma_mode) { > > + switch (gamma_mode & GAMMA_MODE_MODE_MASK) { > > case GAMMA_MODE_MODE_8BIT: > > case GAMMA_MODE_MODE_10BIT: > > if (!intel_color_lut_entry_equal(lut1, lut2, > > > lut_size2, err)) > > return false; > > break; > > + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: > > + if (!intel_color_lut_entry_multi_equal(lut1, lut2, > > + > lut_size2, err)) > > + return false; > > + break; > > default: > > MISSING_CASE(gamma_mode); > > return false; > > @@ -1745,6 +1786,60 @@ static void glk_read_luts(struct intel_crtc_state > *crtc_state) > > crtc_state->base.gamma_lut = > glk_read_lut_10(crtc_state, > > PAL_PREC_INDEX_VALUE(0)); } > > > > +static struct drm_property_blob * > > +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state) > > +{ > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; > > + enum pipe pipe = crtc->pipe; > > + struct drm_property_blob *blob; > > + struct drm_color_lut *blob_data; > > + u32 i, val1, val2; > > + > > + blob = drm_property_create_blob(&dev_priv->drm, > > + > sizeof(struct drm_color_lut) * lut_size, > > + NULL); > > + if (IS_ERR(blob)) > > + return NULL; > > + > > + blob_data = blob->data; > > + > > + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), > PAL_PREC_AUTO_INCREMENT); > > + > > + for (i = 0; i < 9; i++) { > > + val1 = > I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); > > + val2 = > I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe)); > > + > > + blob_data[i].red = > REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 | > > + > REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1); > > + blob_data[i].green = > REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 | > > + > REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1); > > + blob_data[i].blue = > REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 | > > + > REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1); > > + } > > + > > + /* > > + * FIXME readouts from PAL_PREC_DATA register aren't giving correct > values > > + * in the case of fine and coarse segments. Restricting readouts only > for > > + * super fine segment as of now. > > + */ > > Apparently this is causing problems with the display, possibly because the blob ends > up being only 9 entries. Can you try to reproduce locally? > > We're likely going to have to revert this. For this fdo bug made: https://bugs.freedesktop.org/show_bug.cgi?id=111809 > > BR, > Jani. > > > > + > > + return blob; > > +} > > + > > +static void icl_read_luts(struct intel_crtc_state *crtc_state) { > > + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == > > + GAMMA_MODE_MODE_8BIT) > > + crtc_state->base.gamma_lut = > i9xx_read_lut_8(crtc_state); > > + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) > == > > + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED) > > + crtc_state->base.gamma_lut = > icl_read_lut_multi_segment(crtc_state); > > + else > > + crtc_state->base.gamma_lut = > glk_read_lut_10(crtc_state, > > +PAL_PREC_INDEX_VALUE(0)); } > > + > > void intel_color_init(struct intel_crtc *crtc) { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ > > -1788,6 +1883,7 @@ void intel_color_init(struct intel_crtc *crtc) > > > > if (INTEL_GEN(dev_priv) >= 11) { > > dev_priv->display.load_luts = > icl_load_luts; > > + dev_priv->display.read_luts = > icl_read_luts; > > } else if (IS_CANNONLAKE(dev_priv) || > IS_GEMINILAKE(dev_priv)) { > > dev_priv->display.load_luts = > glk_load_luts; > > dev_priv->display.read_luts = > glk_read_luts; diff --git > > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index bf37ece..1ea26c8 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -10401,6 +10401,12 @@ enum skl_power_gate { > > > > #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C > > #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C > > +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) > > +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) > > +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) > > +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) > > +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) #define > > +PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) > > > > #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ > > > _PAL_PREC_MULTI_SEG_INDEX_A, \ > > -- > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v4][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma 2019-09-21 20:10 ` [v4][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma 2019-09-21 20:10 ` [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma @ 2019-09-21 20:10 ` Swati Sharma 2019-09-22 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev4) Patchwork ` (3 subsequent siblings) 6 siblings, 0 replies; 13+ messages in thread From: Swati Sharma @ 2019-09-21 20:10 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal Only to print hw and sw lut values/channel. Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 299ada5b..3508d6a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1475,6 +1475,8 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat static bool err_check(struct drm_color_lut *lut1, struct drm_color_lut *lut2, u32 err) { + DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green); + return ((abs((long)lut2->red - lut1->red)) <= err) && ((abs((long)lut2->blue - lut1->blue)) <= err) && ((abs((long)lut2->green - lut1->green)) <= err); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev4) 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma ` (2 preceding siblings ...) 2019-09-21 20:10 ` [v4][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma @ 2019-09-22 12:39 ` Patchwork 2019-09-22 13:02 ` ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2019-09-22 12:39 UTC (permalink / raw) To: Swati Sharma; +Cc: intel-gfx == Series Details == Series: adding gamma state checker for icl+ platforms (rev4) URL : https://patchwork.freedesktop.org/series/66811/ State : warning == Summary == $ dim checkpatch origin/drm-tip a2941dc3f4c3 drm/i915/color: Fix formatting issues 07413db306f1 drm/i915/color: Extract icl_read_luts() -:33: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #33: -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA -:103: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #103: FILE: drivers/gpu/drm/i915/display/intel_color.c:1482: + +} total: 0 errors, 1 warnings, 1 checks, 215 lines checked 35a88c0ab404 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs -:18: WARNING:LONG_LINE: line over 100 characters #18: FILE: drivers/gpu/drm/i915/display/intel_color.c:1509: + DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green); total: 0 errors, 1 warnings, 0 checks, 8 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for adding gamma state checker for icl+ platforms (rev4) 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma ` (3 preceding siblings ...) 2019-09-22 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev4) Patchwork @ 2019-09-22 13:02 ` Patchwork 2019-09-23 1:51 ` ✓ Fi.CI.IGT: " Patchwork 2019-09-23 7:42 ` [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Jani Nikula 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2019-09-22 13:02 UTC (permalink / raw) To: Swati Sharma; +Cc: intel-gfx == Series Details == Series: adding gamma state checker for icl+ platforms (rev4) URL : https://patchwork.freedesktop.org/series/66811/ State : success == Summary == CI Bug Log - changes from CI_DRM_6934 -> Patchwork_14488 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/ Known issues ------------ Here are the changes found in Patchwork_14488 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@basic-flip-a: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-icl-u3/igt@kms_busy@basic-flip-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-icl-u3/igt@kms_busy@basic-flip-a.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html * igt@gem_mmap_gtt@basic-write: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html * igt@i915_module_load@reload: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-icl-u3/igt@i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-icl-u3/igt@i915_module_load@reload.html * igt@kms_busy@basic-flip-c: - fi-skl-6770hq: [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][11] ([fdo#109483]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html #### Warnings #### * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) -> [FAIL][16] ([fdo#111407]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (55 -> 45) ------------------------------ Missing (10): fi-ilk-m540 fi-icl-u4 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6934 -> Patchwork_14488 CI-20190529: 20190529 CI_DRM_6934: dd5bccfa3b5d8de4b5529db8145341c65930a710 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5196: 98783313b8b3097680df69007a9551c6248ab209 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14488: 35a88c0ab404cd8ee83962d4f2394be99dbfff61 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 35a88c0ab404 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs 07413db306f1 drm/i915/color: Extract icl_read_luts() a2941dc3f4c3 drm/i915/color: Fix formatting issues == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for adding gamma state checker for icl+ platforms (rev4) 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma ` (4 preceding siblings ...) 2019-09-22 13:02 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-09-23 1:51 ` Patchwork 2019-09-23 7:42 ` [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Jani Nikula 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2019-09-23 1:51 UTC (permalink / raw) To: Swati Sharma; +Cc: intel-gfx == Series Details == Series: adding gamma state checker for icl+ platforms (rev4) URL : https://patchwork.freedesktop.org/series/66811/ State : success == Summary == CI Bug Log - changes from CI_DRM_6934_full -> Patchwork_14488_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_14488_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-apl3/igt@gem_workarounds@suspend-resume-context.html * igt@kms_color@pipe-c-ctm-0-5: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108682]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl6/igt@kms_color@pipe-c-ctm-0-5.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl5/igt@kms_color@pipe-c-ctm-0-5.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#103355]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-stridechange: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#106978] / [fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +17 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-none: - shard-iclb: [SKIP][25] ([fdo#109276]) -> [PASS][26] +18 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html * igt@gem_eio@unwedge-stress: - shard-glk: [FAIL][27] ([fdo#109661]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-glk1/igt@gem_eio@unwedge-stress.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-glk1/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][29] ([fdo#110854]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb5/igt@gem_exec_balancer@smoke.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb4/igt@gem_exec_balancer@smoke.html * igt@gem_exec_reloc@basic-cpu-read-active: - shard-skl: [DMESG-WARN][31] ([fdo#106107]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl10/igt@gem_exec_reloc@basic-cpu-read-active.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl4/igt@gem_exec_reloc@basic-cpu-read-active.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [SKIP][33] ([fdo#111325]) -> [PASS][34] +4 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb3/igt@gem_exec_schedule@in-order-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][35] ([fdo#108686]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-apl1/igt@gem_tiled_swapping@non-threaded.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-apl8/igt@gem_tiled_swapping@non-threaded.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +8 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-apl7/igt@i915_suspend@sysfs-reader.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-apl3/igt@i915_suspend@sysfs-reader.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [INCOMPLETE][39] ([fdo#109507]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-skl8/igt@kms_flip@flip-vs-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-skl9/igt@kms_flip@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite: - shard-iclb: [FAIL][41] ([fdo#103167]) -> [PASS][42] +6 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][43] ([fdo#108566]) -> [PASS][44] +3 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb8/igt@kms_psr@psr2_sprite_render.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb2/igt@kms_psr@psr2_sprite_render.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [FAIL][47] ([fdo#111329]) -> [SKIP][48] ([fdo#109276]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html * igt@gem_mocs_settings@mocs-settings-bsd2: - shard-iclb: [FAIL][49] ([fdo#111330]) -> [SKIP][50] ([fdo#109276]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6934/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507 [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329 [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330 Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6934 -> Patchwork_14488 CI-20190529: 20190529 CI_DRM_6934: dd5bccfa3b5d8de4b5529db8145341c65930a710 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5196: 98783313b8b3097680df69007a9551c6248ab209 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14488: 35a88c0ab404cd8ee83962d4f2394be99dbfff61 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14488/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [v4][PATCH 0/3] adding gamma state checker for icl+ platforms 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma ` (5 preceding siblings ...) 2019-09-23 1:51 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-09-23 7:42 ` Jani Nikula 6 siblings, 0 replies; 13+ messages in thread From: Jani Nikula @ 2019-09-23 7:42 UTC (permalink / raw) To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal On Sun, 22 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > In this patch series, added state checker to validate gamma lut values > for icelake+ platforms. It's extension of the > patch series https://patchwork.freedesktop.org/patch/328246/?series=58039 > which enabled the basic infrastructure and state checker for > legacy platforms. > Major changes done in patch 2, details in commit message. Pushed, thanks for the patches. Please do follow-up with the remaining multi segmented issues. BR, Jani. > > Swati Sharma (3): > drm/i915/color: Fix formatting issues > drm/i915/color: Extract icl_read_luts() > FOR_TESTING_ONLY: Print rgb values of hw and sw blobs > > drivers/gpu/drm/i915/display/intel_color.c | 168 ++++++++++++++++++++++------- > drivers/gpu/drm/i915/i915_reg.h | 6 ++ > 2 files changed, 138 insertions(+), 36 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-09-25 5:43 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-09-21 20:10 [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma 2019-09-21 20:10 ` [v4][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma 2019-09-22 10:26 ` Jani Nikula 2019-09-23 5:29 ` Sharma, Swati2 2019-09-21 20:10 ` [v4][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma 2019-09-24 12:17 ` Jani Nikula 2019-09-24 14:28 ` Sharma, Swati2 2019-09-25 5:43 ` Saarinen, Jani 2019-09-21 20:10 ` [v4][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma 2019-09-22 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev4) Patchwork 2019-09-22 13:02 ` ✓ Fi.CI.BAT: success " Patchwork 2019-09-23 1:51 ` ✓ Fi.CI.IGT: " Patchwork 2019-09-23 7:42 ` [v4][PATCH 0/3] adding gamma state checker for icl+ platforms Jani Nikula
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