[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[Stafford Horne]

Hello,

As I am working on openrisc which uses cgen in binutils I have needed to make
these changes.

The Unordered compares is needed for FPU unordered (NaN detecting) comparisons.
These have been implemented and tested in OpenRISC (both simulation and
assembler (running on FPGA hardware)).

The gen-doc changes come from me noticing the docs [0] on the cgen website are
very much out of date.

Does anyone know the process to get the regenerated docs posted?  I think they
are beneficial and with some more updates they could be really good.

[0] https://sourceware.org/cgen/gen-doc/

Stafford Horne (2):
  cgen: Add unordered compare operation
  gen-doc: Updates for latest cpu definitions

 gen-all-doc   | 46 ++++++++++++++++++++++++++++++++--------------
 html.scm      |  2 +-
 rtl-c.scm     |  4 ++++
 rtx-funcs.scm |  7 +++++++
 4 files changed, 44 insertions(+), 15 deletions(-)
 mode change 100644 => 100755 gen-all-doc

-- 
2.21.0

[OpenRISC] [PATCH 1/2] cgen: Add unordered compare operation

[Stafford Horne]

On OpenRISC we have added FPU unordered comparison operations (NaN
detection).  This patch adds the unordered operation which will generate
c hooks to be implemented in simulators.

An unordered comparison can now be defined as:

  ; Compare unordered (set flag if either r1 or r2 is NaN)
  (set BI flag (unordered WI r1 r2))

  ; Compare unordered, greater than or equal
  (set BI flag (or (unordered WI r1 r2)
		   (ge WI r1 r2)))

ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* rtl-c.scm (unordered): New comparison operation.
	* rtx-funcs.scm (unordered): New rtx node.
---
 rtl-c.scm     | 4 ++++
 rtx-funcs.scm | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/rtl-c.scm b/rtl-c.scm
index 1a4b8b0..4d4d671 100644
--- a/rtl-c.scm
+++ b/rtl-c.scm
@@ -1897,6 +1897,10 @@
 (define-fn geu (*estate* options mode s1 s2)
   (s-cmpop *estate* 'geu ">=" mode s1 s2)
 )
+(define-fn unordered (*estate* options mode s1 s2)
+  (s-cmpop *estate* 'unordered #f mode s1 s2)
+)
+
 
 (define-fn member (*estate* options mode value set)
   ;; NOTE: There are multiple evalutions of VALUE in the generated code.
diff --git a/rtx-funcs.scm b/rtx-funcs.scm
index 6c28735..f16864a 100644
--- a/rtx-funcs.scm
+++ b/rtx-funcs.scm
@@ -1086,6 +1086,13 @@
      COMPARE
      #f
 )
+; Detect NaNs
+(drn (unordered &options &mode s1 s2)
+     BI
+     (OPTIONS ANYNUMMODE RTX RTX) (NA NA MATCHEXPR MATCH2)
+     COMPARE
+     #f
+)
 \f
 ; Set membership.
 ; Useful in ifield assertions.
-- 
2.21.0

[OpenRISC] [PATCH 2/2] gen-doc: Updates for latest cpu definitions

[Stafford Horne]

Doc generation was no longer working due to several issues.

 - openrisc.cpu no longer exists (its not cpu/or1k.cpu in binutils-gdb)
 - Relavive paths for archfile no longer work due to wrong cwd.
 - Many architectures have been added and removed.

I have be able to get this working and added all the architectures I
could get working with the below changes. I have posted the results
here:

  http://shorne.noip.me/downloads/gen-doc/

ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* gen-all-doc (archs): Add new archs and update locations.
	(archfile): Prepend cgendir.
	(index.html gen): Change name openrisc to or1k.
	* html.scm (gen-html-trailer): Change redhat.com to
	sourceware.org.
---
 gen-all-doc | 46 ++++++++++++++++++++++++++++++++--------------
 html.scm    |  2 +-
 2 files changed, 33 insertions(+), 15 deletions(-)
 mode change 100644 => 100755 gen-all-doc

diff --git a/gen-all-doc b/gen-all-doc
old mode 100644
new mode 100755
index e2a49b6..5db3200
--- a/gen-all-doc
+++ b/gen-all-doc
@@ -18,7 +18,7 @@
 # <http://www.gnu.org/licenses/>.
 #
 
-# Run this script in the src/cgen directory.
+# Run this script in the binutils-gdb/cgen directory.
 
 # Exit on any error.
 set -e
@@ -26,28 +26,46 @@ set -e
 # For debugging.
 set -x
 
-# ??? Some are missing, need to add them after some research.
-#../cpu/m32c.cpu
-#../cpu/xc16x.cpu
+# ??? Broken archs not in list, grouped by error
+# h-prefixreg error
+#../cpu/cris.cpu
+# Error: unexpected operand: #f
+# ../cpu/m32c.cpu
+# ../cpu/xc16x.cpu
+# cpu/ia32.cpu
+# sh64-compact.cpu:316:3: Error: Instruction has opcode bits outside of its mask
+# ../cpu/sh.cpu
+# ia64.cpu:924:invalid argument to %sym: (if (eq? (string-length "") 0) "" ".")
+# ../cpu/ia64.cpu
+# sparc.cpu:389:1: define-hardware: hardware already defined: h-gr
+# cpu/sparc.cpu
+
+# Archs in parent directly should be from the binutils-gdb project. Others are
+# hosted here in cgen.
+
 archs="
-cpu/fr30.cpu
-cpu/arm.cpu
+../cpu/epiphany.cpu
+../cpu/fr30.cpu
 ../cpu/frv.cpu
-cpu/i960.cpu
-cpu/ip2k.cpu
+../cpu/ip2k.cpu
 ../cpu/iq2000.cpu
 ../cpu/lm32.cpu
 ../cpu/m32r.cpu
-cpu/mep.cpu
+../cpu/mep.cpu
 ../cpu/mt.cpu
-cpu/openrisc.cpu
+../cpu/or1k.cpu
+../cpu/xstormy16.cpu
+cpu/arm.cpu
+cpu/i960.cpu
+cpu/m68k.cpu
+cpu/play.cpu
+cpu/powerpc.cpu
 cpu/sh.cpu
-cpu/xstormy16.cpu
 "
 
 if [ ! -f sim.scm ]
 then
-    echo "Not in the src/cgen directory." >& 2
+    echo "Not in the cgen source directory." >& 2
     exit 1
 fi
 
@@ -66,7 +84,7 @@ export cgendir=`pwd`
 
   for a in $archs
   do
-    archfile=../$a
+    archfile=$cgendir/$a
     arch=$(basename $archfile .cpu)
 
     case $arch in
@@ -129,7 +147,7 @@ EOF
     arm-thumb.*) name="ARM Thumb" ;;
     frv-1.*) name="FRV FR400" ;;
     frv-2.*) name="FRV FR500" ;;
-    openrisc.*) name="Openrisc" ;;
+    or1k.*) name="OpenRISC" ;;
     xstormy16.*) name="Xstormy16" ;;
     *) name=`echo ${html/.html} | tr $lower $upper` ;;
     esac
diff --git a/html.scm b/html.scm
index 3d6bb4a..0a57a73 100644
--- a/html.scm
+++ b/html.scm
@@ -111,7 +111,7 @@ See the input .cpu file(s) for copyright information.
    "This documentation was machine generated from the cgen cpu description\n"
    "files for this architecture.\n"
    "<br>\n"
-   "<a href=\"http://sources.redhat.com/cgen/\">http://sources.redhat.com/cgen/</a>\n"
+   "<a href=\"https://sourceware.org/cgen/\">https://sourceware.org/cgen/</a>\n"
    "</body>\n"
    "</html>\n"
    )
-- 
2.21.0

[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[Stafford Horne]

Hello,

Did anyone have a chance to look at this?  The binutils patches that require
this are approved, but I rather not commit them unless this I get OK on these
patches and push them.

-Stafford

On Sat, Jun 01, 2019 at 04:26:27PM +0900, Stafford Horne wrote:
> Hello,
> 
> As I am working on openrisc which uses cgen in binutils I have needed to make
> these changes.
> 
> The Unordered compares is needed for FPU unordered (NaN detecting) comparisons.
> These have been implemented and tested in OpenRISC (both simulation and
> assembler (running on FPGA hardware)).
> 
> The gen-doc changes come from me noticing the docs [0] on the cgen website are
> very much out of date.
> 
> Does anyone know the process to get the regenerated docs posted?  I think they
> are beneficial and with some more updates they could be really good.
> 
> [0] https://sourceware.org/cgen/gen-doc/
> 
> Stafford Horne (2):
>   cgen: Add unordered compare operation
>   gen-doc: Updates for latest cpu definitions
> 
>  gen-all-doc   | 46 ++++++++++++++++++++++++++++++++--------------
>  html.scm      |  2 +-
>  rtl-c.scm     |  4 ++++
>  rtx-funcs.scm |  7 +++++++
>  4 files changed, 44 insertions(+), 15 deletions(-)
>  mode change 100644 => 100755 gen-all-doc
> 
> -- 
> 2.21.0
> 

[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[Jose E. Marchesi]

    
    Did anyone have a chance to look at this?  The binutils patches that require
    this are approved, but I rather not commit them unless this I get OK on these
    patches and push them.

I'm not a CGEN maintainer, but FWIW both patches look good to me.

[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[Frank Ch. Eigler]

Hi -

> Did anyone have a chance to look at this?  The binutils patches that require
> this are approved, but I rather not commit them unless this I get OK on these
> patches and push them.

These are merged, thanks.

- FChE

[OpenRISC] [PATCH 0/2] CGEN unordered fpu compares + fixes

[Stafford Horne]

On Wed, Jun 12, 2019 at 11:04:40AM -0400, Frank Ch. Eigler wrote:
> Hi -
> 
> > Did anyone have a chance to look at this?  The binutils patches that require
> > this are approved, but I rather not commit them unless this I get OK on these
> > patches and push them.
> 
> These are merged, thanks.

Thanks,

Note, I noticed the changelog was not updated.  I usually do that as part of the
final phase up pushing the changes to git.

Or did we stop maintaining the change log when moving to git (I would have no
problem with that myself ;) )?

-Stafford