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From: Jani Nikula <jani.nikula@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Introduce BITS_PER_TYPE
Date: Fri, 06 Jul 2018 12:07:32 +0300	[thread overview]
Message-ID: <878t6oohpn.fsf@intel.com> (raw)
In-Reply-To: <20180706084455.23601-1-chris@chris-wilson.co.uk>

On Fri, 06 Jul 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Borrow the idea from net_dim.h to simplify the common determination of
> how many bits in a particular type (sizeof(type) * BITS_PER_BYTE).

Nice. Follow-up, have that included in bitops.h?

BR,
Jani.

>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c          | 4 ++--
>  drivers/gpu/drm/i915/i915_gem.c          | 2 +-
>  drivers/gpu/drm/i915/i915_query.c        | 2 +-
>  drivers/gpu/drm/i915/i915_syncmap.c      | 3 ++-
>  drivers/gpu/drm/i915/i915_utils.h        | 4 +++-
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +--
>  drivers/gpu/drm/i915/intel_engine_cs.c   | 2 +-
>  7 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0db3c83cce29..248c7db2ae2a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -887,8 +887,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
>  	device_info->device_id = dev_priv->drm.pdev->device;
>  
>  	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> -		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
> -	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
> +		     BITS_PER_TYPE(device_info->platform_mask));
> +	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>  	spin_lock_init(&dev_priv->irq_lock);
>  	spin_lock_init(&dev_priv->gpu_error.lock);
>  	mutex_init(&dev_priv->backlight_lock);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0c0a1a959d0b..0dc9caaa1dc9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5880,7 +5880,7 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
>  	 * the bits.
>  	 */
>  	BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
> -		     sizeof(atomic_t) * BITS_PER_BYTE);
> +		     BITS_PER_TYPE(atomic_t));
>  
>  	if (old) {
>  		WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 3f502eef2431..5821002cad42 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -28,7 +28,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>  	slice_length = sizeof(sseu->slice_mask);
>  	subslice_length = sseu->max_slices *
>  		DIV_ROUND_UP(sseu->max_subslices,
> -			     sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
> +			     BITS_PER_TYPE(sseu->subslice_mask[0]));
>  	eu_length = sseu->max_slices * sseu->max_subslices *
>  		DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
>  
> diff --git a/drivers/gpu/drm/i915/i915_syncmap.c b/drivers/gpu/drm/i915/i915_syncmap.c
> index 58f8d0cc125c..1741db6fb0ce 100644
> --- a/drivers/gpu/drm/i915/i915_syncmap.c
> +++ b/drivers/gpu/drm/i915/i915_syncmap.c
> @@ -28,6 +28,7 @@
>  
>  #include "i915_gem.h" /* GEM_BUG_ON() */
>  #include "i915_selftest.h"
> +#include "i915_utils.h" /* BITS_PER_TYPE() */
>  
>  #define SHIFT ilog2(KSYNCMAP)
>  #define MASK (KSYNCMAP - 1)
> @@ -92,7 +93,7 @@ void i915_syncmap_init(struct i915_syncmap **root)
>  {
>  	BUILD_BUG_ON_NOT_POWER_OF_2(KSYNCMAP);
>  	BUILD_BUG_ON_NOT_POWER_OF_2(SHIFT);
> -	BUILD_BUG_ON(KSYNCMAP > BITS_PER_BYTE * sizeof((*root)->bitmap));
> +	BUILD_BUG_ON(KSYNCMAP > BITS_PER_TYPE((*root)->bitmap));
>  	*root = NULL;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
> index 00165ad55fb3..617f02737fdf 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -43,6 +43,8 @@
>  #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>  			     __stringify(x), (long)(x))
>  
> +#define BITS_PER_TYPE(T) (sizeof(T) * BITS_PER_BYTE)
> +
>  #if GCC_VERSION >= 70000
>  #define add_overflows(A, B) \
>  	__builtin_add_overflow_p((A), (B), (typeof((A) + (B)))0)
> @@ -68,7 +70,7 @@
>  
>  /* Note we don't consider signbits :| */
>  #define overflows_type(x, T) \
> -	(sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
> +	(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
>  
>  #define ptr_mask_bits(ptr, n) ({					\
>  	unsigned long __v = (unsigned long)(ptr);			\
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 0fd13df424cf..1422758a4d36 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -750,8 +750,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		info->num_scalers[PIPE_C] = 1;
>  	}
>  
> -	BUILD_BUG_ON(I915_NUM_ENGINES >
> -		     sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
> +	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>  
>  	/*
>  	 * Skylake and Broxton currently don't expose the topmost plane as its
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 478c928912c4..b459a0819569 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -333,7 +333,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
>  
>  	WARN_ON(ring_mask == 0);
>  	WARN_ON(ring_mask &
> -		GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
> +		GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
>  
>  	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
>  		if (!HAS_ENGINE(dev_priv, i))

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-07-06  9:07 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-06  8:44 [PATCH] drm/i915: Introduce BITS_PER_TYPE Chris Wilson
2018-07-06  8:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-07-06  8:59 ` [PATCH] " Tvrtko Ursulin
2018-07-06  9:07 ` Jani Nikula [this message]
2018-07-06  9:10 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-07-07  0:59 ` ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-09-26 10:47 [PATCH] " Chris Wilson
2018-09-26 10:58 ` Jani Nikula
2018-09-26 10:59 ` Ville Syrjälä

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