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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <mwalle@kernel.org>,
	 Takahiro Kuwano <takahiro.kuwano@infineon.com>,
	Mark Brown <broonie@kernel.org>,
	 Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	 linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	 linux-mtd@lists.infradead.org
Subject: Re: [PATCH v2 2/5] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode
Date: Wed, 28 Oct 2026 17:39:32 +0100	[thread overview]
Message-ID: <87a4nxg4or.fsf@bootlin.com> (raw)
In-Reply-To: <20261028121100.79667-3-changhuang.liang@starfivetech.com> (Changhuang Liang's message of "Wed, 28 Oct 2026 05:10:57 -0700")

On 28/10/2026 at 05:10:57 -07, Changhuang Liang <changhuang.liang@starfivetech.com> wrote:

> Add support for 1S-xD-xD DDR transfers in the enhanced SPI mode of the
> DW SPI controller, on controllers that have DW_SPI_CAP_DDR.
>
> SPI_CTRLR0.SPI_DDR_EN switches the address, dummy and data phases to
> DDR all together, and it only applies to the Dual/Quad/Octal frame
> formats. So in supports_op() only accept DTR operations where the
> command is sent in STR on one line, the data phase uses two lines or
> more, and the address and dummy phases are DTR on the data lines.
> DDR instruction phase (8D-8D-8D) is not supported for now.
>
> For DDR transfers the dummy phase takes two bits per clock on each
> line, so the wait cycles must be halved. Factor the wait cycle
> calculation into dw_spi_enh_wait_cycles(), so that supports_op() and
> exec_op() use the same value, and refuse dummy phases that are not a
> whole number of clock cycles.
>
> When DDR is enabled, program the DDR_DRIVE_EDGE register. The
> recommended TDE value is SCKDV / 4, clamped to SCKDV / 2 - 1 and to
> the field width. The register is only written when the controller
> supports DDR.
>
> Finally, advertise DTR to the spi-mem layer through a dedicated
> dw_spi_ddr_mem_caps when the controller has DW_SPI_CAP_DDR.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>

Looks correct to me.

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <mwalle@kernel.org>,
	 Takahiro Kuwano <takahiro.kuwano@infineon.com>,
	Mark Brown <broonie@kernel.org>,
	 Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	 linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	 linux-mtd@lists.infradead.org
Subject: Re: [PATCH v2 2/5] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode
Date: Wed, 28 Oct 2026 17:39:32 +0100	[thread overview]
Message-ID: <87a4nxg4or.fsf@bootlin.com> (raw)
In-Reply-To: <20261028121100.79667-3-changhuang.liang@starfivetech.com> (Changhuang Liang's message of "Wed, 28 Oct 2026 05:10:57 -0700")

On 28/10/2026 at 05:10:57 -07, Changhuang Liang <changhuang.liang@starfivetech.com> wrote:

> Add support for 1S-xD-xD DDR transfers in the enhanced SPI mode of the
> DW SPI controller, on controllers that have DW_SPI_CAP_DDR.
>
> SPI_CTRLR0.SPI_DDR_EN switches the address, dummy and data phases to
> DDR all together, and it only applies to the Dual/Quad/Octal frame
> formats. So in supports_op() only accept DTR operations where the
> command is sent in STR on one line, the data phase uses two lines or
> more, and the address and dummy phases are DTR on the data lines.
> DDR instruction phase (8D-8D-8D) is not supported for now.
>
> For DDR transfers the dummy phase takes two bits per clock on each
> line, so the wait cycles must be halved. Factor the wait cycle
> calculation into dw_spi_enh_wait_cycles(), so that supports_op() and
> exec_op() use the same value, and refuse dummy phases that are not a
> whole number of clock cycles.
>
> When DDR is enabled, program the DDR_DRIVE_EDGE register. The
> recommended TDE value is SCKDV / 4, clamped to SCKDV / 2 - 1 and to
> the field width. The register is only written when the controller
> supports DDR.
>
> Finally, advertise DTR to the spi-mem layer through a dedicated
> dw_spi_ddr_mem_caps when the controller has DW_SPI_CAP_DDR.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>

Looks correct to me.

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

  reply	other threads:[~2026-10-28 16:39 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-28 12:10 [PATCH v2 0/5] Add DDR (Dual Data-Rate) support for DW SPI controller Changhuang Liang
2026-10-28 12:10 ` Changhuang Liang
2026-10-28 12:10 ` [PATCH v2 1/5] spi: dw: Detect DDR support in enhanced SPI mode Changhuang Liang
2026-10-28 12:10   ` Changhuang Liang
2026-10-28 12:10 ` [PATCH v2 2/5] spi: dw: Add DDR (Dual Data-Rate) support for " Changhuang Liang
2026-10-28 12:10   ` Changhuang Liang
2026-10-28 16:39   ` Miquel Raynal [this message]
2026-10-28 16:39     ` Miquel Raynal
2026-10-28 12:10 ` [PATCH v2 3/5] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Changhuang Liang
2026-10-28 12:10   ` Changhuang Liang
2026-10-28 12:10 ` [PATCH v2 4/5] mtd: spi-nor: debugfs: Correct DTR protocol names for 1S-xD-xD modes Changhuang Liang
2026-10-28 12:10   ` Changhuang Liang
2026-10-28 12:11 ` [PATCH v2 5/5] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G Changhuang Liang
2026-10-28 12:11   ` Changhuang Liang

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