From: Thomas Gleixner <tglx@kernel.org>
To: Icenowy Zheng <zhengxingda@iscas.ac.cn>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Huacai Chen <chenhuacai@kernel.org>,
WANG Xuerui <kernel@xen0n.name>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Icenowy Zheng <uwu@icenowy.me>, Yao Zi <me@ziyao.cc>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
loongarch@lists.linux.dev, linux-mips@vger.kernel.org,
Icenowy Zheng <zhengxingda@iscas.ac.cn>
Subject: Re: [PATCH v3 1/8] MIPS: Loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
Date: Fri, 20 Mar 2026 10:09:10 +0100 [thread overview]
Message-ID: <87a4w2lvex.ffs@tglx> (raw)
In-Reply-To: <20260314162828.1055188-2-zhengxingda@iscas.ac.cn>
On Sun, Mar 15 2026 at 00:28, Icenowy Zheng wrote:
> On some Loongson 3A devices, a LPC bus is present and some legacy
> devices (e.g. 8259) on it expect hardcoded low IRQ numbers. However
s/IRQ/interrupt/ all over the place
Change log are supposed to be written in proper prose and not be riddled
with acronyms unless the acronym has a technical relevance like LPC or
ACPI. IRQ[s] does not qualify for that.
Thanks,
tglx
next prev parent reply other threads:[~2026-03-20 9:09 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-14 16:28 [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 1/8] MIPS: Loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs Icenowy Zheng
2026-03-20 9:09 ` Thomas Gleixner [this message]
2026-03-14 16:28 ` [PATCH v3 2/8] LoongArch: " Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 3/8] dt-bindings: interrupt-controller: add LS7A PCH LPC Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 4/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-03-20 9:15 ` Thomas Gleixner
2026-03-14 16:28 ` [PATCH v3 5/8] irqchip/loongson-pch-lpc: add OF init code Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64 Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 7/8] MIPS: Loongson64: dts: sort nodes Icenowy Zheng
2026-03-14 16:28 ` [PATCH v3 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC Icenowy Zheng
2026-03-18 13:57 ` [PATCH v3 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Huacai Chen
2026-03-20 9:16 ` Thomas Gleixner
2026-03-21 9:15 ` Icenowy Zheng
2026-03-21 8:59 ` Icenowy Zheng
2026-03-21 17:14 ` Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87a4w2lvex.ffs@tglx \
--to=tglx@kernel.org \
--cc=chenhuacai@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=kernel@xen0n.name \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=loongarch@lists.linux.dev \
--cc=me@ziyao.cc \
--cc=robh@kernel.org \
--cc=tsbogend@alpha.franken.de \
--cc=uwu@icenowy.me \
--cc=zhengxingda@iscas.ac.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.