From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Mark Brown" <broonie@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Vaishnav Achath" <vaishnav.a@ti.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Hervé Codina" <herve.codina@bootlin.com>,
"Wolfram Sang" <wsa+renesas@sang-engineering.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Santhosh Kumar K" <s-k6@ti.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
"Pascal Eberhard" <pascal.eberhard@se.com>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2 13/13] ARM: dts: r9a06g032: Describe the QSPI controller
Date: Fri, 16 Jan 2026 16:19:12 +0100 [thread overview]
Message-ID: <87a4ydtwjz.fsf@bootlin.com> (raw)
In-Reply-To: <CAMuHMdUqWUriQHR8UY631HZfVNsejgXE64jrChi=k2=5E6Hi-Q@mail.gmail.com> (Geert Uytterhoeven's message of "Fri, 16 Jan 2026 11:07:03 +0100")
On 16/01/2026 at 11:07:03 +01, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Miquel,
>
> On Fri, 16 Jan 2026 at 10:49, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>> >> + qspi0: spi@40005000 {
>> >> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
>> >> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
>> >> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> >> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
>> >> + <&sysctrl R9A06G032_HCLK_QSPI0>;
>> >> + clock-names = "ref", "ahb", "apb";
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> + cdns,fifo-width = <4>;
>> >
>> > <4> is the default, right?
>>
>> It is the default in the bindings indeed, however the driver does not
>> imply that default and errors out if the property is missing. The
>> property is also marked required in the bindings, which is kind of
>> incorrect I guess. Also, all DTS explicitly set this value to 4.
>
> OK.
>
>>
>> However looking into the RM I found "Transmit and receive FIFOs are 16
>> bytes". I haven't tested that, I will.
>
> Oh, that bullet is not present in the docs on the CD I looked at.
> It is indeed documented in newer versions.
>
> There's also cdns,fifo-depth, which thus should be 4?
Ah, that's right. You mean fifo-width = 4 and fifo-depth = 4, right?
It is marked as being discoverable by reading CQSPI_REG_SRAMPARTITION,
but on my board this register returns 0. So I guess yes, I will go for
fifo-depth = 4 and we should be fine.
...
>> > The rest LGTM, ignoring my comments on the bindings:
>> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>> Thanks for the review, but I guess if I end up changing the DTS snippet
>> I might drop it. Or would you like me to keep it anyway?
>
> Please keep it as long as you don't change the (SoC integration)
> things I typically focus on (address, interrupts, clocks), and don't make
> too wild changes ;-)
Thanks,
Miquèl
next prev parent reply other threads:[~2026-01-16 15:19 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-15 9:24 [PATCH v2 00/13] spi: cadence-qspi: Add Renesas RZ/N1 support Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 01/13] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Miquel Raynal (Schneider Electric)
2026-01-15 12:45 ` Geert Uytterhoeven
2026-01-16 9:39 ` Miquel Raynal
2026-01-21 2:40 ` Rob Herring
2026-01-21 10:39 ` Miquel Raynal
2026-01-15 9:24 ` [PATCH v2 02/13] spi: cadence-qspi: Align definitions Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 03/13] spi: cadence-qspi: Fix style and improve readability Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 04/13] spi: cadence-qspi: Fix ORing style and alignments Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 05/13] spi: cadence-qspi: Remove an useless operation Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 06/13] spi: cadence-qspi: Make sure we filter out unsupported ops Miquel Raynal
2026-01-15 9:24 ` [PATCH v2 07/13] spi: cadence-qspi: Fix probe error path and remove Miquel Raynal (Schneider Electric)
2026-01-15 9:24 ` [PATCH v2 08/13] spi: cadence-qspi: Try hard to disable the clocks Miquel Raynal (Schneider Electric)
2026-01-15 9:25 ` [PATCH v2 09/13] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Miquel Raynal (Schneider Electric)
2026-01-15 9:25 ` [PATCH v2 10/13] spi: cadence-qspi: Add a flag for controllers without indirect access support Miquel Raynal (Schneider Electric)
2026-01-15 9:25 ` [PATCH v2 11/13] spi: cadence-qspi: Make sure write protection is disabled Miquel Raynal (Schneider Electric)
2026-01-15 9:25 ` [PATCH v2 12/13] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller Miquel Raynal (Schneider Electric)
2026-01-15 9:25 ` [PATCH v2 13/13] ARM: dts: r9a06g032: Describe the QSPI controller Miquel Raynal (Schneider Electric)
2026-01-15 13:00 ` Geert Uytterhoeven
2026-01-16 9:49 ` Miquel Raynal
2026-01-16 10:07 ` Geert Uytterhoeven
2026-01-16 15:19 ` Miquel Raynal [this message]
2026-01-21 17:03 ` Miquel Raynal
2026-01-16 11:26 ` [PATCH v2 00/13] spi: cadence-qspi: Add Renesas RZ/N1 support Wolfram Sang
2026-01-20 9:22 ` Santhosh Kumar K
2026-01-20 15:05 ` Miquel Raynal
2026-01-21 10:37 ` Miquel Raynal
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