From: Frank Oltmanns <frank@oltmanns.dev>
To: Maxime Ripard <maxime@cerno.tech>
Cc: jagan@amarulasolutions.com, michael@amarulasolutions.com,
Chen-Yu Tsai <wens@csie.org>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
"open list:DRM DRIVERS FOR ALLWINNER A10"
<dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Allwinner sunXi SoC support"
<linux-arm-kernel@lists.infradead.org>,
"open list:ARM/Allwinner sunXi SoC support"
<linux-sunxi@lists.linux.dev>,
open list <linux-kernel@vger.kernel.org>,
Roman Beranek <romanberanek@icloud.com>
Subject: Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI
Date: Tue, 21 Mar 2023 20:55:32 +0100 [thread overview]
Message-ID: <87a605hmo5.fsf@oltmanns.dev> (raw)
In-Reply-To: <20230321145739.jlpbzplsc27dlh7v@houat>
[-- Attachment #1: Type: text/plain, Size: 1207 bytes --]
Hi Maxime,
On 2023-03-21 at 15:57:39 +0100, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi,
>
> On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
>> Set the required PLL rate by adjusting the dotclock rate when calling
>> clk_set_rate() when using DSI.
>>
>> According to the Allwinners A64’s BSP code, a TCON divider of 4 has to
>> be used and the PLL rate needs to be set to the following frequency when
>> using DSI:
>> PLL rate = DCLK * bpp / lanes
>>
>> After this change the common mode set function would only contain
>> setting the resolution. Therefore, dissolve the function and transfer
>> the functionality to the individual mode set functions.
>>
>> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
>
> This is similar to:
> <https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/>
>
> What’s the story there?
Sorry, as Roman wrote in the other thread, I submitted the patch after not hearing back from him for a week. My apologies, I wasn’t patient enough. So now there are two submissions to consider. FWIW, I think this patch is a bit more straightforward than the other one.
Best regards,
Frank
> Maxime
>
WARNING: multiple messages have this Message-ID (diff)
From: Frank Oltmanns <frank@oltmanns.dev>
To: Maxime Ripard <maxime@cerno.tech>
Cc: jagan@amarulasolutions.com, michael@amarulasolutions.com,
Chen-Yu Tsai <wens@csie.org>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
"open list:DRM DRIVERS FOR ALLWINNER A10"
<dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Allwinner sunXi SoC support"
<linux-arm-kernel@lists.infradead.org>,
"open list:ARM/Allwinner sunXi SoC support"
<linux-sunxi@lists.linux.dev>,
open list <linux-kernel@vger.kernel.org>,
Roman Beranek <romanberanek@icloud.com>
Subject: Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI
Date: Tue, 21 Mar 2023 20:55:32 +0100 [thread overview]
Message-ID: <87a605hmo5.fsf@oltmanns.dev> (raw)
In-Reply-To: <20230321145739.jlpbzplsc27dlh7v@houat>
[-- Attachment #1: Type: text/plain, Size: 1207 bytes --]
Hi Maxime,
On 2023-03-21 at 15:57:39 +0100, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi,
>
> On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
>> Set the required PLL rate by adjusting the dotclock rate when calling
>> clk_set_rate() when using DSI.
>>
>> According to the Allwinners A64’s BSP code, a TCON divider of 4 has to
>> be used and the PLL rate needs to be set to the following frequency when
>> using DSI:
>> PLL rate = DCLK * bpp / lanes
>>
>> After this change the common mode set function would only contain
>> setting the resolution. Therefore, dissolve the function and transfer
>> the functionality to the individual mode set functions.
>>
>> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
>
> This is similar to:
> <https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/>
>
> What’s the story there?
Sorry, as Roman wrote in the other thread, I submitted the patch after not hearing back from him for a week. My apologies, I wasn’t patient enough. So now there are two submissions to consider. FWIW, I think this patch is a bit more straightforward than the other one.
Best regards,
Frank
> Maxime
>
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Frank Oltmanns <frank@oltmanns.dev>
To: Maxime Ripard <maxime@cerno.tech>
Cc: Samuel Holland <samuel@sholland.org>,
"open list:DRM DRIVERS FOR ALLWINNER A10"
<dri-devel@lists.freedesktop.org>,
open list <linux-kernel@vger.kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Roman Beranek <romanberanek@icloud.com>,
Chen-Yu Tsai <wens@csie.org>,
jagan@amarulasolutions.com, michael@amarulasolutions.com,
"open list:ARM/Allwinner sunXi SoC support"
<linux-sunxi@lists.linux.dev>,
"moderated list:ARM/Allwinner sunXi SoC support"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI
Date: Tue, 21 Mar 2023 20:55:32 +0100 [thread overview]
Message-ID: <87a605hmo5.fsf@oltmanns.dev> (raw)
In-Reply-To: <20230321145739.jlpbzplsc27dlh7v@houat>
[-- Attachment #1: Type: text/plain, Size: 1207 bytes --]
Hi Maxime,
On 2023-03-21 at 15:57:39 +0100, Maxime Ripard <maxime@cerno.tech> wrote:
> Hi,
>
> On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
>> Set the required PLL rate by adjusting the dotclock rate when calling
>> clk_set_rate() when using DSI.
>>
>> According to the Allwinners A64’s BSP code, a TCON divider of 4 has to
>> be used and the PLL rate needs to be set to the following frequency when
>> using DSI:
>> PLL rate = DCLK * bpp / lanes
>>
>> After this change the common mode set function would only contain
>> setting the resolution. Therefore, dissolve the function and transfer
>> the functionality to the individual mode set functions.
>>
>> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
>
> This is similar to:
> <https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/>
>
> What’s the story there?
Sorry, as Roman wrote in the other thread, I submitted the patch after not hearing back from him for a week. My apologies, I wasn’t patient enough. So now there are two submissions to consider. FWIW, I think this patch is a bit more straightforward than the other one.
Best regards,
Frank
> Maxime
>
next prev parent reply other threads:[~2023-03-21 20:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-19 16:07 [PATCH 0/1] Fixing the DSI dot clock on Allwinner Frank Oltmanns
2023-03-19 16:07 ` Frank Oltmanns
2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns
2023-03-19 16:07 ` Frank Oltmanns
2023-03-21 14:57 ` Maxime Ripard
2023-03-21 14:57 ` Maxime Ripard
2023-03-21 14:57 ` Maxime Ripard
2023-03-21 19:55 ` Frank Oltmanns [this message]
2023-03-21 19:55 ` Frank Oltmanns
2023-03-21 19:55 ` Frank Oltmanns
2023-03-22 3:25 ` Roman Beranek
2023-03-22 3:25 ` Roman Beranek
2023-03-22 3:25 ` Roman Beranek
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