From: Marc Zyngier <maz@kernel.org>
To: Joey Gouly <joey.gouly@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>, <nd@arm.com>,
<alexandru.elisei@arm.com>, <catalin.marinas@arm.com>,
<corbet@lwn.net>, <james.morse@arm.com>, <reijiw@google.com>,
<suzuki.poulose@arm.com>, <will@kernel.org>
Subject: Re: [PATCH v1 2/3] arm64: add ID_AA64ISAR2_EL1 sys register
Date: Wed, 01 Dec 2021 16:23:26 +0000 [thread overview]
Message-ID: <87a6hkmgzl.wl-maz@kernel.org> (raw)
In-Reply-To: <20211201120558.9140-3-joey.gouly@arm.com>
On Wed, 01 Dec 2021 12:05:57 +0000,
Joey Gouly <joey.gouly@arm.com> wrote:
>
> This is a new ID register, introduced in 8.7.
>
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Alexandru Elisei <alexandru.elisei@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Reiji Watanabe <reijiw@google.com>
> ---
> arch/arm64/include/asm/cpu.h | 1 +
> arch/arm64/include/asm/sysreg.h | 10 ++++++++++
> arch/arm64/kernel/cpufeature.c | 9 +++++++++
> arch/arm64/kernel/cpuinfo.c | 1 +
> arch/arm64/kvm/sys_regs.c | 2 +-
> 5 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 0f6d16faa540..a58e366f0b07 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -51,6 +51,7 @@ struct cpuinfo_arm64 {
> u64 reg_id_aa64dfr1;
> u64 reg_id_aa64isar0;
> u64 reg_id_aa64isar1;
> + u64 reg_id_aa64isar2;
> u64 reg_id_aa64mmfr0;
> u64 reg_id_aa64mmfr1;
> u64 reg_id_aa64mmfr2;
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index adcab9009f9d..b4470b0eba69 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -182,6 +182,7 @@
>
> #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
> #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
> +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
>
> #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
> #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
> @@ -771,6 +772,15 @@
> #define ID_AA64ISAR1_GPI_NI 0x0
> #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
>
> +/* id_aa64isar2 */
> +#define ID_AA64ISAR2_RPRES_SHIFT 4
> +#define ID_AA64ISAR2_WFXT_SHIFT 0
> +
> +#define ID_AA64ISAR2_RPRES_8BIT 0x0
> +#define ID_AA64ISAR2_RPRES_12BIT 0x1
> +#define ID_AA64ISAR2_WFXT_NI 0x0
> +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x1
Could you also document the "fixed" version of WFxT (aka FEAT_WFxT2),
where the register number is reported in ESR_EL2 when trapping?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2021-12-01 16:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 12:05 [PATCH v1 0/3] arm64: Add two HWCAPs for Arm v8.7 FP behaviour Joey Gouly
2021-12-01 12:05 ` [PATCH v1 1/3] arm64: cpufeature: add HWCAP for FEAT_AFP Joey Gouly
2021-12-01 12:05 ` [PATCH v1 2/3] arm64: add ID_AA64ISAR2_EL1 sys register Joey Gouly
2021-12-01 16:23 ` Marc Zyngier [this message]
2021-12-01 12:05 ` [PATCH v1 3/3] arm64: cpufeature: add HWCAP for FEAT_RPRES Joey Gouly
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