From: "Keith Packard" <keithp@keithp.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Laurent Vivier <laurent@vivier.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] riscv: Add semihosting support [v8]
Date: Mon, 26 Oct 2020 14:06:20 -0700 [thread overview]
Message-ID: <87a6w8hf3n.fsf@keithp.com> (raw)
In-Reply-To: <32eb3f3a-1256-ac68-c2ad-e887269ee796@linaro.org>
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Richard Henderson <richard.henderson@linaro.org> writes:
> This is no different to EXCP_DEBUG, really, which is also internal to qemu but
> user-visible in the same way. Just adjust the logging in riscv_cpu_do_interrupt.
I think that's already handled by the early return in
riscv_cpu_do_interrupt after handling the RISCV_EXCP_SEMIHOST case.
--
-keith
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WARNING: multiple messages have this Message-ID (diff)
From: "Keith Packard" via <qemu-devel@nongnu.org>
To: Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Laurent Vivier <laurent@vivier.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] riscv: Add semihosting support [v8]
Date: Mon, 26 Oct 2020 14:06:20 -0700 [thread overview]
Message-ID: <87a6w8hf3n.fsf@keithp.com> (raw)
In-Reply-To: <32eb3f3a-1256-ac68-c2ad-e887269ee796@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 368 bytes --]
Richard Henderson <richard.henderson@linaro.org> writes:
> This is no different to EXCP_DEBUG, really, which is also internal to qemu but
> user-visible in the same way. Just adjust the logging in riscv_cpu_do_interrupt.
I think that's already handled by the early return in
riscv_cpu_do_interrupt after handling the RISCV_EXCP_SEMIHOST case.
--
-keith
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next prev parent reply other threads:[~2020-10-26 21:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 21:49 [PATCH] riscv: Add semihosting support [v8] Keith Packard
2020-10-23 21:49 ` Keith Packard via
2020-10-24 0:22 ` Alistair Francis
2020-10-24 0:22 ` Alistair Francis
2020-10-24 5:56 ` Keith Packard
2020-10-24 5:56 ` Keith Packard via
2020-10-24 15:00 ` Alistair Francis
2020-10-24 15:00 ` Alistair Francis
2020-10-26 19:26 ` Richard Henderson
2020-10-26 19:26 ` Richard Henderson
2020-10-26 21:06 ` Keith Packard [this message]
2020-10-26 21:06 ` Keith Packard via
2020-10-26 19:22 ` Richard Henderson
2020-10-26 19:22 ` Richard Henderson
2020-10-26 21:20 ` Keith Packard
2020-10-26 21:20 ` Keith Packard via
-- strict thread matches above, loose matches on Subject: below --
2020-09-17 21:02 [PATCH] riscv: Add semihosting support [v7] Keith Packard
2020-09-17 21:13 ` [PATCH] riscv: Add semihosting support [v8] Keith Packard
2020-09-17 21:13 ` Keith Packard via
2020-09-17 21:18 ` no-reply
2020-09-17 21:18 ` no-reply
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