* [PATCH v7 01/26] Pass generic CPUState to gen_intermediate_code()
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
@ 2017-06-22 17:32 ` Lluís Vilanova
2017-06-22 17:32 ` [Qemu-devel] [PATCH v7 02/26] queue: Add macro for incremental traversal Lluís Vilanova
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini, Peter Maydell, Edgar E. Iglesias, Eduardo Habkost,
Michael Walle, Laurent Vivier, Aurelien Jarno, Yongbok Kim,
Anthony Green, Stafford Horne, David Gibson, Alexander Graf,
Mark Cave-Ayland, Artyom Tarasenko, Bastian Koppelmann,
Guan Xuetao, Max Filippov, open list:ARM, open list:PowerPC
Needed to implement a target-agnostic gen_intermediate_code() in the
future.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
include/exec/exec-all.h | 2 +-
target/alpha/translate.c | 11 +++++------
target/arm/translate.c | 20 ++++++++++----------
target/cris/translate.c | 17 ++++++++---------
target/i386/translate.c | 13 ++++++-------
target/lm32/translate.c | 22 +++++++++++-----------
target/m68k/translate.c | 15 +++++++--------
target/microblaze/translate.c | 22 +++++++++++-----------
target/mips/translate.c | 15 +++++++--------
target/moxie/translate.c | 14 +++++++-------
target/openrisc/translate.c | 19 ++++++++++---------
target/ppc/translate.c | 15 +++++++--------
target/s390x/translate.c | 13 ++++++-------
target/sh4/translate.c | 15 +++++++--------
target/sparc/translate.c | 11 +++++------
target/tilegx/translate.c | 7 +++----
target/tricore/translate.c | 9 ++++-----
target/unicore32/translate.c | 17 ++++++++---------
target/xtensa/translate.c | 13 ++++++-------
translate-all.c | 2 +-
20 files changed, 130 insertions(+), 142 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 87ae10bcc9..1ec7637170 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t;
#include "qemu/log.h"
-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
target_ulong *data);
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 7c45ae360c..9b60680454 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2900,10 +2900,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUAlphaState *env = cpu->env_ptr;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
target_ulong pc_mask;
@@ -2918,7 +2917,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env, false);
ctx.implver = env->implver;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
#ifdef CONFIG_USER_ONLY
ctx.ir = cpu_std_ir;
@@ -2961,7 +2960,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
ret = gen_excp(&ctx, EXCP_DEBUG, 0);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -3030,7 +3029,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 1);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 1);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0862f9e4aa..96272a9888 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUARMState *env = cpu->env_ptr;
+ ARMCPU *arm_cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
@@ -11804,7 +11804,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
- gen_intermediate_code_a64(cpu, tb);
+ gen_intermediate_code_a64(arm_cpu, tb);
return;
}
@@ -11814,7 +11814,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->condjmp = 0;
dc->aarch64 = 0;
@@ -11840,7 +11840,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
- dc->cp_regs = cpu->cp_regs;
+ dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features;
/* Single step state. The code-generation logic here is:
@@ -11941,9 +11941,9 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
}
#endif
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
CPUBreakpoint *bp;
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+ QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (bp->flags & BP_CPU) {
gen_set_condexec(dc);
@@ -12042,7 +12042,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(cs, "IO on conditional branch instruction");
+ cpu_abort(cpu, "IO on conditional branch instruction");
}
gen_io_end();
}
@@ -12156,7 +12156,7 @@ done_generating:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start,
+ log_target_disas(cpu, pc_start, dc->pc - pc_start,
dc->thumb | (dc->sctlr_b << 1));
qemu_log("\n");
qemu_log_unlock();
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 0ee05ca02d..35931e7061 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
*/
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUCRISState *env = cpu->env_ptr;
uint32_t pc_start;
unsigned int insn_len;
struct DisasContext ctx;
@@ -3105,13 +3104,13 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->cpu = cpu;
+ dc->cpu = cris_env_get_cpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->flags_uptodate = 1;
dc->flagx_known = 1;
dc->flags_x = tb->flags & X_FLAG;
@@ -3151,7 +3150,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
? dc->ppc | 1 : dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc);
t_gen_raise_exception(EXCP_DEBUG);
@@ -3225,7 +3224,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
/* If we are rexecuting a branch due to exceptions on
delay slots don't break. */
- if (!(tb->pc & 1) && cs->singlestep_enabled) {
+ if (!(tb->pc & 1) && cpu->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -3258,7 +3257,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
cris_evaluate_flags(dc);
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(env_pc, npc);
}
@@ -3293,7 +3292,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
qemu_log_lock();
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start,
+ log_target_disas(cpu, pc_start, dc->pc - pc_start,
env->pregs[PR_VR]);
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
diff --git a/target/i386/translate.c b/target/i386/translate.c
index ed3b896db4..b94303ff10 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUX86State *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint32_t flags;
@@ -8404,7 +8403,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
@@ -8426,7 +8425,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || cpu->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK));
/* Do not optimize repz jumps at all in icount mode, because
rep movsS instructions are execured with different paths
@@ -8475,7 +8474,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
num_insns++;
/* If RF is set, suppress an internally generated breakpoint. */
- if (unlikely(cpu_breakpoint_test(cs, pc_ptr,
+ if (unlikely(cpu_breakpoint_test(cpu, pc_ptr,
tb->flags & HF_RF_MASK
? BP_GDB : BP_ANY))) {
gen_debug(dc, pc_ptr - dc->cs_base);
@@ -8551,7 +8550,7 @@ done_generating:
else
#endif
disas_flags = !dc->code32;
- log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags);
+ log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 692882f447..0ac34fc620 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPULM32State *env = cpu->env_ptr;
+ LM32CPU *lm32_cpu = lm32_env_get_cpu(env);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;
@@ -1055,14 +1055,14 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
int max_insns;
pc_start = tb->pc;
- dc->features = cpu->features;
- dc->num_breakpoints = cpu->num_breakpoints;
- dc->num_watchpoints = cpu->num_watchpoints;
+ dc->features = lm32_cpu->features;
+ dc->num_breakpoints = lm32_cpu->num_breakpoints;
+ dc->num_watchpoints = lm32_cpu->num_watchpoints;
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
if (pc_start & 3) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -1085,7 +1085,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
tcg_gen_insn_start(dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
t_gen_raise_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
@@ -1108,7 +1108,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
dc->pc += 4;
} while (!dc->is_jmp
&& !tcg_op_buf_full()
- && !cs->singlestep_enabled
+ && !cpu->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1117,7 +1117,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
gen_io_end();
}
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
@@ -1150,7 +1150,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("\n");
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
qemu_log_unlock();
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ad4d4efb8d..0a3372818c 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5039,10 +5039,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUM68KState *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
int pc_offset;
@@ -5059,7 +5058,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_synced = 1;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->done_mac = 0;
@@ -5080,7 +5079,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
tcg_gen_insn_start(dc->pc, dc->cc_op);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
gen_exception(dc, dc->pc, EXCP_DEBUG);
dc->is_jmp = DISAS_JUMP;
/* The address covered by the breakpoint must be included in
@@ -5098,14 +5097,14 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
} while (!dc->is_jmp && !tcg_op_buf_full() &&
- !cs->singlestep_enabled &&
+ !cpu->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
update_cc_op(dc);
@@ -5138,7 +5137,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0bb609513c..d5f499658d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1594,10 +1594,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMBState *env = cpu->env_ptr;
+ MicroBlazeCPU *mb_cpu = mb_env_get_cpu(env);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;
@@ -1607,7 +1607,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
int max_insns;
pc_start = tb->pc;
- dc->cpu = cpu;
+ dc->cpu = mb_cpu;
dc->tb = tb;
org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
@@ -1618,13 +1618,13 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
dc->jmp = JMP_INDIRECT;
}
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->cpustate_changed = 0;
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
if (pc_start & 3) {
- cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
+ cpu_abort(cpu, "Microblaze: unaligned PC=%x\n", pc_start);
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
@@ -1650,7 +1650,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
}
#endif
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
t_gen_raise_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
/* The address covered by the breakpoint must be included in
@@ -1707,7 +1707,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
break;
}
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -1728,7 +1728,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- /* Force an update if the per-tb cpu state has changed. */
+ /* Force an update if the per-tb mb_cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
dc->is_jmp = DISAS_UPDATE;
@@ -1736,7 +1736,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
}
t_sync_flags(dc);
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
if (dc->is_jmp != DISAS_JUMP) {
@@ -1773,7 +1773,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
qemu_log_lock();
qemu_log("--------------\n");
#if DISAS_GNU
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
#endif
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 559f8fed89..1f9e02f426 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19878,10 +19878,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMIPSState *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;
@@ -19894,7 +19893,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
@@ -19941,7 +19940,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
gen_helper_raise_exception_debug(cpu_env);
@@ -19996,7 +19995,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
+ if (cpu->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
}
@@ -20017,7 +20016,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
if (tb->cflags & CF_LAST_IO) {
gen_io_end();
}
- if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
+ if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
} else {
@@ -20049,7 +20048,7 @@ done_generating:
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 0660b44c08..176063a1de 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MoxieCPU *cpu = moxie_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMoxieState *env = cpu->env_ptr;
+ MoxieCPU *moxie_cpu = moxie_env_get_cpu(env);
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
@@ -851,7 +851,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
ctx.bstate = BS_EXCP;
@@ -864,12 +864,12 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
}
ctx.opcode = cpu_lduw_code(env, ctx.pc);
- ctx.pc += decode_opc(cpu, &ctx);
+ ctx.pc += decode_opc(moxie_cpu, &ctx);
if (num_insns >= max_insns) {
break;
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
@@ -877,7 +877,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
}
} while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
tcg_gen_movi_tl(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index e49518e893..aaac359d5b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1518,9 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
}
}
-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ OpenRISCState *env = cpu->env_ptr;
+ OpenRISCCPU *or_cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
@@ -1533,10 +1534,10 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->mem_idx = cpu_mmu_index(&cpu->env, false);
+ dc->mem_idx = cpu_mmu_index(&or_cpu->env, false);
dc->tb_flags = tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
@@ -1571,7 +1572,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
| (num_insns ? 2 : 0));
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
@@ -1586,7 +1587,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
- disas_openrisc_insn(dc, cpu);
+ disas_openrisc_insn(dc, or_cpu);
dc->pc = dc->pc + 4;
/* delay slot */
@@ -1601,7 +1602,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
}
} while (!dc->is_jmp
&& !tcg_op_buf_full()
- && !cs->singlestep_enabled
+ && !cpu->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1619,7 +1620,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
dc->is_jmp = DISAS_UPDATE;
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
gen_exception(dc, EXCP_DEBUG);
} else {
switch (dc->is_jmp) {
@@ -1647,7 +1648,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(pc_start)) {
- log_target_disas(cs, pc_start, tb->size, 0);
+ log_target_disas(cpu, pc_start, tb->size, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c0cd64d927..9a934117d8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7203,10 +7203,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
}
/*****************************************************************************/
-void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUPPCState *env = cpu->env_ptr;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
target_ulong pc_start;
@@ -7267,7 +7266,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.singlestep_enabled = 0;
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
#if defined (DO_SINGLE_STEP) && 0
@@ -7290,7 +7289,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.nip);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.nip, BP_ANY))) {
gen_debug_exception(ctxp);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -7369,7 +7368,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.exception != POWERPC_EXCP_BRANCH)) {
gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
- (cs->singlestep_enabled) ||
+ (cpu->singlestep_enabled) ||
singlestep ||
num_insns >= max_insns)) {
/* if we reach a page boundary or are single stepping, stop
@@ -7389,7 +7388,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
gen_debug_exception(ctxp);
}
/* Generate the return instruction */
@@ -7408,7 +7407,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
flags |= ctx.le_mode << 16;
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
+ log_target_disas(cpu, pc_start, ctx.nip - pc_start, flags);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 8c055b7bb7..684ae4ce2f 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5708,10 +5708,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
return ret;
}
-void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- S390CPU *cpu = s390_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUS390XState *env = cpu->env_ptr;
DisasContext dc;
target_ulong pc_start;
uint64_t next_page_start;
@@ -5730,7 +5729,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
dc.pc = pc_start;
dc.cc_op = CC_OP_DYNAMIC;
dc.ex_value = tb->cs_base;
- do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
+ do_debug = dc.singlestep_enabled = cpu->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
@@ -5749,7 +5748,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(dc.pc, dc.cc_op);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
status = EXIT_PC_STALE;
do_debug = true;
/* The address covered by the breakpoint must be included in
@@ -5773,7 +5772,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
|| tcg_op_buf_full()
|| num_insns >= max_insns
|| singlestep
- || cs->singlestep_enabled
+ || cpu->singlestep_enabled
|| dc.ex_value)) {
status = EXIT_PC_STALE;
}
@@ -5823,7 +5822,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value);
} else {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start, 1);
+ log_target_disas(cpu, pc_start, dc.pc - pc_start, 1);
qemu_log("\n");
}
qemu_log_unlock();
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8bc132b27b..6a797072d4 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1815,10 +1815,9 @@ static void decode_opc(DisasContext * ctx)
}
}
-void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSH4State *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns;
@@ -1834,7 +1833,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.features = env->features;
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
@@ -1852,7 +1851,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc, ctx.envflags);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
/* We have hit a breakpoint - make sure PC is up-to-date */
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
@@ -1874,7 +1873,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
if (num_insns >= max_insns)
@@ -1884,7 +1883,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
} else {
@@ -1915,7 +1914,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d54e..90c43e4460 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5747,10 +5747,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
-void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
{
- SPARCCPU *cpu = sparc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSPARCState *env = cpu->env_ptr;
target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
int num_insns;
@@ -5768,7 +5767,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (cs->singlestep_enabled || singlestep);
+ dc->singlestep = (cpu->singlestep_enabled || singlestep);
#ifndef CONFIG_USER_ONLY
dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
#endif
@@ -5800,7 +5799,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
num_insns++;
last_pc = dc->pc;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
if (dc->pc != pc_start) {
save_state(dc);
}
@@ -5864,7 +5863,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
qemu_log_lock();
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
+ log_target_disas(cpu, pc_start, last_pc + 4 - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index ff2ef7b63d..a86e9e9d22 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
}
}
-void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- TileGXCPU *cpu = tilegx_env_get_cpu(env);
+ CPUTLGState *env = cpu->env_ptr;
DisasContext ctx;
DisasContext *dc = &ctx;
- CPUState *cs = CPU(cpu);
uint64_t pc_start = tb->pc;
uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
int num_insns = 0;
@@ -2397,7 +2396,7 @@ void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
if (!max_insns) {
max_insns = CF_COUNT_MASK;
}
- if (cs->singlestep_enabled || singlestep) {
+ if (cpu->singlestep_enabled || singlestep) {
max_insns = 1;
}
if (max_insns > TCG_MAX_INSNS) {
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ddd2dd07dd..1930da2f2a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
}
}
-void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- TriCoreCPU *cpu = tricore_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUTriCoreState *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
@@ -8806,7 +8805,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.tb = tb;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.bstate = BS_NONE;
ctx.mem_idx = cpu_mmu_index(env, false);
@@ -8840,7 +8839,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 666a2016a8..494ed58c10 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUUniCore32State *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
uint32_t next_page_start;
@@ -1888,7 +1887,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->condjmp = 0;
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();
@@ -1917,7 +1916,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
tcg_gen_insn_start(dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
gen_set_pc_im(dc->pc);
gen_exception(EXCP_DEBUG);
dc->is_jmp = DISAS_JUMP;
@@ -1949,7 +1948,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
* Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. */
} while (!dc->is_jmp && !tcg_op_buf_full() &&
- !cs->singlestep_enabled &&
+ !cpu->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -1958,7 +1957,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(cs, "IO on conditional branch instruction");
+ cpu_abort(cpu, "IO on conditional branch instruction");
}
gen_io_end();
}
@@ -1966,7 +1965,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
if (dc->is_jmp == DISAS_SYSCALL) {
@@ -2027,7 +2026,7 @@ done_generating:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 263002486c..63e4f25c08 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
}
}
-void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUXtensaState *env = cpu->env_ptr;
DisasContext dc;
int insn_count = 0;
int max_insns = tb->cflags & CF_COUNT_MASK;
@@ -3136,7 +3135,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
}
dc.config = env->config;
- dc.singlestep_enabled = cs->singlestep_enabled;
+ dc.singlestep_enabled = cpu->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
@@ -3179,7 +3178,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
tcg_gen_insn_start(dc.pc);
++insn_count;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
dc.is_jmp = DISAS_UPDATE;
@@ -3215,7 +3214,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
break;
@@ -3247,7 +3246,7 @@ done:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/translate-all.c b/translate-all.c
index b3ee876526..e5de5cace9 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1292,7 +1292,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
tcg_ctx.cpu = ENV_GET_CPU(env);
- gen_intermediate_code(env, tb);
+ gen_intermediate_code(cpu, tb);
tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v7 01/26] Pass generic CPUState to gen_intermediate_code()
@ 2017-06-22 17:32 ` Lluís Vilanova
0 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini, Peter Maydell, Edgar E. Iglesias, Eduardo Habkost,
Michael Walle, Laurent Vivier, Aurelien Jarno, Yongbok Kim,
Anthony Green, Stafford Horne, David Gibson, Alexander Graf,
Mark Cave-Ayland, Artyom Tarasenko, Bastian Koppelmann,
Guan Xuetao, Max Filippov, open list:ARM, open list:PowerPC
Needed to implement a target-agnostic gen_intermediate_code() in the
future.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
include/exec/exec-all.h | 2 +-
target/alpha/translate.c | 11 +++++------
target/arm/translate.c | 20 ++++++++++----------
target/cris/translate.c | 17 ++++++++---------
target/i386/translate.c | 13 ++++++-------
target/lm32/translate.c | 22 +++++++++++-----------
target/m68k/translate.c | 15 +++++++--------
target/microblaze/translate.c | 22 +++++++++++-----------
target/mips/translate.c | 15 +++++++--------
target/moxie/translate.c | 14 +++++++-------
target/openrisc/translate.c | 19 ++++++++++---------
target/ppc/translate.c | 15 +++++++--------
target/s390x/translate.c | 13 ++++++-------
target/sh4/translate.c | 15 +++++++--------
target/sparc/translate.c | 11 +++++------
target/tilegx/translate.c | 7 +++----
target/tricore/translate.c | 9 ++++-----
target/unicore32/translate.c | 17 ++++++++---------
target/xtensa/translate.c | 13 ++++++-------
translate-all.c | 2 +-
20 files changed, 130 insertions(+), 142 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 87ae10bcc9..1ec7637170 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t;
#include "qemu/log.h"
-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
target_ulong *data);
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 7c45ae360c..9b60680454 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2900,10 +2900,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUAlphaState *env = cpu->env_ptr;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
target_ulong pc_mask;
@@ -2918,7 +2917,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env, false);
ctx.implver = env->implver;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
#ifdef CONFIG_USER_ONLY
ctx.ir = cpu_std_ir;
@@ -2961,7 +2960,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
ret = gen_excp(&ctx, EXCP_DEBUG, 0);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -3030,7 +3029,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 1);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 1);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0862f9e4aa..96272a9888 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUARMState *env = cpu->env_ptr;
+ ARMCPU *arm_cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
@@ -11804,7 +11804,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
- gen_intermediate_code_a64(cpu, tb);
+ gen_intermediate_code_a64(arm_cpu, tb);
return;
}
@@ -11814,7 +11814,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->condjmp = 0;
dc->aarch64 = 0;
@@ -11840,7 +11840,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
- dc->cp_regs = cpu->cp_regs;
+ dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features;
/* Single step state. The code-generation logic here is:
@@ -11941,9 +11941,9 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
}
#endif
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
CPUBreakpoint *bp;
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+ QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (bp->flags & BP_CPU) {
gen_set_condexec(dc);
@@ -12042,7 +12042,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(cs, "IO on conditional branch instruction");
+ cpu_abort(cpu, "IO on conditional branch instruction");
}
gen_io_end();
}
@@ -12156,7 +12156,7 @@ done_generating:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start,
+ log_target_disas(cpu, pc_start, dc->pc - pc_start,
dc->thumb | (dc->sctlr_b << 1));
qemu_log("\n");
qemu_log_unlock();
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 0ee05ca02d..35931e7061 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
*/
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUCRISState *env = cpu->env_ptr;
uint32_t pc_start;
unsigned int insn_len;
struct DisasContext ctx;
@@ -3105,13 +3104,13 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->cpu = cpu;
+ dc->cpu = cris_env_get_cpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->flags_uptodate = 1;
dc->flagx_known = 1;
dc->flags_x = tb->flags & X_FLAG;
@@ -3151,7 +3150,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
? dc->ppc | 1 : dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc);
t_gen_raise_exception(EXCP_DEBUG);
@@ -3225,7 +3224,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
/* If we are rexecuting a branch due to exceptions on
delay slots don't break. */
- if (!(tb->pc & 1) && cs->singlestep_enabled) {
+ if (!(tb->pc & 1) && cpu->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -3258,7 +3257,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
cris_evaluate_flags(dc);
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(env_pc, npc);
}
@@ -3293,7 +3292,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
qemu_log_lock();
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start,
+ log_target_disas(cpu, pc_start, dc->pc - pc_start,
env->pregs[PR_VR]);
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
diff --git a/target/i386/translate.c b/target/i386/translate.c
index ed3b896db4..b94303ff10 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUX86State *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint32_t flags;
@@ -8404,7 +8403,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
@@ -8426,7 +8425,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || cpu->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK));
/* Do not optimize repz jumps at all in icount mode, because
rep movsS instructions are execured with different paths
@@ -8475,7 +8474,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
num_insns++;
/* If RF is set, suppress an internally generated breakpoint. */
- if (unlikely(cpu_breakpoint_test(cs, pc_ptr,
+ if (unlikely(cpu_breakpoint_test(cpu, pc_ptr,
tb->flags & HF_RF_MASK
? BP_GDB : BP_ANY))) {
gen_debug(dc, pc_ptr - dc->cs_base);
@@ -8551,7 +8550,7 @@ done_generating:
else
#endif
disas_flags = !dc->code32;
- log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags);
+ log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 692882f447..0ac34fc620 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPULM32State *env = cpu->env_ptr;
+ LM32CPU *lm32_cpu = lm32_env_get_cpu(env);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;
@@ -1055,14 +1055,14 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
int max_insns;
pc_start = tb->pc;
- dc->features = cpu->features;
- dc->num_breakpoints = cpu->num_breakpoints;
- dc->num_watchpoints = cpu->num_watchpoints;
+ dc->features = lm32_cpu->features;
+ dc->num_breakpoints = lm32_cpu->num_breakpoints;
+ dc->num_watchpoints = lm32_cpu->num_watchpoints;
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
if (pc_start & 3) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -1085,7 +1085,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
tcg_gen_insn_start(dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
t_gen_raise_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
@@ -1108,7 +1108,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
dc->pc += 4;
} while (!dc->is_jmp
&& !tcg_op_buf_full()
- && !cs->singlestep_enabled
+ && !cpu->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1117,7 +1117,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
gen_io_end();
}
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
@@ -1150,7 +1150,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("\n");
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
qemu_log_unlock();
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ad4d4efb8d..0a3372818c 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5039,10 +5039,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUM68KState *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
int pc_offset;
@@ -5059,7 +5058,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_synced = 1;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->done_mac = 0;
@@ -5080,7 +5079,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
tcg_gen_insn_start(dc->pc, dc->cc_op);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
gen_exception(dc, dc->pc, EXCP_DEBUG);
dc->is_jmp = DISAS_JUMP;
/* The address covered by the breakpoint must be included in
@@ -5098,14 +5097,14 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
} while (!dc->is_jmp && !tcg_op_buf_full() &&
- !cs->singlestep_enabled &&
+ !cpu->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
update_cc_op(dc);
@@ -5138,7 +5137,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0bb609513c..d5f499658d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1594,10 +1594,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMBState *env = cpu->env_ptr;
+ MicroBlazeCPU *mb_cpu = mb_env_get_cpu(env);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;
@@ -1607,7 +1607,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
int max_insns;
pc_start = tb->pc;
- dc->cpu = cpu;
+ dc->cpu = mb_cpu;
dc->tb = tb;
org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
@@ -1618,13 +1618,13 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
dc->jmp = JMP_INDIRECT;
}
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->cpustate_changed = 0;
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
if (pc_start & 3) {
- cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
+ cpu_abort(cpu, "Microblaze: unaligned PC=%x\n", pc_start);
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
@@ -1650,7 +1650,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
}
#endif
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
t_gen_raise_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
/* The address covered by the breakpoint must be included in
@@ -1707,7 +1707,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
break;
}
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -1728,7 +1728,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- /* Force an update if the per-tb cpu state has changed. */
+ /* Force an update if the per-tb mb_cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
dc->is_jmp = DISAS_UPDATE;
@@ -1736,7 +1736,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
}
t_sync_flags(dc);
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
if (dc->is_jmp != DISAS_JUMP) {
@@ -1773,7 +1773,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
qemu_log_lock();
qemu_log("--------------\n");
#if DISAS_GNU
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
#endif
qemu_log("\nisize=%d osize=%d\n",
dc->pc - pc_start, tcg_op_buf_count());
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 559f8fed89..1f9e02f426 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19878,10 +19878,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMIPSState *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;
@@ -19894,7 +19893,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
@@ -19941,7 +19940,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
gen_helper_raise_exception_debug(cpu_env);
@@ -19996,7 +19995,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
+ if (cpu->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
}
@@ -20017,7 +20016,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
if (tb->cflags & CF_LAST_IO) {
gen_io_end();
}
- if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
+ if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
} else {
@@ -20049,7 +20048,7 @@ done_generating:
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 0660b44c08..176063a1de 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- MoxieCPU *cpu = moxie_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMoxieState *env = cpu->env_ptr;
+ MoxieCPU *moxie_cpu = moxie_env_get_cpu(env);
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
@@ -851,7 +851,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
ctx.bstate = BS_EXCP;
@@ -864,12 +864,12 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
}
ctx.opcode = cpu_lduw_code(env, ctx.pc);
- ctx.pc += decode_opc(cpu, &ctx);
+ ctx.pc += decode_opc(moxie_cpu, &ctx);
if (num_insns >= max_insns) {
break;
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
@@ -877,7 +877,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
}
} while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
tcg_gen_movi_tl(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index e49518e893..aaac359d5b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1518,9 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
}
}
-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ OpenRISCState *env = cpu->env_ptr;
+ OpenRISCCPU *or_cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
@@ -1533,10 +1534,10 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->mem_idx = cpu_mmu_index(&cpu->env, false);
+ dc->mem_idx = cpu_mmu_index(&or_cpu->env, false);
dc->tb_flags = tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
@@ -1571,7 +1572,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
| (num_insns ? 2 : 0));
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
@@ -1586,7 +1587,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
- disas_openrisc_insn(dc, cpu);
+ disas_openrisc_insn(dc, or_cpu);
dc->pc = dc->pc + 4;
/* delay slot */
@@ -1601,7 +1602,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
}
} while (!dc->is_jmp
&& !tcg_op_buf_full()
- && !cs->singlestep_enabled
+ && !cpu->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1619,7 +1620,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
dc->is_jmp = DISAS_UPDATE;
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
gen_exception(dc, EXCP_DEBUG);
} else {
switch (dc->is_jmp) {
@@ -1647,7 +1648,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(pc_start)) {
- log_target_disas(cs, pc_start, tb->size, 0);
+ log_target_disas(cpu, pc_start, tb->size, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c0cd64d927..9a934117d8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7203,10 +7203,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
}
/*****************************************************************************/
-void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUPPCState *env = cpu->env_ptr;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
target_ulong pc_start;
@@ -7267,7 +7266,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.singlestep_enabled = 0;
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
#if defined (DO_SINGLE_STEP) && 0
@@ -7290,7 +7289,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.nip);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.nip, BP_ANY))) {
gen_debug_exception(ctxp);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -7369,7 +7368,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.exception != POWERPC_EXCP_BRANCH)) {
gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
- (cs->singlestep_enabled) ||
+ (cpu->singlestep_enabled) ||
singlestep ||
num_insns >= max_insns)) {
/* if we reach a page boundary or are single stepping, stop
@@ -7389,7 +7388,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
gen_debug_exception(ctxp);
}
/* Generate the return instruction */
@@ -7408,7 +7407,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
flags |= ctx.le_mode << 16;
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
+ log_target_disas(cpu, pc_start, ctx.nip - pc_start, flags);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 8c055b7bb7..684ae4ce2f 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5708,10 +5708,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
return ret;
}
-void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- S390CPU *cpu = s390_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUS390XState *env = cpu->env_ptr;
DisasContext dc;
target_ulong pc_start;
uint64_t next_page_start;
@@ -5730,7 +5729,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
dc.pc = pc_start;
dc.cc_op = CC_OP_DYNAMIC;
dc.ex_value = tb->cs_base;
- do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
+ do_debug = dc.singlestep_enabled = cpu->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
@@ -5749,7 +5748,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
tcg_gen_insn_start(dc.pc, dc.cc_op);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
status = EXIT_PC_STALE;
do_debug = true;
/* The address covered by the breakpoint must be included in
@@ -5773,7 +5772,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
|| tcg_op_buf_full()
|| num_insns >= max_insns
|| singlestep
- || cs->singlestep_enabled
+ || cpu->singlestep_enabled
|| dc.ex_value)) {
status = EXIT_PC_STALE;
}
@@ -5823,7 +5822,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value);
} else {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start, 1);
+ log_target_disas(cpu, pc_start, dc.pc - pc_start, 1);
qemu_log("\n");
}
qemu_log_unlock();
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8bc132b27b..6a797072d4 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1815,10 +1815,9 @@ static void decode_opc(DisasContext * ctx)
}
}
-void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSH4State *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns;
@@ -1834,7 +1833,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.features = env->features;
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
@@ -1852,7 +1851,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
tcg_gen_insn_start(ctx.pc, ctx.envflags);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) {
/* We have hit a breakpoint - make sure PC is up-to-date */
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
@@ -1874,7 +1873,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
break;
}
if (num_insns >= max_insns)
@@ -1884,7 +1883,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
} else {
@@ -1915,7 +1914,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d54e..90c43e4460 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5747,10 +5747,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
-void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
{
- SPARCCPU *cpu = sparc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSPARCState *env = cpu->env_ptr;
target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
int num_insns;
@@ -5768,7 +5767,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (cs->singlestep_enabled || singlestep);
+ dc->singlestep = (cpu->singlestep_enabled || singlestep);
#ifndef CONFIG_USER_ONLY
dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
#endif
@@ -5800,7 +5799,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
num_insns++;
last_pc = dc->pc;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
if (dc->pc != pc_start) {
save_state(dc);
}
@@ -5864,7 +5863,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
qemu_log_lock();
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
+ log_target_disas(cpu, pc_start, last_pc + 4 - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index ff2ef7b63d..a86e9e9d22 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
}
}
-void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- TileGXCPU *cpu = tilegx_env_get_cpu(env);
+ CPUTLGState *env = cpu->env_ptr;
DisasContext ctx;
DisasContext *dc = &ctx;
- CPUState *cs = CPU(cpu);
uint64_t pc_start = tb->pc;
uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
int num_insns = 0;
@@ -2397,7 +2396,7 @@ void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
if (!max_insns) {
max_insns = CF_COUNT_MASK;
}
- if (cs->singlestep_enabled || singlestep) {
+ if (cpu->singlestep_enabled || singlestep) {
max_insns = 1;
}
if (max_insns > TCG_MAX_INSNS) {
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ddd2dd07dd..1930da2f2a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
}
}
-void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
- TriCoreCPU *cpu = tricore_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUTriCoreState *env = cpu->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
@@ -8806,7 +8805,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.tb = tb;
- ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.singlestep_enabled = cpu->singlestep_enabled;
ctx.bstate = BS_NONE;
ctx.mem_idx = cpu_mmu_index(env, false);
@@ -8840,7 +8839,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 666a2016a8..494ed58c10 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUUniCore32State *env = cpu->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
uint32_t next_page_start;
@@ -1888,7 +1887,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->singlestep_enabled = cpu->singlestep_enabled;
dc->condjmp = 0;
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();
@@ -1917,7 +1916,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
tcg_gen_insn_start(dc->pc);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) {
gen_set_pc_im(dc->pc);
gen_exception(EXCP_DEBUG);
dc->is_jmp = DISAS_JUMP;
@@ -1949,7 +1948,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
* Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. */
} while (!dc->is_jmp && !tcg_op_buf_full() &&
- !cs->singlestep_enabled &&
+ !cpu->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -1958,7 +1957,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(cs, "IO on conditional branch instruction");
+ cpu_abort(cpu, "IO on conditional branch instruction");
}
gen_io_end();
}
@@ -1966,7 +1965,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
if (dc->is_jmp == DISAS_SYSCALL) {
@@ -2027,7 +2026,7 @@ done_generating:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc->pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 263002486c..63e4f25c08 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
}
}
-void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUXtensaState *env = cpu->env_ptr;
DisasContext dc;
int insn_count = 0;
int max_insns = tb->cflags & CF_COUNT_MASK;
@@ -3136,7 +3135,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
}
dc.config = env->config;
- dc.singlestep_enabled = cs->singlestep_enabled;
+ dc.singlestep_enabled = cpu->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
@@ -3179,7 +3178,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
tcg_gen_insn_start(dc.pc);
++insn_count;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
dc.is_jmp = DISAS_UPDATE;
@@ -3215,7 +3214,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
}
- if (cs->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
break;
@@ -3247,7 +3246,7 @@ done:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
+ log_target_disas(cpu, pc_start, dc.pc - pc_start, 0);
qemu_log("\n");
qemu_log_unlock();
}
diff --git a/translate-all.c b/translate-all.c
index b3ee876526..e5de5cace9 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1292,7 +1292,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
tcg_ctx.cpu = ENV_GET_CPU(env);
- gen_intermediate_code(env, tb);
+ gen_intermediate_code(cpu, tb);
tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v7 02/26] queue: Add macro for incremental traversal
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
2017-06-22 17:32 ` [Qemu-devel] " Lluís Vilanova
@ 2017-06-22 17:32 ` Lluís Vilanova
2017-06-22 17:33 ` [Qemu-devel] " Lluís Vilanova
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini
Adds macro QTAILQ_FOREACH_CONTINUE to support incremental list
traversal.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
include/qemu/queue.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/qemu/queue.h b/include/qemu/queue.h
index 35292c3155..eb2bf9cb1c 100644
--- a/include/qemu/queue.h
+++ b/include/qemu/queue.h
@@ -415,6 +415,18 @@ struct { \
(var); \
(var) = ((var)->field.tqe_next))
+/**
+ * QTAILQ_FOREACH_CONTINUE:
+ * @var: Variable to resume iteration from.
+ * @field: Field in @var holding a QTAILQ_ENTRY for this queue.
+ *
+ * Resumes iteration on a queue from the element in @var.
+ */
+#define QTAILQ_FOREACH_CONTINUE(var, field) \
+ for ((var) = ((var)->field.tqe_next); \
+ (var); \
+ (var) = ((var)->field.tqe_next))
+
#define QTAILQ_FOREACH_SAFE(var, head, field, next_var) \
for ((var) = ((head)->tqh_first); \
(var) && ((next_var) = ((var)->field.tqe_next), 1); \
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v7 03/26] cpu-exec: Avoid global variables in icount-related functions
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
@ 2017-06-22 17:33 ` Lluís Vilanova
2017-06-22 17:32 ` [Qemu-devel] [PATCH v7 02/26] queue: Add macro for incremental traversal Lluís Vilanova
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini, Peter Maydell, Edgar E. Iglesias, Eduardo Habkost,
Michael Walle, Laurent Vivier, Aurelien Jarno, Yongbok Kim,
Anthony Green, Chris Wulff, Marek Vasut, Stafford Horne,
David Gibson, Alexander Graf, Mark Cave-Ayland, Artyom Tarasenko,
Bastian Koppelmann, Guan Xuetao, Max Filippov, open list:ARM,
open list:PowerPC
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
include/exec/gen-icount.h | 6 +++--
target/alpha/translate.c | 14 ++++++------
target/arm/translate-a64.c | 10 ++++-----
target/arm/translate.c | 10 ++++-----
target/cris/translate.c | 6 +++--
target/hppa/translate.c | 6 +++--
target/i386/translate.c | 46 +++++++++++++++++++++--------------------
target/lm32/translate.c | 14 ++++++------
target/m68k/translate.c | 6 +++--
target/microblaze/translate.c | 6 +++--
target/mips/translate.c | 26 ++++++++++++-----------
target/moxie/translate.c | 2 +-
target/nios2/translate.c | 6 +++--
target/openrisc/translate.c | 6 +++--
target/ppc/translate.c | 6 +++--
target/ppc/translate_init.c | 32 ++++++++++++++---------------
target/s390x/translate.c | 6 +++--
target/sh4/translate.c | 6 +++--
target/sparc/translate.c | 6 +++--
target/tilegx/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/unicore32/translate.c | 6 +++--
target/xtensa/translate.c | 26 ++++++++++++-----------
23 files changed, 128 insertions(+), 128 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 62d462e494..9b26c7da5f 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -8,7 +8,7 @@
static int icount_start_insn_idx;
static TCGLabel *exitreq_label;
-static inline void gen_tb_start(TranslationBlock *tb)
+static inline void gen_tb_start(TranslationBlock *tb, TCGv_env cpu_env)
{
TCGv_i32 count, imm;
@@ -59,14 +59,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns)
tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next = 0;
}
-static inline void gen_io_start(void)
+static inline void gen_io_start(TCGv_env cpu_env)
{
TCGv_i32 tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
-static inline void gen_io_end(void)
+static inline void gen_io_end(TCGv_env cpu_env)
{
TCGv_i32 tmp = tcg_const_i32(0);
tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 9b60680454..fdc49109ad 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1329,9 +1329,9 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)
helper = gen_helper_get_vmtime;
do_helper:
if (use_icount) {
- gen_io_start();
+ gen_io_start(cpu_env);
helper(va);
- gen_io_end();
+ gen_io_end(cpu_env);
return EXIT_PC_STALE;
} else {
helper(va);
@@ -2379,9 +2379,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
/* RPCC */
va = dest_gpr(ctx, ra);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
gen_helper_load_pcc(va, cpu_env);
- gen_io_end();
+ gen_io_end(cpu_env);
ret = EXIT_PC_STALE;
} else {
gen_helper_load_pcc(va, cpu_env);
@@ -2955,7 +2955,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
pc_mask = ~TARGET_PAGE_MASK;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(ctx.pc);
num_insns++;
@@ -2970,7 +2970,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
insn = cpu_ldl_code(env, ctx.pc);
@@ -2991,7 +2991,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
} while (ret == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (ret) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 860e279658..43261e7939 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1558,7 +1558,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
}
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_rt = cpu_reg(s, rt);
@@ -1590,7 +1590,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
- gen_io_end();
+ gen_io_end(cpu_env);
s->is_jmp = DISAS_UPDATE;
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* We default to ending the TB on a coprocessor register write,
@@ -11263,7 +11263,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
@@ -11297,7 +11297,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc->ss_active && !dc->pstate_ss) {
@@ -11338,7 +11338,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (unlikely(cs->singlestep_enabled || dc->ss_active)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 96272a9888..073562269b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7654,7 +7654,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (isread) {
@@ -7746,7 +7746,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
- gen_io_end();
+ gen_io_end(cpu_env);
gen_lookup_tb(s);
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* We default to ending the TB on a coprocessor register write,
@@ -11881,7 +11881,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
@@ -11969,7 +11969,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc->ss_active && !dc->pstate_ss) {
@@ -12044,7 +12044,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
code. */
cpu_abort(cpu, "IO on conditional branch instruction");
}
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* At this stage dc->condjmp will only be set when the skipped
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 35931e7061..90424abe00 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3144,7 +3144,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->delayed_branch == 1
? dc->ppc | 1 : dc->pc);
@@ -3167,7 +3167,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->clear_x = 1;
@@ -3240,7 +3240,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
npc = dc->pc;
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
/* Force an update if the per-tb cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || !dc->flagx_known
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e10abc5e04..ba154661fc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3773,7 +3773,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
}
num_insns = 0;
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
/* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */
ctx.null_cond = cond_make_f();
@@ -3793,7 +3793,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
break;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (ctx.iaoq_f < TARGET_PAGE_SIZE) {
@@ -3869,7 +3869,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
} while (ret == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (ret) {
diff --git a/target/i386/translate.c b/target/i386/translate.c
index b94303ff10..9f42a5509d 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -1120,7 +1120,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
@@ -1135,14 +1135,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
static inline void gen_outs(DisasContext *s, TCGMemOp ot)
{
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
@@ -1155,7 +1155,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
@@ -6338,14 +6338,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6359,14 +6359,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6377,14 +6377,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6397,14 +6397,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7112,11 +7112,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_rdtsc(cpu_env);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7571,11 +7571,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_rdtscp(cpu_env);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7940,24 +7940,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_op_mov_v_reg(ot, cpu_T0, rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T0);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg));
gen_op_mov_reg_v(ot, rm, cpu_T0);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
break;
@@ -8468,7 +8468,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
for(;;) {
tcg_gen_insn_start(pc_ptr, dc->cc_op);
num_insns++;
@@ -8486,7 +8486,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
goto done_generating;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
pc_ptr = disas_insn(env, dc, pc_ptr);
@@ -8533,7 +8533,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
done_generating:
gen_tb_end(tb, num_insns);
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 0ac34fc620..b635d4ea7a 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -875,24 +875,24 @@ static void dec_wcsr(DisasContext *dc)
case CSR_IM:
/* mark as an io operation because it could cause an interrupt */
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
dc->is_jmp = DISAS_UPDATE;
break;
case CSR_IP:
/* mark as an io operation because it could cause an interrupt */
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
dc->is_jmp = DISAS_UPDATE;
break;
@@ -1080,7 +1080,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -1101,7 +1101,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
decode(dc, cpu_ldl_code(env, dc->pc));
@@ -1114,7 +1114,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
&& num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (unlikely(cpu->singlestep_enabled)) {
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0a3372818c..5fac91aec5 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5072,7 +5072,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
@@ -5091,7 +5091,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->insn_pc = dc->pc;
@@ -5103,7 +5103,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index d5f499658d..7bcdc81413 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1637,7 +1637,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do
{
tcg_gen_insn_start(dc->pc);
@@ -1665,7 +1665,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->clear_imm = 1;
@@ -1727,7 +1727,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
/* Force an update if the per-tb mb_cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1f9e02f426..1a14319e7a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5233,11 +5233,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* Mark as an IO operation because we read the time. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mfc0_count(arg, cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
@@ -5637,7 +5637,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
switch (reg) {
@@ -6286,7 +6286,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
ctx->bstate = BS_STOP;
}
return;
@@ -6546,11 +6546,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* Mark as an IO operation because we read the time. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mfc0_count(arg, cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
@@ -6937,7 +6937,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS64);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
switch (reg) {
@@ -7254,11 +7254,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Mark as an IO operation because we may trigger a software
interrupt. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mtc0_cause(cpu_env, arg);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Stop translation as we may have triggered an intetrupt */
ctx->bstate = BS_STOP;
@@ -7584,7 +7584,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
ctx->bstate = BS_STOP;
}
return;
@@ -19935,7 +19935,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
@@ -19953,7 +19953,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
@@ -20014,7 +20014,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 176063a1de..2bcf1f6856 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -846,7 +846,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(ctx.pc);
num_insns++;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 2f3c2e5dfb..b21fed869b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -834,7 +834,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
}
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -850,7 +850,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
/* Decode an instruction */
@@ -867,7 +867,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Indicate where the next block should start */
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index aaac359d5b..6c555dfeeb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1557,7 +1557,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
qemu_log("IN: %s\n", lookup_symbol(pc_start));
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
@@ -1585,7 +1585,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
disas_openrisc_insn(dc, or_cpu);
dc->pc = dc->pc + 4;
@@ -1608,7 +1608,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
&& num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9a934117d8..b395241f01 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7282,7 +7282,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
@@ -7303,7 +7303,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
- gen_io_start();
+ gen_io_start(cpu_env);
if (unlikely(need_byteswap(&ctx))) {
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
} else {
@@ -7384,7 +7384,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 56a0ab22cf..d25c309415 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -175,11 +175,11 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -187,11 +187,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -202,11 +202,11 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -214,11 +214,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -239,11 +239,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -251,11 +251,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -283,11 +283,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -295,11 +295,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 684ae4ce2f..14abb6e6b9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5742,7 +5742,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc.pc, dc.cc_op);
@@ -5760,7 +5760,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
status = translate_one(env, &dc);
@@ -5779,7 +5779,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
} while (status == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (status) {
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 6a797072d4..2558347d9a 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1846,7 +1846,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) {
tcg_gen_insn_start(ctx.pc, ctx.envflags);
num_insns++;
@@ -1865,7 +1865,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
ctx.opcode = cpu_lduw_code(env, ctx.pc);
@@ -1882,7 +1882,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (cpu->singlestep_enabled) {
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 90c43e4460..763d399419 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5788,7 +5788,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
if (dc->npc & JUMP_PC) {
assert(dc->jump_pc[1] == dc->pc + 4);
@@ -5810,7 +5810,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
insn = cpu_ldl_code(env, dc->pc);
@@ -5837,7 +5837,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
exit_gen_loop:
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (!dc->is_br) {
if (dc->pc != DYNAMIC_PC &&
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index a86e9e9d22..2dbed6b19b 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2402,7 +2402,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (1) {
tcg_gen_insn_start(dc->pc);
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1930da2f2a..a4a8bb2272 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8810,7 +8810,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
ctx.mem_idx = cpu_mmu_index(env, false);
tcg_clear_temp_count();
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc);
num_insns++;
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 494ed58c10..a7878ffd81 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1911,7 +1911,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
#endif
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -1929,7 +1929,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
disas_uc32_insn(env, dc);
@@ -1959,7 +1959,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
code. */
cpu_abort(cpu, "IO on conditional branch instruction");
}
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* At this stage dc->condjmp will only be set when the skipped
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 63e4f25c08..63e9646d17 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -514,12 +514,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_update_ccount(cpu_env);
tcg_gen_mov_i32(d, cpu_SR[sr]);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
return true;
}
return false;
@@ -699,11 +699,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static void gen_check_interrupts(DisasContext *dc)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_check_interrupts(cpu_env);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
@@ -757,11 +757,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wsr_ccount(cpu_env, v);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jumpi_check_loop_end(dc, 0);
return true;
}
@@ -798,11 +798,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_update_ccompare(cpu_env, tmp);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jumpi_check_loop_end(dc, 0);
ret = true;
}
@@ -897,11 +897,11 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4)
TCGv_i32 intlevel = tcg_const_i32(imm4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_waiti(cpu_env, pc, intlevel);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
tcg_temp_free(pc);
tcg_temp_free(intlevel);
@@ -3156,7 +3156,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
dc.next_icount = tcg_temp_local_new_i32();
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
if ((tb->cflags & CF_USE_ICOUNT) &&
(tb->flags & XTENSA_TBFLAG_YIELD)) {
@@ -3191,7 +3191,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc.icount) {
@@ -3232,7 +3232,7 @@ done:
}
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (dc.is_jmp == DISAS_NEXT) {
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v7 03/26] cpu-exec: Avoid global variables in icount-related functions
@ 2017-06-22 17:33 ` Lluís Vilanova
0 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini, Peter Maydell, Edgar E. Iglesias, Eduardo Habkost,
Michael Walle, Laurent Vivier, Aurelien Jarno, Yongbok Kim,
Anthony Green, Chris Wulff, Marek Vasut, Stafford Horne,
David Gibson, Alexander Graf, Mark Cave-Ayland, Artyom Tarasenko,
Bastian Koppelmann, Guan Xuetao, Max Filippov, open list:ARM,
open list:PowerPC
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
include/exec/gen-icount.h | 6 +++--
target/alpha/translate.c | 14 ++++++------
target/arm/translate-a64.c | 10 ++++-----
target/arm/translate.c | 10 ++++-----
target/cris/translate.c | 6 +++--
target/hppa/translate.c | 6 +++--
target/i386/translate.c | 46 +++++++++++++++++++++--------------------
target/lm32/translate.c | 14 ++++++------
target/m68k/translate.c | 6 +++--
target/microblaze/translate.c | 6 +++--
target/mips/translate.c | 26 ++++++++++++-----------
target/moxie/translate.c | 2 +-
target/nios2/translate.c | 6 +++--
target/openrisc/translate.c | 6 +++--
target/ppc/translate.c | 6 +++--
target/ppc/translate_init.c | 32 ++++++++++++++---------------
target/s390x/translate.c | 6 +++--
target/sh4/translate.c | 6 +++--
target/sparc/translate.c | 6 +++--
target/tilegx/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/unicore32/translate.c | 6 +++--
target/xtensa/translate.c | 26 ++++++++++++-----------
23 files changed, 128 insertions(+), 128 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 62d462e494..9b26c7da5f 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -8,7 +8,7 @@
static int icount_start_insn_idx;
static TCGLabel *exitreq_label;
-static inline void gen_tb_start(TranslationBlock *tb)
+static inline void gen_tb_start(TranslationBlock *tb, TCGv_env cpu_env)
{
TCGv_i32 count, imm;
@@ -59,14 +59,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns)
tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next = 0;
}
-static inline void gen_io_start(void)
+static inline void gen_io_start(TCGv_env cpu_env)
{
TCGv_i32 tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
-static inline void gen_io_end(void)
+static inline void gen_io_end(TCGv_env cpu_env)
{
TCGv_i32 tmp = tcg_const_i32(0);
tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 9b60680454..fdc49109ad 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1329,9 +1329,9 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)
helper = gen_helper_get_vmtime;
do_helper:
if (use_icount) {
- gen_io_start();
+ gen_io_start(cpu_env);
helper(va);
- gen_io_end();
+ gen_io_end(cpu_env);
return EXIT_PC_STALE;
} else {
helper(va);
@@ -2379,9 +2379,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
/* RPCC */
va = dest_gpr(ctx, ra);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
gen_helper_load_pcc(va, cpu_env);
- gen_io_end();
+ gen_io_end(cpu_env);
ret = EXIT_PC_STALE;
} else {
gen_helper_load_pcc(va, cpu_env);
@@ -2955,7 +2955,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
pc_mask = ~TARGET_PAGE_MASK;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(ctx.pc);
num_insns++;
@@ -2970,7 +2970,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
insn = cpu_ldl_code(env, ctx.pc);
@@ -2991,7 +2991,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
} while (ret == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (ret) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 860e279658..43261e7939 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1558,7 +1558,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
}
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_rt = cpu_reg(s, rt);
@@ -1590,7 +1590,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
- gen_io_end();
+ gen_io_end(cpu_env);
s->is_jmp = DISAS_UPDATE;
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* We default to ending the TB on a coprocessor register write,
@@ -11263,7 +11263,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
@@ -11297,7 +11297,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc->ss_active && !dc->pstate_ss) {
@@ -11338,7 +11338,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (unlikely(cs->singlestep_enabled || dc->ss_active)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 96272a9888..073562269b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7654,7 +7654,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (isread) {
@@ -7746,7 +7746,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
- gen_io_end();
+ gen_io_end(cpu_env);
gen_lookup_tb(s);
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* We default to ending the TB on a coprocessor register write,
@@ -11881,7 +11881,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
@@ -11969,7 +11969,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc->ss_active && !dc->pstate_ss) {
@@ -12044,7 +12044,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
code. */
cpu_abort(cpu, "IO on conditional branch instruction");
}
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* At this stage dc->condjmp will only be set when the skipped
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 35931e7061..90424abe00 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3144,7 +3144,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->delayed_branch == 1
? dc->ppc | 1 : dc->pc);
@@ -3167,7 +3167,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->clear_x = 1;
@@ -3240,7 +3240,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
npc = dc->pc;
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
/* Force an update if the per-tb cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || !dc->flagx_known
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e10abc5e04..ba154661fc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3773,7 +3773,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
}
num_insns = 0;
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
/* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */
ctx.null_cond = cond_make_f();
@@ -3793,7 +3793,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
break;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (ctx.iaoq_f < TARGET_PAGE_SIZE) {
@@ -3869,7 +3869,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
} while (ret == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (ret) {
diff --git a/target/i386/translate.c b/target/i386/translate.c
index b94303ff10..9f42a5509d 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -1120,7 +1120,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
@@ -1135,14 +1135,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
static inline void gen_outs(DisasContext *s, TCGMemOp ot)
{
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
@@ -1155,7 +1155,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
@@ -6338,14 +6338,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6359,14 +6359,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6377,14 +6377,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -6397,14 +6397,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7112,11 +7112,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_rdtsc(cpu_env);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7571,11 +7571,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_rdtscp(cpu_env);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jmp(s, s->pc - s->cs_base);
}
break;
@@ -7940,24 +7940,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_op_mov_v_reg(ot, cpu_T0, rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T0);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg));
gen_op_mov_reg_v(ot, rm, cpu_T0);
if (s->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
break;
@@ -8468,7 +8468,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
for(;;) {
tcg_gen_insn_start(pc_ptr, dc->cc_op);
num_insns++;
@@ -8486,7 +8486,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
goto done_generating;
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
pc_ptr = disas_insn(env, dc, pc_ptr);
@@ -8533,7 +8533,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
done_generating:
gen_tb_end(tb, num_insns);
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 0ac34fc620..b635d4ea7a 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -875,24 +875,24 @@ static void dec_wcsr(DisasContext *dc)
case CSR_IM:
/* mark as an io operation because it could cause an interrupt */
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
dc->is_jmp = DISAS_UPDATE;
break;
case CSR_IP:
/* mark as an io operation because it could cause an interrupt */
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
dc->is_jmp = DISAS_UPDATE;
break;
@@ -1080,7 +1080,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -1101,7 +1101,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
decode(dc, cpu_ldl_code(env, dc->pc));
@@ -1114,7 +1114,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
&& num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (unlikely(cpu->singlestep_enabled)) {
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0a3372818c..5fac91aec5 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5072,7 +5072,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
@@ -5091,7 +5091,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->insn_pc = dc->pc;
@@ -5103,7 +5103,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (unlikely(cpu->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index d5f499658d..7bcdc81413 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1637,7 +1637,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do
{
tcg_gen_insn_start(dc->pc);
@@ -1665,7 +1665,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
dc->clear_imm = 1;
@@ -1727,7 +1727,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
/* Force an update if the per-tb mb_cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1f9e02f426..1a14319e7a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5233,11 +5233,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* Mark as an IO operation because we read the time. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mfc0_count(arg, cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
@@ -5637,7 +5637,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
switch (reg) {
@@ -6286,7 +6286,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
ctx->bstate = BS_STOP;
}
return;
@@ -6546,11 +6546,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
/* Mark as an IO operation because we read the time. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mfc0_count(arg, cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
@@ -6937,7 +6937,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS64);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
switch (reg) {
@@ -7254,11 +7254,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Mark as an IO operation because we may trigger a software
interrupt. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_mtc0_cause(cpu_env, arg);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Stop translation as we may have triggered an intetrupt */
ctx->bstate = BS_STOP;
@@ -7584,7 +7584,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
ctx->bstate = BS_STOP;
}
return;
@@ -19935,7 +19935,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
@@ -19953,7 +19953,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
@@ -20014,7 +20014,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 176063a1de..2bcf1f6856 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -846,7 +846,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(ctx.pc);
num_insns++;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 2f3c2e5dfb..b21fed869b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -834,7 +834,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
}
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -850,7 +850,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
/* Decode an instruction */
@@ -867,7 +867,7 @@ void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* Indicate where the next block should start */
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index aaac359d5b..6c555dfeeb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1557,7 +1557,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
qemu_log("IN: %s\n", lookup_symbol(pc_start));
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
@@ -1585,7 +1585,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
disas_openrisc_insn(dc, or_cpu);
dc->pc = dc->pc + 4;
@@ -1608,7 +1608,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
&& num_insns < max_insns);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9a934117d8..b395241f01 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7282,7 +7282,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
tcg_clear_temp_count();
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
@@ -7303,7 +7303,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
- gen_io_start();
+ gen_io_start(cpu_env);
if (unlikely(need_byteswap(&ctx))) {
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
} else {
@@ -7384,7 +7384,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 56a0ab22cf..d25c309415 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -175,11 +175,11 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -187,11 +187,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -202,11 +202,11 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -214,11 +214,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -239,11 +239,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -251,11 +251,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -283,11 +283,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
@@ -295,11 +295,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
if (ctx->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_stop_exception(ctx);
}
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 684ae4ce2f..14abb6e6b9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5742,7 +5742,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc.pc, dc.cc_op);
@@ -5760,7 +5760,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
status = translate_one(env, &dc);
@@ -5779,7 +5779,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
} while (status == NO_EXIT);
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
switch (status) {
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 6a797072d4..2558347d9a 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1846,7 +1846,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) {
tcg_gen_insn_start(ctx.pc, ctx.envflags);
num_insns++;
@@ -1865,7 +1865,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
ctx.opcode = cpu_lduw_code(env, ctx.pc);
@@ -1882,7 +1882,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
break;
}
if (tb->cflags & CF_LAST_IO)
- gen_io_end();
+ gen_io_end(cpu_env);
if (cpu->singlestep_enabled) {
gen_save_cpu_state(&ctx, true);
gen_helper_debug(cpu_env);
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 90c43e4460..763d399419 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5788,7 +5788,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
if (dc->npc & JUMP_PC) {
assert(dc->jump_pc[1] == dc->pc + 4);
@@ -5810,7 +5810,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
insn = cpu_ldl_code(env, dc->pc);
@@ -5837,7 +5837,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb)
exit_gen_loop:
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (!dc->is_br) {
if (dc->pc != DYNAMIC_PC &&
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index a86e9e9d22..2dbed6b19b 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2402,7 +2402,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (1) {
tcg_gen_insn_start(dc->pc);
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1930da2f2a..a4a8bb2272 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8810,7 +8810,7 @@ void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
ctx.mem_idx = cpu_mmu_index(env, false);
tcg_clear_temp_count();
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
while (ctx.bstate == BS_NONE) {
tcg_gen_insn_start(ctx.pc);
num_insns++;
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 494ed58c10..a7878ffd81 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1911,7 +1911,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
#endif
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
do {
tcg_gen_insn_start(dc->pc);
num_insns++;
@@ -1929,7 +1929,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
disas_uc32_insn(env, dc);
@@ -1959,7 +1959,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
code. */
cpu_abort(cpu, "IO on conditional branch instruction");
}
- gen_io_end();
+ gen_io_end(cpu_env);
}
/* At this stage dc->condjmp will only be set when the skipped
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 63e4f25c08..63e9646d17 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -514,12 +514,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_update_ccount(cpu_env);
tcg_gen_mov_i32(d, cpu_SR[sr]);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
return true;
}
return false;
@@ -699,11 +699,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static void gen_check_interrupts(DisasContext *dc)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_check_interrupts(cpu_env);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
}
@@ -757,11 +757,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_wsr_ccount(cpu_env, v);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jumpi_check_loop_end(dc, 0);
return true;
}
@@ -798,11 +798,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_update_ccompare(cpu_env, tmp);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
gen_jumpi_check_loop_end(dc, 0);
ret = true;
}
@@ -897,11 +897,11 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4)
TCGv_i32 intlevel = tcg_const_i32(imm4);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
gen_helper_waiti(cpu_env, pc, intlevel);
if (dc->tb->cflags & CF_USE_ICOUNT) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
tcg_temp_free(pc);
tcg_temp_free(intlevel);
@@ -3156,7 +3156,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
dc.next_icount = tcg_temp_local_new_i32();
}
- gen_tb_start(tb);
+ gen_tb_start(tb, cpu_env);
if ((tb->cflags & CF_USE_ICOUNT) &&
(tb->flags & XTENSA_TBFLAG_YIELD)) {
@@ -3191,7 +3191,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
}
if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
+ gen_io_start(cpu_env);
}
if (dc.icount) {
@@ -3232,7 +3232,7 @@ done:
}
if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+ gen_io_end(cpu_env);
}
if (dc.is_jmp == DISAS_NEXT) {
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v7 04/26] target: [tcg] Add generic translation framework
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
` (2 preceding siblings ...)
2017-06-22 17:33 ` [Qemu-devel] " Lluís Vilanova
@ 2017-06-22 17:33 ` Lluís Vilanova
2017-06-22 17:33 ` [Qemu-devel] [PATCH v7 08/26] target: [tcg, i386] Refactor init_globals Lluís Vilanova
2017-06-22 18:06 ` [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
Makefile.target | 1
include/exec/gen-icount.h | 2
include/exec/translate-block.h | 125 +++++++++++++++++++++++++++
include/qom/cpu.h | 22 +++++
translate-block.c | 185 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 334 insertions(+), 1 deletion(-)
create mode 100644 include/exec/translate-block.h
create mode 100644 translate-block.c
diff --git a/Makefile.target b/Makefile.target
index ce8dfe44a8..253c6e7999 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -90,6 +90,7 @@ all: $(PROGS) stap
# cpu emulator library
obj-y = exec.o translate-all.o cpu-exec.o
obj-y += translate-common.o
+obj-y += translate-block.o
obj-y += cpu-exec-common.o
obj-y += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
obj-$(CONFIG_TCG_INTERPRETER) += tci.o
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 9b26c7da5f..f4ad61014b 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -44,7 +44,7 @@ static inline void gen_tb_start(TranslationBlock *tb, TCGv_env cpu_env)
tcg_temp_free_i32(count);
}
-static void gen_tb_end(TranslationBlock *tb, int num_insns)
+static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
{
if (tb->cflags & CF_USE_ICOUNT) {
/* Update the num_insn immediate parameter now that we know
diff --git a/include/exec/translate-block.h b/include/exec/translate-block.h
new file mode 100644
index 0000000000..d14d23f2cb
--- /dev/null
+++ b/include/exec/translate-block.h
@@ -0,0 +1,125 @@
+/*
+ * Generic intermediate code generation.
+ *
+ * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef EXEC__TRANSLATE_BLOCK_H
+#define EXEC__TRANSLATE_BLOCK_H
+
+/*
+ * Include this header from a target-specific file, and add a
+ *
+ * DisasContextBase base;
+ *
+ * member in your target-specific DisasContext.
+ */
+
+
+#include "exec/exec-all.h"
+#include "tcg/tcg.h"
+
+
+/**
+ * BreakpointCheckType:
+ * @BC_MISS: No hit
+ * @BC_HIT_INSN: Hit, but continue translating TB
+ * @BC_HIT_TB: Hit, stop translating TB
+ *
+ * How to react to a breakpoint. A hit means no more breakpoints will be checked
+ * for the current instruction.
+ *
+ * Not all breakpoints associated to an address are necessarily raised by
+ * targets (e.g., due to conditions encoded in their flags), so tey can decide
+ * that a breakpoint missed the address (@BP_MISS).
+ */
+typedef enum BreakpointCheckType {
+ BC_MISS,
+ BC_HIT_INSN,
+ BC_HIT_TB,
+} BreakpointCheckType;
+
+/**
+ * DisasJumpType:
+ * @DJ_NEXT: Next instruction in program order.
+ * @DJ_TOO_MANY: Too many instructions translated.
+ * @DJ_TARGET: Start of target-specific conditions.
+ *
+ * What instruction to disassemble next.
+ */
+typedef enum DisasJumpType {
+ DJ_NEXT,
+ DJ_TOO_MANY,
+ DJ_TARGET,
+} DisasJumpType;
+
+/**
+ * DisasContextBase:
+ * @tb: Translation block for this disassembly.
+ * @pc_first: Address of first guest instruction in this TB.
+ * @pc_next: Address of next guest instruction in this TB (current during
+ * disassembly).
+ * @is_jmp: What instruction to disassemble next.
+ * @num_insns: Number of translated instructions (including current).
+ * @singlestep_enabled: "Hardware" single stepping enabled.
+ *
+ * Architecture-agnostic disassembly context.
+ */
+typedef struct DisasContextBase {
+ TranslationBlock *tb;
+ target_ulong pc_first;
+ target_ulong pc_next;
+ DisasJumpType is_jmp;
+ unsigned int num_insns;
+ bool singlestep_enabled;
+} DisasContextBase;
+
+/**
+ * TranslatorOps:
+ * @init_disas_context: Initialize a DisasContext struct (DisasContextBase has
+ * already been initialized).
+ * @init_globals: Initialize global variables.
+ * @tb_start: Start translating a new TB.
+ * @insn_start: Start translating a new instruction.
+ * @breakpoint_check: Check if a breakpoint did hit. When called, the breakpoint
+ * has already been checked to match the PC.
+ * @disas_insn: Disassemble one instruction an return the PC for the next
+ * one. Can set db->is_jmp to DJ_TARGET or above to stop
+ * translation.
+ * @tb_stop: Stop translating a TB.
+ * @disas_flags: Get flags argument for log_target_disas().
+ *
+ * Target-specific operations for the generic translator loop.
+ *
+ * All operations but disas_insn() are optional, and ignored when not set.
+ * A missing breakpoint_check() will ignore breakpoints. A missing disas_flags()
+ * will pass no flags.
+ */
+typedef struct TranslatorOps {
+ void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
+ void (*init_globals)(DisasContextBase *db, CPUState *cpu);
+ void (*tb_start)(DisasContextBase *db, CPUState *cpu);
+ void (*insn_start)(DisasContextBase *db, CPUState *cpu);
+ BreakpointCheckType (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
+ const CPUBreakpoint *bp);
+ target_ulong (*disas_insn)(DisasContextBase *db, CPUState *cpu);
+ void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
+ int (*disas_flags)(const DisasContextBase *db);
+} TranslatorOps;
+
+/**
+ * translate_block:
+ * @ops: Target-specific operations.
+ * @db:
+ * @cpu:
+ * @tb:
+ *
+ * Generic translator loop.
+ */
+void translate_block(const TranslatorOps *ops, DisasContextBase *db,
+ CPUState *cpu, TCGv_env *tcg_cpu, TranslationBlock *tb);
+
+#endif /* EXEC__TRANSLATE_BLOCK_H */
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 89ddb686fb..d46e8df756 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -982,6 +982,28 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}
+/* Get first breakpoint matching a PC */
+static inline CPUBreakpoint *cpu_breakpoint_get(CPUState *cpu, vaddr pc,
+ CPUBreakpoint *bp)
+{
+ if (likely(bp == NULL)) {
+ if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
+ if (bp->pc == pc) {
+ return bp;
+ }
+ }
+ }
+ } else {
+ QTAILQ_FOREACH_CONTINUE(bp, entry) {
+ if (bp->pc == pc) {
+ return bp;
+ }
+ }
+ }
+ return NULL;
+}
+
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
diff --git a/translate-block.c b/translate-block.c
new file mode 100644
index 0000000000..1aac80560e
--- /dev/null
+++ b/translate-block.c
@@ -0,0 +1,185 @@
+/*
+ * Generic intermediate code generation.
+ *
+ * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/error-report.h"
+#include "cpu.h"
+#include "tcg/tcg.h"
+#include "tcg/tcg-op.h"
+#include "exec/exec-all.h"
+#include "exec/gen-icount.h"
+#include "exec/log.h"
+#include "exec/translate-block.h"
+
+
+static inline void translate_block_tcg_check(const DisasContextBase *db)
+{
+ if (tcg_check_temp_count()) {
+ error_report("warning: TCG temporary leaks before "TARGET_FMT_lx,
+ db->pc_next);
+ }
+}
+
+void translate_block(const TranslatorOps *ops, DisasContextBase *db,
+ CPUState *cpu, TCGv_env *tcg_cpu, TranslationBlock *tb)
+{
+ int max_insns;
+
+ /* Sanity-check ops */
+ if (ops->disas_insn == NULL) {
+ error_report("Missing ops->disas_insn");
+ abort();
+ }
+
+ /* Initialize DisasContext */
+ db->tb = tb;
+ db->pc_first = tb->pc;
+ db->pc_next = db->pc_first;
+ db->is_jmp = DJ_NEXT;
+ db->num_insns = 0;
+ db->singlestep_enabled = cpu->singlestep_enabled;
+ if (ops->init_disas_context) {
+ ops->init_disas_context(db, cpu);
+ }
+
+ /* Initialize globals */
+ if (ops->init_globals) {
+ ops->init_globals(db, cpu);
+ }
+ tcg_clear_temp_count();
+
+ /* Instruction counting */
+ max_insns = db->tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+ if (db->singlestep_enabled || singlestep) {
+ max_insns = 1;
+ }
+
+ /* Start translating */
+ gen_tb_start(db->tb, *tcg_cpu);
+ if (ops->tb_start) {
+ ops->tb_start(db, cpu);
+ }
+
+ while (true) {
+ CPUBreakpoint *bp;
+
+ db->num_insns++;
+ if (ops->insn_start) {
+ ops->insn_start(db, cpu);
+ }
+
+ /* Early exit before breakpoint checks */
+ if (unlikely(db->is_jmp != DJ_NEXT)) {
+ break;
+ }
+
+ /* Pass breakpoint hits to target for further processing */
+ bp = NULL;
+ do {
+ bp = cpu_breakpoint_get(cpu, db->pc_next, bp);
+ if (unlikely(bp) && ops->breakpoint_check) {
+ BreakpointCheckType bp_check = ops->breakpoint_check(
+ db, cpu, bp);
+ if (bp_check == BC_HIT_INSN) {
+ /* Hit, keep translating */
+ /*
+ * TODO: if we're never going to have more than one BP in a
+ * single address, we can simply use a bool here.
+ */
+ break;
+ } else if (bp_check == BC_HIT_TB) {
+ goto done_generating;
+ } else {
+ error_report("Unexpected BreakpointCheckType %d", bp_check);
+ abort();
+ }
+ }
+ } while (bp != NULL);
+
+ /* Accept I/O on last instruction */
+ if (db->num_insns == max_insns && (db->tb->cflags & CF_LAST_IO)) {
+ gen_io_start(*tcg_cpu);
+ }
+
+ /* Disassemble one instruction */
+ db->pc_next = ops->disas_insn(db, cpu);
+
+ /**************************************************/
+ /* Conditions to stop translation */
+ /**************************************************/
+
+ /* Target-specific conditions set by disassembly */
+ if (db->is_jmp != DJ_NEXT) {
+ break;
+ }
+
+ /* Too many instructions */
+ if (tcg_op_buf_full() || db->num_insns >= max_insns) {
+ db->is_jmp = DJ_TOO_MANY;
+ break;
+ }
+
+ /*
+ * Check if next instruction is on next page, which can cause an
+ * exception.
+ *
+ * NOTE: Target-specific code must check a single instruction does not
+ * cross page boundaries; the first in the TB is always allowed to
+ * cross pages (never goes through this check).
+ */
+ if ((db->pc_first & TARGET_PAGE_MASK)
+ != (db->pc_next & TARGET_PAGE_MASK)) {
+ db->is_jmp = DJ_TOO_MANY;
+ break;
+ }
+
+ translate_block_tcg_check(db);
+ }
+
+ if (ops->tb_stop) {
+ ops->tb_stop(db, cpu);
+ }
+
+ if (db->tb->cflags & CF_LAST_IO) {
+ gen_io_end(*tcg_cpu);
+ }
+
+done_generating:
+ gen_tb_end(db->tb, db->num_insns);
+
+ translate_block_tcg_check(db);
+
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
+ qemu_log_in_addr_range(db->pc_first)) {
+ int flags;
+ if (ops->disas_flags) {
+ flags = ops->disas_flags(db);
+ } else {
+ flags = 0;
+ }
+ qemu_log_lock();
+ qemu_log("----------------\n");
+ qemu_log("IN: %s\n", lookup_symbol(db->pc_first));
+ log_target_disas(cpu, db->pc_first, db->pc_next - db->pc_first, flags);
+ qemu_log("\n");
+ qemu_log_unlock();
+ }
+#endif
+
+ db->tb->size = db->pc_next - db->pc_first;
+ db->tb->icount = db->num_insns;
+}
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v7 08/26] target: [tcg, i386] Refactor init_globals
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
` (3 preceding siblings ...)
2017-06-22 17:33 ` [Qemu-devel] [PATCH v7 04/26] target: [tcg] Add generic translation framework Lluís Vilanova
@ 2017-06-22 17:33 ` Lluís Vilanova
2017-06-22 18:06 ` [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Richard Henderson, Peter Crosthwaite,
Paolo Bonzini, Eduardo Habkost
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target/i386/translate.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 84ff49030b..f0d12a3d13 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8452,6 +8452,22 @@ static void i386_trblock_init_disas_context(DisasContextBase *db, CPUState *cpu)
#endif
}
+static void i386_trblock_init_globals(DisasContextBase *db, CPUState *cpu)
+{
+ cpu_T0 = tcg_temp_new();
+ cpu_T1 = tcg_temp_new();
+ cpu_A0 = tcg_temp_new();
+
+ cpu_tmp0 = tcg_temp_new();
+ cpu_tmp1_i64 = tcg_temp_new_i64();
+ cpu_tmp2_i32 = tcg_temp_new_i32();
+ cpu_tmp3_i32 = tcg_temp_new_i32();
+ cpu_tmp4 = tcg_temp_new();
+ cpu_ptr0 = tcg_temp_new_ptr();
+ cpu_ptr1 = tcg_temp_new_ptr();
+ cpu_cc_srcT = tcg_temp_local_new();
+}
+
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
@@ -8469,18 +8485,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
db->pc_next = db->pc_first;
i386_trblock_init_disas_context(db, cpu);
- cpu_T0 = tcg_temp_new();
- cpu_T1 = tcg_temp_new();
- cpu_A0 = tcg_temp_new();
-
- cpu_tmp0 = tcg_temp_new();
- cpu_tmp1_i64 = tcg_temp_new_i64();
- cpu_tmp2_i32 = tcg_temp_new_i32();
- cpu_tmp3_i32 = tcg_temp_new_i32();
- cpu_tmp4 = tcg_temp_new();
- cpu_ptr0 = tcg_temp_new_ptr();
- cpu_ptr1 = tcg_temp_new_ptr();
- cpu_cc_srcT = tcg_temp_local_new();
+ i386_trblock_init_globals(db, cpu);
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework
2017-06-22 17:32 [Qemu-devel] [RFC PATCH v7 00/26] translate: [tcg] Generic translation framework Lluís Vilanova
` (4 preceding siblings ...)
2017-06-22 17:33 ` [Qemu-devel] [PATCH v7 08/26] target: [tcg, i386] Refactor init_globals Lluís Vilanova
@ 2017-06-22 18:06 ` Lluís Vilanova
5 siblings, 0 replies; 13+ messages in thread
From: Lluís Vilanova @ 2017-06-22 18:06 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Peter Crosthwaite, Alex Bennée,
Richard Henderson
Please ignore, I'm having problems with my mail server and there's patches being
dropeed.
Thanks,
Lluis
Lluís Vilanova writes:
> This series proposes a generic (target-agnostic) instruction translation
> framework.
> It basically provides a generic main loop for instruction disassembly, which
> calls target-specific functions when necessary. This generalization makes
> inserting new code in the main loop easier, and helps in keeping all targets in
> synch as to the contents of it.
> This series also paves the way towards adding events to trace guest code
> execution (BBLs and instructions).
> I've ported i386/x86-64 and arm/aarch64 as an example to see how it fits in the
> current organization, but will port the rest when this series gets merged.
> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
> ---
> Changes in v7
> =============
> * Change BreakpointHitType (BH_*) for BreakpointCheckType (BC_*).
> * Move target-specific translation functions to a struct (TranslatorOps).
> * Split target-specific changes into multiple patches.
> * Rebase on edf8bc9842.
> Changes in v6
> =============
> * Rebase on upstream master (64175afc69).
> * Reorder fields in DisasContextBase to minimize padding [Richard Henderson].
> Changes in v5
> =============
> * Remove stray uses of "restrict" keyword.
> Changes in v4
> =============
> * Document new macro QTAILQ_FOREACH_CONTINUE [Peter Maydell].
> * Fix coding style errors reported by checkpatch.
> * Remove use of "restrict" in added functions; it makes older gcc versions barf
> about compilation errors.
> Changes in v3
> =============
> * Rebase on 0737f32daf.
> Changes in v2
> =============
> * Port ARM and AARCH64 targets.
> * Fold single-stepping checks into "max_insns" [Richard Henderson].
> * Move instruction start marks to target code [Richard Henderson].
> * Add target hook for TB start.
> * Check for TCG temporary leaks.
> * Move instruction disassembly into a target hook.
> * Make breakpoint_hit() return an enum to accomodate target's needs (ARM).
> Lluís Vilanova (26):
> Pass generic CPUState to gen_intermediate_code()
> queue: Add macro for incremental traversal
> cpu-exec: Avoid global variables in icount-related functions
> target: [tcg] Add generic translation framework
> target: [tcg] Redefine DISAS_* onto the generic translation framework (DJ_*)
> target: [tcg,i386] Port to DisasContextBase
> target: [tcg,i386] Refactor init_disas_context
> target: [tcg,i386] Refactor init_globals
> target: [tcg,i386] Refactor insn_start
> target: [tcg,i386] Refactor breakpoint_check
> target: [tcg,i386] Refactor disas_insn
> target: [tcg,i386] Refactor tb_stop
> target: [tcg,i386] Refactor disas_flags
> target: [tcg,i386] Replace DISAS_* with DJ_*
> target: [tcg,i386] Port to generic translation framework
> target: [tcg,arm] Replace DISAS_* with DJ_*
> target: [tcg,arm] Port to DisasContextBase
> target: [tcg,arm] Port to init_disas_context
> target: [tcg,arm] Port to init_globals
> target: [tcg,arm] Port to tb_start
> target: [tcg,arm] Port to insn_start
> target: [tcg,arm] Port to breakpoint_check
> target: [tcg,arm] Port to disas_insn
> target: [tcg,arm] Port to tb_stop
> target: [tcg,arm] Port to disas_flags
> target: [tcg,arm] Port to generic translation framework
> Makefile.target | 1
> include/exec/exec-all.h | 13 +
> include/exec/gen-icount.h | 8 -
> include/exec/translate-block.h | 125 ++++++++++
> include/qemu/queue.h | 12 +
> include/qom/cpu.h | 22 ++
> target/alpha/translate.c | 25 +-
> target/arm/translate-a64.c | 312 ++++++++++++-------------
> target/arm/translate.c | 503 ++++++++++++++++++++++------------------
> target/arm/translate.h | 38 ++-
> target/cris/translate.c | 26 +-
> target/hppa/translate.c | 6
> target/i386/translate.c | 353 +++++++++++++++-------------
> target/lm32/translate.c | 36 +--
> target/m68k/translate.c | 24 +-
> target/microblaze/translate.c | 28 +-
> target/mips/translate.c | 41 ++-
> target/moxie/translate.c | 16 +
> target/nios2/translate.c | 6
> target/openrisc/translate.c | 25 +-
> target/ppc/translate.c | 21 +-
> target/ppc/translate_init.c | 32 +--
> target/s390x/translate.c | 22 +-
> target/sh4/translate.c | 21 +-
> target/sparc/translate.c | 17 +
> target/tilegx/translate.c | 9 -
> target/tricore/translate.c | 11 -
> target/unicore32/translate.c | 26 +-
> target/xtensa/translate.c | 39 ++-
> translate-all.c | 2
> translate-block.c | 185 +++++++++++++++
> 31 files changed, 1212 insertions(+), 793 deletions(-)
> create mode 100644 include/exec/translate-block.h
> create mode 100644 translate-block.c
> To: qemu-devel@nongnu.org
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Peter Crosthwaite <crosthwaite.peter@gmail.com>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Alex Bennée <alex.bennee@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread